Power Converter with Bypass Function

Abstract

The present document relates to a power converter. The power converter may be configured to convert an input voltage at the input of the power converter into an output voltage at an output of the power converter. The power converter may comprise a pass device, a feedback circuit, and a bypass circuit. The pass device may be coupled between the input of the power converter and the output of the power converter. The feedback circuit may be configured to generate, in a voltage regulation mode, a drive signal for driving a control terminal of the pass device. The bypass circuit may be configured to apply, in a bypass mode, a predetermined voltage to the control terminal of the pass device.

Claims

1) A power converter configured to convert an input voltage at the input of the power converter into an output voltage at an output of the power converter, wherein the power converter comprises a pass device coupled between the input of the power converter and the output of the power converter, a feedback circuit configured to generate, in a voltage regulation mode, a drive signal for driving a control terminal of the pass device, a bypass circuit configured to apply, in a bypass mode, a predetermined voltage to the control terminal of the pass device.

2) The power converter according to claim 1, further comprising a comparator circuit for comparing a voltage indicative of the input voltage with a threshold voltage, wherein the power converter is configured to select between the bypass mode and the voltage regulation mode based on the result of the comparison.

3) The power converter according to claim 2, wherein the power converter is configured to switch to the bypass mode if the input voltage falls below a threshold input voltage, and switch to the voltage regulation mode if the input voltage exceeds the threshold input voltage.

4) The power converter according to claim 2, wherein the feedback circuit is configured to regulate, in the voltage regulation mode, the output voltage of the power converter towards a target output voltage.

5) The power converter according to claim 1, wherein the bypass circuit is coupled between the input of the power converter and a reference potential, and wherein the bypass circuit comprises a current source or a voltage source for generating said predetermined voltage.

6) The power converter according to claim 1, wherein the power converter is configured to operate, in the bypass mode, the pass device as a closed switch between the input of the power converter and the output of the power converter.

7) The power converter according to claim 1, wherein the feedback circuit is configured to generate, in the voltage regulation mode, the drive signal by comparing the output voltage with a reference voltage.

8) The power converter according to claim 7, wherein the feedback circuit comprises an error amplifier and an inverter circuit, wherein the error amplifier is configured to generate an error signal by comparing the output voltage with the reference voltage, and the inverter circuit is configured to generate the drive signal based on the error signal.

9) The power converter according to claim 8, wherein the inverter circuit comprises a first transistor coupled between the input of the power converter and an output of the inverter circuit, and a second transistor coupled between the output of the inverter circuit and a reference potential.

10) The power converter according to claim 8, wherein the error amplifier comprises a current source, a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein the current source is coupled between the input of the power converter and a first intermediate node, the first transistor is coupled between the first intermediate node and a second intermediate node, the second transistor is coupled between the first intermediate node and an output of the error amplifier, the third transistor is coupled between the second intermediate node and a reference potential, and the fourth transistor is coupled between the output of the error amplifier and the reference potential.

11) The power converter according to claim 1, further comprising a switching circuit configured to couple the bypass circuit or the feedback circuit to the control terminal of the pass device.

12) The power converter according to claim 1, wherein the power converter is configured to, in the bypass mode, disable the feedback circuit.

13) A method of operating a power converter, wherein the power converter converts an input voltage at the input of the power converter into an output voltage at an output of the power converter, wherein the power converter comprises a pass device, a feedback circuit, and a bypass circuit, wherein the pass device is coupled between the input of the power converter and the output of the power converter, and wherein the method comprises generating, by the feedback circuit, in a voltage regulation mode, a drive signal for driving a control terminal of the pass device, and applying, by a bypass circuit, in a bypass mode, a predetermined voltage to the control terminal of the pass device.

14) The method according to claim 13, wherein the power converter comprises a comparator circuit for comparing a voltage indicative of the input voltage with a threshold voltage, wherein the method comprises selecting between the bypass mode and the voltage regulation mode based on the result of the comparison.

15) The method according to claim 14, further comprising switching to the bypass mode if the input voltage falls below a threshold input voltage, and switching to the voltage regulation mode if the input voltage exceeds the threshold input voltage.

16) The method according to claim 14, further comprising regulating, by the feedback circuit, in the voltage regulation mode, the output voltage of the power converter towards a target output voltage.

17) The method according to claim 13, wherein the bypass circuit is coupled between the input of the power converter and a reference potential, and wherein the method comprises generating said predetermined voltage using a current source or a voltage source of the bypass circuit.

18) The method according to claim 13, further comprising operating, in the bypass mode, the pass device as a closed switch between the input of the power converter and the output of the power converter.

19) The method according to claim 13, further comprising generating, by the feedback circuit, in the voltage regulation mode, the drive signal by comparing the output voltage with a reference voltage.

20) The method according to claim 19, wherein the feedback circuit comprises an error amplifier and an inverter circuit, wherein the method comprises generating, by the error amplifier, an error signal by comparing the output voltage with the reference voltage, and generating, by the inverter circuit, the drive signal based on the error signal.

21) The method according to claim 20, wherein the inverter circuit comprises a first transistor and a second transistor, wherein the method comprises coupling the first transistor between the input of the power converter and an output of the inverter circuit, and coupling the second transistor between the output of the inverter circuit and a reference potential.

22) The method according to claim 20, wherein the error amplifier comprises a current source, a first transistor, a second transistor, a third transistor, and a fourth transistor, and wherein the method comprises coupling the current source between the input of the power converter and a first intermediate node, coupling the first transistor between the first intermediate node and a second intermediate node, coupling the second transistor between the first intermediate node and an output of the error amplifier, coupling the third transistor between the second intermediate node and a reference potential, and coupling the fourth transistor between the output of the error amplifier and the reference potential.

23) The method according to claim 13, further comprising coupling, by a switching circuit, the bypass circuit or the feedback circuit to the control terminal of the pass device.

24) The method according to claim 13, further comprising disabling the feedback circuit in the bypass mode.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar or identical elements, and in which

[0028] FIGS. 1A, 1B, 1C and 1D show an exemplary power converter and three diagrams illustrating the relation between the input voltage and the output voltage; and

[0029] FIG. 2 shows a more detailed circuit diagram of an exemplary power converter.

DESCRIPTION

[0030] FIGS. 1A, 1B, 1C and 1D show an exemplary power converter 1 and three diagrams illustrating the relation between the input voltage and the output voltage. The exemplary power converter 1 in FIG. 1A comprises a pass transistor 10 (pass device), a feedback circuit including an LDO control block 11, and a bypass circuit including voltage source 12 and comparator 13. The pass transistor 10 is coupled between the input of the power converter 1 and the output of the power converter. The LDO control block 11 generates, in a voltage regulation mode, a drive signal for driving the gate of pass transistor 10. The voltage source 12 applies, in a bypass mode, a predetermined voltage to the gate of pass transistor 10. In this way, pass transistor 10 is operated as a switch, and the power consumption of the power converter 1 is substantially reduced compared to a situation in which the power converter 1 is in drop-out (i.e. in the voltage regulation mode with a low input voltage). In bypass mode, the power converter 1 is always stable since no feedback loop is active. As another advantage of the bypass mode, the design of the LDO feedback circuit is simplified since stability must be guaranteed in a reduced voltage range (i.e. from the threshold input voltage to V.sub.IN_MAX), whereas a conventional LDO needs to be stable in the full voltage range (i.e. from 0V to V.sub.IN_MAX).

[0031] The power converter 1 further comprises a switching circuit with switches 14 and 15 for connecting either LDO control block 11 or voltage source 12 to the gate of pass transistor 10. Both switches 14 and 15 are controlled based on the output of comparator 13.

[0032] FIG. 1C shows an exemplary signal waveform of the input voltage. Depending on the relation between the target output voltage VLDO_TARGET and the threshold input voltage VIN_th, three different behaviors of the output voltage can be observed:

[0033] 1. In FIG. 1D, VLDO_TARGET<VIN_th: In that case, the output voltage will experience a STEP when the input voltage VIN crosses the threshold input voltage VIN_th. This scenario is depicted in the bottom of FIG. 1D. Main advantage of such a mode of operation is the maximum possible power efficiency because LDO drop-out operation is avoided.

[0034] 2. In FIG. 1C, VLDO_TARGET=VIN_th: In that case, the output voltage is a smooth, continuous function of the input voltage VIN. This arrangement is of particular use when a circuit at the output of the power converter 1 has requirements for low ripple of supply voltage. This scenario is depicted in the middle diagram 3.

[0035] 3. When VLDO_TARGET>VIN_th: Again, the output voltage will be a smooth continuous function of the input voltage VIN, as in case 2, but IQ of the regulator may increase substantially. This case may not show any advantage compared to the previous two cases. This scenario is not depicted in FIG. 1B, 1C or 1D.

[0036] In general, there are three main classes of power management circuits that can be distinguished: Switch Mode Power Supplies, linear regulators (in particular, regulators with low voltage drop over regulating power device, called LDO) and power switches. For the goal of safety and better power utilization, a new type of power management circuit is derived within this document from the combination of power switch and LDO. The same power device can work as a switch and output voltage regulating device. Thus, the power converter presented in this document has a bypass mode and voltage regulation mode (LDO mode) of operation.

[0037] FIG. 2 shows a more detailed circuit diagram of an exemplary power converter 2. In FIG. 2, the LDO control block 10 of FIG. 1 is implemented with the help of current source ib1 21, transistors M1-M6 22, 23, 24, 25, 26, 27, and resistor divider R1, R2. In particular, current source ib1 and transistors M1-M4 form an error amplifier for comparing a scaled version of the output voltage vLDO-out with the reference voltage V.sub.REF, and for amplifying the difference between the latter signals. Transistors M5 and M6 form a buffer (inverter circuit). Comparator 13, Zener Diode 29 and current source 28 form the bypass circuit which applies a constant voltage to the gate of pass device 10 if the comparator 13 decides that the power converter 2 is in the bypass mode. The breakdown voltage (e.g. 5V) of the Zener diode may be smaller than the breakdown voltage of the gate-oxid of the pass device 10 (e.g. 5.5V). In FIG. 2, the switching circuitry comprises a switch 16 in addition to the two switches 14 and 14 which are displayed in FIG. 1. Switch 16 may be regarded as isolation switch for stopping current flow through the buffer. In addition, power converter 2 may comprise an additional isolation switch (not shown) for disabling the error amplifier. Such an additional isolation switch may be coupled e.g. in series to the current source ib1.

[0038] The comparator 13 defines the mode of operation of the power converter 2 by opening and closing switches Sw1-Sw3. When VIN>VIN_th, comparator 13 closes Sw1-Sw2 and opens Sw3 and thereby allows negative feedback, from the output, to stabilize the output voltage vLdo_out and limits the output voltage to a safe level of VOUT TARGET (i.e. the target output voltage). When VIN<VIN_th, switch Sw3 is closed and Sw1-Sw2 are opened. In that case, the gate-source voltage VGS of pass device pwrPmos is constant and defined by breakdown of Zener diode DZ or the input voltage VIN (whatever is smaller).

[0039] The example schematic in FIG. 2 illustrates increased current consumption in case VIN gets close to VLDO_TARGET. If we assume that VIN is getting low, the drop over pwrPmos might become lower and lower such that the output voltage stays stable and equal to VLDO_TARGET. This may be achieved by increasing current through the diode connected M6. When VIN gets equal or lower than VLDO_TARGET, than feedback loop, in an attempt to keep the output voltage at VLDO_TARGET, will pull pGate as low as possible, causing significant increase of the current in the branch comprising Sw1, M5, M6. In this condition (VIN<VLDO_TARGET), current trough M6 is maximum and independent from output load. This maximum current is defined by the size of M6, which in turn, is defined by the requirements for stable operation of the LDO. Entering the bypass mode when VIN<VLDO_TARGET will solve this high IQ issue, because Ib2 can be very small. Finally, it should be mentioned that the target output voltage VLDO_TARGET and the threshold input voltage (VIN_th) may be defined independently to optimize the performance of power converter 2.

[0040] It should be noted that the description and drawings merely illustrate the principles of the proposed methods and systems. Those skilled in the art will be able to implement various arrangements that, although not explicitly described or shown herein, embody the principles of the invention and are included within its spirit and scope. Furthermore, all examples and embodiment outlined in the present document are principally intended expressly to be only for explanatory purposes to help the reader in understanding the principles of the proposed methods and systems. Furthermore, all statements herein providing principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.