Array power supply-based screening of static random access memory cells for bias temperature instability

Abstract

A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both). Asymmetric bias voltages applied to the transistors in this manner will reduce the transistor drive current, and can thus mimic the effects of bias temperature instability (BTI). Cells that are vulnerable to threshold voltage shift over time can thus be identified.

Claims

1. A method of making an integrated circuit, the integrated circuit including a microprocessor and a memory array, the memory array including memory cells arranged in rows and columns, each memory cell comprising first and second cross-coupled inverters and a first pass transistor, each column of memory cells associated with a first bit line coupled to the first pass transistor of each memory cell in the column, each row of memory cells associated with a word line coupled to gates of the pass transistors of the memory cells in the row; wherein, in operation, the first and second inverters are each biased from first and second array bias nodes; the method comprising: providing a wafer having one or more of the integrated circuits; writing a first data state to a selected memory cell of the integrated circuit under normal bias conditions; applying, after the writing, a reduced bias at the first array bias node of the first inverter of the selected memory cell relative to a bias applied at the first array bias node of the second inverter of the selected memory cell, during the applying step the selected memory cell is accessed; determining whether the access of the selected memory cell failed; and packaging the integrated circuit if fewer than a limit of memory cells has failed the access.

2. The method of claim 1, further comprising: prior to the writing step, applying a normal bias voltage to the first and second array bias nodes of each of the first and second inverters of the selected memory cell; and wherein the applying step comprises: applying a reduced bias voltage at the first array bias node of the first inverter of the selected memory cell while applying a normal bias voltage at the first array bias node of the second inverter of the selected memory cell.

3. The method of claim 2, further comprising: then applying a normal bias voltage to the first and second array bias nodes of each of the first and second inverters of the selected memory cell; then writing a second data state to the selected memory cell; and applying a reduced bias voltage at the first array bias node of the second inverter of the selected memory cell while applying a normal bias voltage at the first array bias node of the first inverter of the selected memory cell; during the step of applying the reduced bias voltage at the first array bias node of the second inverter, accessing the selected memory cell.

4. The method of claim 3, further comprising: repeating the applying, writing, and accessing steps for both the first and second data states for each of the memory cells in the memory array.

5. The method of claim 1, wherein the first inverter in the selected memory cell comprises: a first load; and a first n-channel driver transistor having a gate, and having a source/drain path connected to the first load at a first storage node, the first load and the source/drain path of the first driver transistor connected in series between an array power supply node and a first array ground node; wherein the second inverter in the selected memory cell comprises: a second load; and a second n-channel driver transistor having a gate connected to the first storage node, and having a source/drain path connected to the second load at a second storage node, the second storage node being connected to the gate of the first driver transistor, the second load and the source/drain path of the second driver transistor connected in series between the array power supply node and a second array ground node; wherein the first array bias node of the first inverter corresponds to the first array ground node; and wherein the first array bias node of the second inverter corresponds to the second array ground node.

6. The method of claim 5, wherein the first data state corresponds to the first storage node at a low voltage and the second storage node at a high voltage; wherein the first pass transistor is coupled between the first storage node and the first bit line; wherein the applying step comprises: raising the voltage at the first array ground node to a voltage above the voltage of the second array ground node; wherein the accessing step comprises: energizing the word line coupled to the gate of the first pass transistor of the selected memory cell; the method further comprising: then applying a normal bias voltage to the first and second array ground nodes of the selected memory cell; and reading the state of the selected memory cell.

7. The method of claim 5, wherein the first data state corresponds to the first storage node at a low voltage and the second storage node at a high voltage; wherein the applying step comprises: raising the voltage at the first array ground node to a voltage above the voltage of the second array ground node; and wherein the accessing step further comprises: reading the state of the selected memory cell.

8. The method of claim 5, wherein the first data state corresponds to the first storage node at a low voltage and the second storage node at a high voltage; wherein each memory cell further comprises a second pass transistor coupled between the second storage node and a second bit line associated with the column associated with the memory cell, and having a gate coupled to the word line for the row associated with the memory cell; wherein the applying step comprises: raising the voltage at the second array ground node to a voltage above the voltage of the first array ground node; wherein the accessing step comprises: writing a second data state to the selected memory cell, the second data state corresponding to the second storage node at a low voltage and the first storage node at a high voltage; then applying a normal bias voltage to the first and second array ground nodes; and reading the state of the selected memory cell.

9. The method of claim 1, wherein the first inverter in the selected memory cell comprises: a first p-channel load transistor having a gate, and having a source/drain path; and a first n-channel driver transistor having a gate connected to the gate of the first load transistor, and having a source/drain path connected to the source/drain path of the first load transistor at a first storage node so that the source/drain paths of the first load transistor and the first driver transistor are connected in series between a first array power supply node and an array ground node; wherein the second inverter in the selected memory cell comprises: a second p-channel load transistor having a gate, and having a source/drain path; and a second n-channel driver transistor having a gate connected to the gate of the second load transistor and connected to the first storage node, having a source/drain path connected to the source/drain path of the second load transistor at a second storage node so that the source/drain paths of the second load transistor and the second driver transistor are connected in series between a second array power supply node and an array ground node, and the second storage node connected to the gates of the first load transistor and the first driver transistor; wherein the first array bias node of the first inverter corresponds to the first array power supply node; and wherein the first array bias node of the second inverter corresponds to the second array power supply node.

10. The method of claim 9, wherein the first data state corresponds to the first storage node at a low voltage and the second storage node at a high voltage; wherein the first pass transistor is coupled between the first storage node and the first bit line; wherein the applying step comprises: lowering the voltage at the second array power supply node to a voltage below the voltage of the first array power supply node; wherein the accessing step comprises: energizing the word line coupled to the gate of the first pass transistor of the selected memory cell; the method further comprising: then applying a normal bias voltage to the first and second array power supply nodes of the selected memory cell; and reading the state of the selected memory cell.

11. The method of claim 9, wherein the first data state corresponds to the first storage node at a low voltage and the second storage node at a high voltage; wherein the applying step comprises: lowering the voltage at the second array power supply node to a voltage below the voltage of the first array power supply node; and wherein the accessing step further comprises: reading the state of the selected memory cell.

12. The method of claim 9, wherein the first data state corresponds to the first storage node at a low voltage and the second storage node at a high voltage; wherein each memory cell further comprises a second pass transistor coupled between the second storage node and a second bit line associated with the column associated with the memory cell, and having a gate coupled to the word line for the row associated with the memory cell; wherein the applying step comprises: lowering the voltage at the first array power supply node to a voltage below the voltage of the second array power supply node; wherein the accessing step comprises: writing a second data state to the selected memory cell, the second data state corresponding to the second storage node at a low voltage and the first storage node at a high voltage; the method further comprising: then applying a normal bias voltage to the first and second array power supply nodes of the selected memory cell; and reading the state of the selected memory cell.

13. The method of claim 9, wherein the source/drain paths of the first load transistor and the first driver transistor are connected in series between a first array power supply node and a first array ground node; wherein the source/drain paths of the second load transistor and the second driver transistor are connected in series between a second array power supply node and a second array ground node; wherein the first bias voltage node of the first inverter corresponds to the first array ground node; wherein the first bias voltage node of the second inverter corresponds to the second array ground node; and wherein the applying step comprises: raising the voltage at the first array ground node to a voltage above the voltage of the second array ground node; and lowering the voltage at the second array power supply node to a voltage below the voltage of the first array power supply node.

14. The method of claim 1, wherein if the selected memory cell has failed the test method then the selected memory cell is repaired by replacing it with an available redundant memory cell.

15. A method of making an integrated circuit having memory cells arranged in rows and columns in a memory array, each memory cell comprising first and second cross-coupled inverters and a first pass transistor, each column of memory cells associated with a first bit line coupled to the first pass transistor of each memory cell in the column, each row of memory cells associated with a word line coupled to gates of the pass transistors of the memory cells in the row; wherein, in operation, the first and second inverters are each biased from first and second array bias nodes; the method comprising: providing a wafer having one or more of the integrated circuits; applying a normal bias voltage to the first and second inverters of a selected memory cell of the integrated circuit; then writing a first data state to the selected memory cell; then applying after the writing, for a selected duration, an asymmetric reduced bias to the first and second inverters so that the voltage between the first and second array bias nodes of the first inverter of the selected memory cell differs from the voltage between the first and second array bias nodes of the second inverter of the selected memory cell; applying a normal bias voltage to the first and second inverters of a selected memory cell; reading the state of the selected memory cell; determining whether the reading of the selected memory cell failed; and packaging the integrated circuit if fewer than a limit of memory cells has failed the reading.

16. The method of claim 15, wherein the first inverter in the selected memory cell comprises: a first load; and a first n-channel driver transistor having a gate, and having a source/drain path connected to the first load at a first storage node, the first load and the source/drain path of the first driver transistor connected in series between an array power supply node and a first array ground node; wherein the second inverter in the selected memory cell comprises: a second load; and a second n-channel driver transistor having a gate connected to the first storage node, and having a source/drain path connected to the second load at a second storage node, the second storage node being connected to the gate of the first driver transistor, the second load and the source/drain path of the second driver transistor connected in series between the array power supply node and a second array ground node; wherein the first data state corresponds to the first storage node at a low voltage and the second storage node at a high voltage; and wherein the applying step comprises: applying a normal ground voltage to the second array ground node while applying a voltage above the normal ground voltage to the first array ground node; and applying a reduced voltage below a normal array power supply voltage to the array power supply node for the selected duration.

17. The method of claim 15, wherein the first inverter in the selected memory cell comprises: a first load; and a first n-channel driver transistor having a gate, and having a source/drain path connected to the first load at a first storage node, the first load and the source/drain path of the first driver transistor connected in series between a first array power supply node and an array ground node; wherein the second inverter in the selected memory cell comprises: a second load; and a second n-channel driver transistor having a gate connected to the first storage node, and having a source/drain path connected to the second load at a second storage node, the second storage node being connected to the gate of the first driver transistor, the second load and the source/drain path of the second driver transistor connected in series between a second array power supply node and the array ground node; wherein the first data state corresponds to the first storage node at a low voltage and the second storage node at a high voltage; and wherein the applying step comprises: applying, for the selected duration, a first reduced array power supply voltage to the first array power supply node while applying a second reduced array power supply voltage lower than the first reduced array power supply voltage to the second array power supply node.

18. The method of claim 15, wherein the selected duration is 100 milliseconds.

19. The method of claim 15, wherein if the selected memory cell has failed the test method then the selected memory cell is repaired by replacing it with an available redundant memory cell.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

(1) FIG. 1 is an electrical diagram, in schematic form, of a conventional static random access memory (SRAM) cell.

(2) FIG. 2 is an electrical diagram, in block form, of an integrated circuit including one or more memory resources suitable for testing according to embodiments of this invention.

(3) FIG. 3 is an electrical diagram, in block form, of a memory in the integrated circuit of FIG. 2 suitable for testing according to embodiments of this invention.

(4) FIG. 4a is an electrical diagram, in schematic form, of an SRAM cell suitable for testing according to an embodiment of this invention.

(5) FIG. 4b is an electrical diagram, in schematic form, of bias voltage select circuitry used in connection with the SRAM cell of FIG. 4a according to that embodiment of the invention.

(6) FIG. 4c is a plan view of a portion of the memory of FIG. 3 including the SRAM cell of FIG. 4a according to that embodiment of the invention.

(7) FIG. 5a is an electrical diagram, in schematic form, of an SRAM cell suitable for testing according to another embodiment of this invention.

(8) FIG. 5b is an electrical diagram, in schematic form, of bias voltage select circuitry used in connection with the SRAM cell of FIG. 5a according to that embodiment of the invention.

(9) FIG. 5c is a plan view of a portion of the memory of FIG. 3 including the SRAM cell of FIG. 5a according to that embodiment of the invention.

(10) FIG. 6 is an electrical diagram, in schematic form, of an SRAM cell suitable for testing according to another embodiment of this invention.

(11) FIG. 7 is a flow diagram of a method of testing the memory of FIG. 3 according to embodiments of this invention.

(12) FIGS. 8a through 8d are flow diagrams of screens within the test method of FIG. 6, according to an embodiment of this invention.

DETAILED DESCRIPTION OF THE INVENTION

(13) This invention will be described in connection with certain embodiments, namely as implemented into a method of testing static random access memories, because it is contemplated that this invention will be especially beneficial when used in such an application. However, it is also contemplated that embodiments of this invention will also be beneficial if applied to memories of other types, including read-only memories and electrically programmable read-only memories, among others. Furthermore, it is contemplated that embodiments of this invention may be used to test and screen circuit functions other than memories, including especially digital logic functions. Accordingly, it is to be understood that the following description is provided by way of example only, and is not intended to limit the true scope of this invention as claimed.

(14) FIG. 2 illustrates an example of large-scale integrated circuit 10, in the form of a so-called “system-on-a-chip” (“SoC”), as now popular in many electronic systems. Integrated circuit 10 is a single-chip integrated circuit into which an entire computer architecture is realized. As such, in this example, integrated circuit 10 includes a central processing unit of microprocessor 12, which is connected to system bus SBUS. Various memory resources, including random access memory (RAM) 18 and read-only memory (ROM) 19, reside on system bus SBUS and are thus accessible to microprocessor 12. In many modern implementations, ROM 19 is realized by way of electrically erasable programmable read-only memory (EEPROM), a common type of which is referred to as “flash” EEPROM. As will be described in further detail below, realization of at least part of ROM 19 as flash EEPROM can facilitate the implementation and operation of embodiments of this invention. In any case, ROM 19 typically serves as program memory, storing the program instructions executable by microprocessor 12, while RAM 18 serves as data memory; in some cases, program instructions may reside in RAM 18 for recall and execution by microprocessor 12. Cache memory 16 (such as level 1, level 2, and level 3 caches, each typically implemented as SRAM) provides another memory resource, and resides within microprocessor 12 itself and therefore does not require bus access. Other system functions are shown, in a generic sense, in integrated circuit 10 by way of system control 14 and input/output interface 17.

(15) Those skilled in the art having reference to this specification will recognize that integrated circuit 10 may include additional or alternative functions to those shown in FIG. 2, or may have its functions arranged according to a different architecture from that shown in FIG. 2. The architecture and functionality of integrated circuit 10 is thus provided only by way of example, and is not intended to limit the scope of this invention.

(16) Further detail in connection with the construction of RAM 18 in integrated circuit 10 is illustrated in FIG. 3. Of course, a similar construction may be used to realize other memory resources such as cache memory 16 further in the alternative, RAM 18 may correspond to a stand-alone memory integrated circuit (i.e., rather than as an embedded memory as shown in FIG. 2). Those skilled in the art having reference to this specification will comprehend that the memory architecture of RAM 18 in FIG. 3 is provided by way of example only.

(17) In this example, RAM 18 includes many memory cells arranged in rows and columns within memory array 20. While a single instance of memory array 20 is shown in FIG. 3, it is to be understood that RAM 18 may include multiple memory arrays 20, each corresponding to a memory block within the address space of RAM 18. In the example shown in FIG. 3, memory array 20 includes m rows and n columns of SRAM cells, with cells in the same column sharing a pair of bit lines BLT[n-1:0], BLB[n-1:0], and with memory cells in the same row sharing one of word lines WL[m-1:0]. Bit line precharge circuitry 27 is provided to apply a desired precharge voltage to the pairs of bit lines BLT[n-1:0], BLB[n-1:0] in advance of read and write operations. Row decoder 25 receives a row address value indicating the row of memory array 20 to be accessed, and energizes the one of word lines WL[m-1:0] corresponding to that row address value. Column select circuit 22 receives a column address value, and in response selects pairs of bit lines BLT[n-1:0], BLB[n-1:0] associated with one or more columns to be placed in communication with read/write circuits 24. Read/write circuits 24 are constructed in the conventional manner, for example to include the typical differential amplifier coupled to the bit lines for a column as selected by column select circuit 22 and a write circuit for selectively pulling toward ground one of the bit lines in the selected pair. The example of RAM 18 shown in FIG. 3 is constructed to an “interleaved” architecture, in which a given memory address selects one of every x (e.g., one of every four) columns for read or write access. The data words stored in memory array 20 are thus interleaved with one another, in the sense that the memory address decoded (in part) by column select circuit 22 selects one column in each group of columns, along the selected row. Alternatively, memory array 20 may be arranged in a non-interleaved fashion, in which each cell in the selected row is coupled to a corresponding read/write circuit in each cycle. In that architecture, read/write circuits 24 could reside between bit lines BL[n-1:0], and column select circuits 22, with the column select circuits selecting which read/write circuits 24 (and thus which columns) are in communication with data bus DATA I/O.

(18) As discussed above in connection with the Background of the Invention, modern integrated circuits are now commonly constructed with extremely small minimum sized features, for example with metal-oxide-semiconductor (MOS) transistor gates having widths deep in the sub-micron regime. While these small feature sizes provide tremendous cell density and, in many respects, high device performance, reliability and stability issues also result from such scaling. As such, it has become no less important to properly screen, at the time of manufacture, memory arrays and other circuit functions in order to identify and repair, or remove from the population, those memory cells and devices that are vulnerable to failing the desired specifications over operating life. For RAM 18 constructed as described above, measures such as static noise margin, writeability, read current, and the like are of particular concern over the expected operating life.

(19) Furthermore, the extreme thinness required of conventional gate dielectric layers (e.g., silicon dioxide) as transistor feature sizes have scaled into the deep submicron realm has rendered those materials unusable in many cases. In response, so-called “high-k” gate dielectrics, such as hafnium oxide (HfO.sub.2), have higher dielectric constants than silicon dioxide and silicon nitride, permitting those films to be substantially thicker than the corresponding silicon dioxide gate films while remaining suitable for use in high performance MOS transistors. Gate electrodes of metals and metal compounds, such as titanium nitride, tantalum-silicon-nitride, tantalum carbide, and the like are now also popular in modern MOS technology, especially in combination with high-k gate dielectrics. These metal gate electrodes eliminate effects such as polysilicon depletion, such effects being noticeable at the extremely small feature sizes required of these technologies. As discussed above, it has been observed that modern high-k metal gate n-channel MOS transistors are susceptible to both negative bias temperature instability (“NBTI”) and positive bias temperature instability (“PBTI”).

(20) Accordingly, it would be useful to screen CMOS SRAM cells to identify and repair, or discard, those memory cells and memories that are sufficiently marginal in static noise margin, writeability, and read current, among other attributes, that transistor degradation over the expected operating life would result in the loss of a stored data state, a read failure, or a write failure. It is particularly useful to provide such a screen in the case of SRAM cells constructed of high-k gate dielectric metal gate n-channel MOS transistors, due to their additional susceptibility to PBTI. Regardless of the screen, it is important to the manufacturer that such screens accurately test for the contemplated degradation mechanisms and effects, without significant overkill and thus undue yield loss.

(21) Conventional SRAM cells and memories are not constructed to readily screen for these measures, especially as those measures may be affected by PBTI at the n-channel driver transistors. As such, conventional test vectors necessarily incorporate certain “proxies” for the effects of shifting device parameters, such as shifts in threshold voltage of n-channel driver transistors of SRAM cells. However, in order to properly screen for such effects as BTI, especially at the extremes of the temperature range, it has been observed that conventional test vectors often present an unrealistic bias condition to the cells under test. Such unrealistic test vectors have been observed to introduce other unintended effects and failure modes for the cells, beyond those related to transistor threshold shift. In addition, the necessary test vector voltages that may be applied by level shifters and other peripheral circuits in the memory architecture are often limited, by virtue of the design and capability of those peripheral circuits.

(22) According to embodiments of this invention, CMOS SRAM cells are constructed to enable a more direct screen for bias temperature instability (BTI) in the cell transistors. FIG. 4a illustrates an example of the construction of memory cell 30.sub.jk of memory array 20, according to embodiments of this invention. Cell 30.sub.jk includes, in the conventional manner, one CMOS inverter constructed from series-connected p-channel load transistor 33a and n-channel driver transistor 34a, and another CMOS inverter of series-connected p-channel load transistor 33b and n-channel transistor 34b. The gates of transistors 33a, 34a in one inverter are connected together and to the common drain node of transistors 33b, 34b of the opposite inverter at storage node SNB; similarly, the gates of transistors 33b, 34b are connected together and to the common drain node of transistors 33a, 34a at storage node SNT. N-channel pass-gate transistors 35a, 35b have their source/drain paths connected between storage nodes SNT, SNB, respectively, and respective bit lines BLT.sub.k, BLB.sub.k for column k of array 20. Word line WL.sub.j for row j controls the gates of transistors 35a, 35b. Alternatively, in embodiments of this invention, cell 30.sub.jk may be constructed in a “single-sided” manner, in which case only a single pass-gate transistor coupling one of the storage nodes SNT, SNB to a single bit line will be provided.

(23) According to embodiments of this invention, the source nodes of driver transistor 34a and driver transistor 34b are connected to separate array ground voltage nodes V.sub.SSAa, V.sub.SSAb, respectively. The source nodes of load transistors 33a, 33b are connected in common to array power supply voltage node V.sub.DDA, and the body nodes of n-channel driver transistors 34a, 34b, and n-channel pass transistors 35a, 35b, are connected together and biased by a voltage V.sub.gnd. As will be described below, these separate ground voltage nodes V.sub.SSAa, V.sub.SSAb enable transistors 34a, 34b to be placed under different biases from one another. It is contemplated that the application of asymmetric transistor biases by way of different array ground voltage nodes V.sub.SSAa, V.sub.SSAb during functional test can mimic threshold voltage shifts at a corresponding one of driver transistors 34a, 34b, and also to some extent at a corresponding one of pass transistors 35a, 35b. More specifically, the application of a voltage above array ground voltage V.sub.gnd at one of array ground voltage nodes V.sub.SSAa, V.sub.SSAb will reduce the bias (i.e., the gate-to-source voltage or drain-to-source voltage, or both) applied at its corresponding driver transistor 34a, 34b, and perhaps also the bias at its corresponding pass transistor 35a, 35b, reducing the drive strength of that transistor or transistors relative to transistors continuing to receive the full bias of a nominal ground voltage. The reduced drive strength can thus mimic the effect of a higher threshold voltage at the affected transistors, and thus the effect of PBTI degradation of those devices as may occur over operating life.

(24) According to this embodiment of the invention, circuitry is provided outside of memory array 20 to control the application of voltages to array ground voltage nodes V.sub.SSAa, V.sub.SSAb. FIG. 4b illustrates an example of ground voltage select circuitry 40 suitable for use in connection with this embodiment of the invention. As evident from FIG. 4b, ground voltage select circuitry 40 resides outside of memory array 20, and applies a selected voltage to each of array ground voltage nodes V.sub.SSAa, V.sub.SSAb, in response to control signals SCRN_a, SCRN_b, and EQ generated by control circuitry (not shown) elsewhere in RAM 18 or integrated circuit 10 (e.g., system control 14). It is contemplated that those skilled in the art having reference to this specification will be readily able to generate the appropriate levels of control signals SCRN_a, SCRN_b, EQ for carrying out the normal operation and screen functions described below in this specification.

(25) As shown in FIG. 4b, ground voltage select circuitry 40 receives two power supply voltages as inputs, namely normal ground voltage V.sub.gnd (which, in this example, is the bias voltage applied to body nodes of n-channel transistors 34, 35 in cell 30.sub.jk as discussed above) and screen ground voltage V.sub.SS_SCRN. It is contemplated that voltage regulator or level shift circuitry elsewhere in RAM 18 or integrated circuit 10 can generate screen ground voltage V.sub.SS_SCRN at a different (i.e., higher) voltage than normal ground voltage V.sub.gnd. On its array side, ground voltage select circuitry 40 is connected to array ground voltage nodes V.sub.SSAa, V.sub.SSAb; as such, the function of ground voltage select circuitry 40 is to apply the appropriate ones of normal ground voltage V.sub.gnd and screen ground voltage V.sub.SSA_SCRN to array ground voltage nodes V.sub.SSAa, V.sub.SSAb for the particular operating mode or screen during test.

(26) In this embodiment of the invention, ground voltage select circuitry 40 includes n-channel MOS pass transistor 42a having its source/drain path connected between screen ground voltage V.sub.SSA_SCRN and array ground voltage node V.sub.SSAa, and n-channel pass transistor 44a having its source/drain path connected between normal ground voltage V.sub.gnd and array ground voltage node V.sub.SSAa. The gate of transistor 42a receives control signal SCRN_a, and the gate of transistor 44a receives the logical complement of control signal SCRN_a (via inverter 41a). Similarly, n-channel pass transistor 42b has its source/drain path connected between screen ground voltage V.sub.SSA_SCRN and array ground voltage node V.sub.SSAb, and n-channel pass transistor 44b has its source/drain path connected between normal ground voltage V.sub.gnd and array ground voltage node V.sub.SSAb. The gate of transistor 42b receives control signal SCRN_b, and the gate of transistor 44b receives the logical complement of control signal SCRN_b (via inverter 41b). Equalization transistor 43 is an n-channel transistor with its source/drain path connected between array ground voltage nodes V.sub.SSAa and V.sub.SSAb, and its gate receiving equalization signal EQ. Equalization signal EQ may be generated by external control circuitry as noted above, or alternatively may be produced by logic circuitry according to control signals SCRN_a, SCRN_b (e.g., the logical AND of the outputs of inverters 41a, 41b).

(27) In normal operation, control signals SCRN_a, SCRN_b will both be inactive at a low logic level. Transistors 42a, 42b will both be off, and transistors 44a, 44b will both be on, in ground voltage select circuitry 40. This will apply normal ground voltage V.sub.gnd to both of array ground voltage nodes V.sub.SSAa, V.sub.SSBb. In this normal mode, it is contemplated that equalization control signal EQ will be active at a high logic level, turning on equalization transistor 43 to ensure symmetric application of normal ground voltage V.sub.gnd to array ground voltage nodes V.sub.SSAa, V.sub.SSBb. In operation during test, for example to carry out an asymmetric bias screen in the manner described in further detail below, one or the other of control signals SCRN_a, SCRN_b will be asserted active, while the other remains inactive. For example, in response to control signal SCRN_a being driven active and control signal SCRN_b remaining inactive, transistor 42a will be turned on and transistor 44a will be off, which connects screen ground voltage V.sub.SSA_SCRN to array ground voltage node V.sub.SSAa; transistors 42b, 44b will be off and on, respectively, connecting normal ground voltage V.sub.gnd to array ground voltage node V.sub.SSAb. Equalization transistor 43 will be turned off in this situation (equalization signal EQ inactive), to allow array ground voltage nodes V.sub.SSAa, V.sub.SSAb to reach different voltages from one another, and thus result in an asymmetric bias at cells 30 in memory array 20. Conversely, with control signal SCRN_b active and control signal SCRN_a inactive, array ground voltage node V.sub.SSAb will receive screen ground voltage V.sub.SSA_SCRN and array ground voltage node V.sub.SSAa will receive normal ground voltage V.sub.gnd.

(28) It is contemplated that multiple cells 30 within memory array 20 will receive array ground voltage nodes V.sub.SSAa, V.sub.SSAb according to this embodiment of the invention. For example, it is contemplated that every cell 30 within memory array 20 will receive array ground voltage nodes V.sub.SSAa, V.sub.SSAb in similar manner as described above for the case of cell 30.sub.jk of FIG. 4a. Alternatively, it is contemplated that multiple instances of ground voltage select circuitry 40, and thus multiple instances of paired array ground voltage nodes V.sub.SSAa, V.sub.SSAb, may be provided in connection with memory array 30. In any event, it is contemplated that cells 30 in the same column k as cell 30.sub.jk (or in the same row j, depending on the orientation of memory array 20 relative to the run of conductors corresponding to array ground voltage nodes V.sub.SSAa, V.sub.SSAb) will share array ground voltage nodes V.sub.SSAa, V.sub.SSAb.

(29) It is contemplated that conductors corresponding to array ground voltage nodes V.sub.SSAa, V.sub.SSAb can be readily routed through memory array 20, providing the capability for the PBTI screens described in further detail below, without significantly increasing the chip area required for these separate conductors. FIG. 4c illustrates an example of the layout of cell 30.sub.jk of FIG. 4a, and portions of its immediately adjacent cells within the same row j (i.e., in columns k−1 and k+1) as constructed at the surface of a silicon substrate, fabricated according to CMOS technology and according to an embodiment of this invention, and at a stage in the manufacture prior to the formation of overlying metal layers. As will become apparent, chip area efficiency is accomplished by routing array ground voltage node conductors so that cells in adjacent columns can share a common array ground voltage node conductor, as will now be described.

(30) In the plan view of FIG. 4c, active regions 54 are locations of the surface of an n-well or a p-well, as the case may be, at which dielectric isolation structures 53 are not present. As known in the art, isolation dielectric structures 53 are relatively thick structures of silicon dioxide or another dielectric material, intended to isolation transistor source and drain regions in separate transistors from one another. Isolation dielectric structures 53 are typically formed by way of shallow trench isolation (STI) structures in modern high-density integrated circuits, or alternatively by the well-known local oxidation of silicon (LOCOS) process. FIG. 4c illustrates the boundaries of p-wells 52 and n-wells 55, within which active regions 54 are defined. These well regions will receive the appropriate body node bias via metal conductors (not shown), in the conventional manner.

(31) As well known in the art, transistors are formed at locations of active regions 54 that underlie gate elements 56, separated therefrom by gate dielectric material (not visible in FIG. 4c). Various materials may be used for gate element 56 and for this gate dielectric, as described above. Commonly used materials include polycrystalline silicon for gate element 56, and silicon dioxide or silicon nitride (or a combination of the two) for the gate dielectric. Those conventional materials are suitable for use with embodiments of this invention. High-k dielectric materials such as hafnium oxide (HfO.sub.2) are becoming favored for use in high-performance transistors, in combination with metals or conductive metal compounds for gate elements 56, examples of which include titanium nitride, tantalum silicon nitride, and tantalum carbide. Other examples of these high-k gate dielectric materials and metal gate materials are known in the art. It is contemplated that embodiments of this invention are especially well-suited for use in connection with such modern transistor materials, particularly considering that these embodiments of the invention can readily screen for device instabilities such as PBTI, to which transistors using those modern materials have been observed to be susceptible.

(32) FIG. 4c illustrates the locations of contact openings 58 that extend through overlying insulator material (not shown) to active regions 54 or to gate elements 56 at the case may be. Metal conductors (e.g., those shown schematically in FIG. 4c for storage nodes SNT, SNB) will be patterned to form conductors that overlie the structure, making contact to active regions 54 or gate elements 56 (or both) via respective contact openings 58.

(33) FIG. 4c illustrates the outline of the various transistors 33, 34, 35 within cell 30.sub.jk, corresponding to the electrical schematic of FIG. 4a. It is contemplated that those skilled in the art will be able to follow the schematic of FIG. 4a within the layout of FIG. 4c. The orientation of the plan view of FIG. 4a is such that cell 30.sub.jk in row m and column k is highlighted. Above and below SRAM cell 30.sub.m,k are cells 30.sub.m,k−1, 30.sub.m,k+1, which also reside in the same row m but in columns k and k+1, respectively. SRAM cell 30.sub.m+1,k is along the right-hand side of cell 30.sub.m,k, residing in the same column k but in neighboring row m+1.

(34) As mentioned above, the metal conductor schematically shown as storage node SNB connects active region 54 at the drain of transistor 34b and one side of pass transistor 35b to active region 54 at the drain of transistor 33b and to gate element 56 serving as the gate of transistors 33a, 34a (via a shared contact opening 58). Similarly, the metal conductor schematically shown as storage node SNT connects active region 54 between transistors 34a, 35a to active region 54 at the drain of transistor 33a, and (via shared contact opening 58) to gate element 56 serving as the gates of transistors 33b, 34b. The routing of array power supply node conductor V.sub.DDA is illustrated in FIG. 4c, including those locations at which it makes contact (via contact openings 58) to the source nodes of transistors 34a, 34b. Bit lines BLT.sub.k, BLB.sub.k, and word line WL.sub.j are connected, via metal conductors (not shown) and contact openings 58 to the appropriate elements within cell 30.sub.jk as shown in FIG. 4c, according to the electrical schematic of FIG. 4a.

(35) According to this embodiment of the invention, metal conductors for array ground voltage nodes V.sub.SSAa, V.sub.SSAb run parallel to the conductor for array power supply voltage node V.sub.DDA, as shown schematically in FIG. 4c. The metal conductor for array ground voltage node V.sub.SSAa connects, via contact openings 58, to the source node of transistor 34a in cell 30.sub.jk and also to the source node of transistor 34a of cell 30.sub.j,k+1 in adjacent column k+1. Similarly, the metal conductor for array ground voltage node V.sub.SSAb connects, via contact openings 58, to the source node of transistor 34b in cell 30.sub.jk and also to the source node of transistor 34b of cell 30.sub.j,k−1 in adjacent column k−1. As such, it is contemplated that separate array ground voltage nodes V.sub.SSAa, V.sub.SSAb within memory array 20 can be implemented with little if any impact on the overall cell chip area.

(36) Referring now to FIGS. 5a through 5c, the construction of SRAM cell 30′.sub.jk and associated support circuitry within RAM 18 according to another embodiment of this invention will now be described in detail. Cell 30′.sub.jk is constructed in similar manner as cell 30.sub.jk of FIG. 4a, with a pair of cross-coupled CMOS inverters, one of which consisting of p-channel load transistor 33a and n-channel driver transistor 34a, and the other as p-channel load transistor 33b and n-channel transistor 34b. The cross-coupling of these two inverters is effected by the gates of transistors 33a, 34a both connected to the common drain node of transistors 33b, 34b together at storage node SNB, and by the gates of transistors 33b, 34b connected together to the common drain node of transistors 33a, 34a at storage node SNT. Pass-gate transistors 35a, 35b respectively selectively couple storage nodes SNT, SNB to bit lines BLT.sub.k, BLB.sub.k, respectively, of column k in response to the activation of word line WL.sub.j for row j.

(37) According to this embodiment of this invention, the source nodes of load transistor 33a and load transistor 33b are connected to separate array power supply voltage nodes V.sub.DDAa, V.sub.DDAb, respectively. The source nodes of driver transistors 34a, 34b are connected in common to array ground voltage node V.sub.SSA, and the body nodes of p-channel load transistors 33a, 33b are connected in common to array power supply voltage V.sub.DDA. The separate array power supply voltage nodes V.sub.DDAa, V.sub.DDAb enable transistors 33a, 33b to receive different biases from one another. More specifically, the application of a voltage below array power supply voltage V.sub.DDA at one of array power supply voltage nodes V.sub.DDAa, V.sub.DDAb will asymmetrically reduce the bias (i.e., the gate-to-source voltage, the drain-to-source voltage, or both) of its corresponding load transistor 33a, 33b, reducing its drive in a manner similar to the effect of NBTI degradation. This asymmetric bias is thus useful in performing a time-zero screen for cells 30′ that are vulnerable to failure due to NBTI degradation.

(38) Similarly as shown in FIG. 4b described above, FIG. 5b illustrates an example of power supply voltage select circuitry 45 suitable for use in connection with cell 30′.sub.jk according to this embodiment of the invention. As before, power voltage select circuitry 45 resides outside of memory array 20, and selectively applies voltages to array power supply voltage nodes V.sub.DDAa, V.sub.DDAb, in response to control signals SCRN_a/, SCRN_b/, and EQ/ generated by control circuitry (not shown) elsewhere in RAM 18 or integrated circuit 10 (e.g., system control 14). The “/” signal designator for these signal lines indicates that these control signals are active at a low logic level. It is contemplated that those skilled in the art having reference to this specification will be readily able to generate the appropriate levels of control signals SCRN_a/, SCRN_b, EQ/ for carrying out the normal operation and screen functions described below in this specification.

(39) Power supply voltage select circuitry 45 is constructed similarly as ground voltage select circuitry 40 described above in connection with FIG. 4b, in essentially a complementary fashion. As such, power supply voltage select circuitry 45 includes p-channel MOS pass transistor 46a with its source/drain path connected between screen power supply voltage V.sub.DDA_SCRN and array power supply voltage node V.sub.DDAa, and p-channel pass transistor 48a having its source/drain path connected between normal power voltage V.sub.DDA and array power voltage node V.sub.DDAa. The gate of transistor 46a receives control signal SCRN_a/, and the gate of transistor 48a receives the logical complement of control signal SCRN_a/ via inverter 47a. Similarly, p-channel pass transistor 46b has its source/drain path connected between screen power supply voltage V.sub.DDA_SCRN and array power supply voltage node V.sub.DDAb, and p-channel pass transistor 48b has its source/drain path connected between normal power supply voltage V.sub.DDA and array power supply voltage node V.sub.DDAb. The gate of transistor 46b receives control signal SCRN_b/, and the gate of transistor 48b receives the logical complement of control signal SCRN_b/ via inverter 47b. Equalization transistor 49 is a p-channel transistor with its source/drain path connected between array power supply voltage nodes V.sub.DDAa and V.sub.DDAb, and its gate receiving equalization signal EQ/. Equalization signal EQ/ may be generated by external control circuitry as noted above, or alternatively may be produced by logic circuitry as the logical NAND of control signals SCRN_a/, SCRN_b/ or in some other logical arrangement.

(40) Power supply voltages V.sub.DDA and screen power supply voltage V.sub.DD_SCRN may be generated by conventional voltage regulator or level shift circuitry elsewhere in RAM 18 or in integrated circuit 10. For purposes of this embodiment of the invention, screen power supply voltage V.sub.DD_SCRN will typically be at a lower voltage than normal power supply voltage V.sub.DDA.

(41) In normal operation, control signals SCRN_a/, SCRN_b/ will both be inactive (at a high logic level), which turns off both of transistors 46a, 46b and turns on transistors 48a, 48b. Typically, equalization control signal EQ/ will be at an active low level during normal operation, turning on transistor 49. In this condition, normal power supply voltage V.sub.DDA is applied to both of array power supply voltage nodes V.sub.DDAa, V.sub.DDAb, with equalization transistor 49 ensuring symmetric application of that voltage. During a time-zero screen test, one or the other of control signals SCRN_a/, SCRN_b/ will be asserted active (low), while the other remains inactive (high); equalization control signal EQ/will be driven inactive (high). Screen power supply voltage V.sub.DDA_SCRN will be applied to the one of array power supply nodes V.sub.DDAa, V.sub.DDAb connected to the one of transistor 46a, 46b turned on by the active one of control signals SCRN_a/, SCRN_b/, applying an asymmetric bias to load transistors 33a, 33b in one or more cells 30′ within memory array 20.

(42) Similarly as described above in connection with FIGS. 4a through 4c, conductors corresponding to array power supply voltage nodes V.sub.DDAa, V.sub.DDAb can be readily routed through memory array 20, without significantly increasing the chip area required for these separate conductors. FIG. 5c illustrates an example of the layout of cell 30′.sub.jk of FIG. 5a, as constructed at the surface of a silicon substrate, fabricated according to CMOS technology and according to an embodiment of this invention, and at a stage in the manufacture prior to the formation of overlying metal layers.

(43) The arrangement of the transistors, active regions 54, gate elements 56, contact openings 58, and isolation dielectric structures 53, of cell 30′.sub.jk is essentially identical to that described above in connection with FIG. 4c. Cell 30′.sub.jk differs, however, in connection with the muting of metal conductors for array power supply voltage nodes V.sub.DDAa, V.sub.DDAb. In this embodiment of the invention, the metal conductor for array power supply voltage node V.sub.DDAa runs parallel to the conductor for array ground voltage node V.sub.SSA, and connects to the source node of transistor 33a in cell 30′.sub.jk, via a contact opening 58. Similarly, the metal conductor for array power supply voltage node V.sub.DDAb connects to the source node of transistor 33b in cell 30′.sub.jk via a corresponding contact opening 58.

(44) As evident from FIG. 5c, the metal conductors for array power supply voltage nodes V.sub.DDAa, V.sub.DDAb are not shared between adjacent columns in this implementation. However, it is contemplated that the chip area effect of this routing in the layout of cell 30′.sub.jk will be minimal, particularly if the metal conductors for array power supply voltage nodes V.sub.DDAa, V.sub.DDAb can run directly over their respective contact openings 58 to transistors 33a, 33b as shown. Alternatively, it is contemplated that cell 30′.sub.jk can be laid out in such a manner as to enable the sharing of these metal conductors between adjacent columns.

(45) FIG. 6 illustrates cell 30″.sub.jk constructed according to another embodiment of this invention. Cell 30″.sub.jk is constructed in similar manner as cells 30.sub.jk and 30′.sub.jk of FIGS. 4a and 5a, respectively. In particular, cell 30″.sub.jk is constructed as a “6-T” SRAM cell in which the cross-coupled CMOS inverters may be biased separately from one another both at the source node of the p-channel load transistor and at the source node of the n-channel driver transistor. More specifically, according to this embodiment of this invention, the source nodes of p-channel load transistors 33a, 33b are connected to separate array power supply voltage nodes V.sub.DDAa, V.sub.DDAb, respectively; in addition, the source nodes of n-channel driver transistors 34a, 34b are connected to separate array ground voltage nodes V.sub.SSAa, V.sub.SSAb, respectively. The body nodes of load transistors 33a, 33b are connected in common to array power supply voltage V.sub.DD and the body nodes of driver transistors 34a, 34b are connected in common to array ground voltage V.sub.gnd. As such, according to this embodiment, load transistors 33a, 33b can be asymmetrically biased by way of a voltage below array power supply voltage V.sub.DD applied to one of array power supply voltage nodes V.sub.DDAa, V.sub.DDAb, and driver transistors 34a, 34b can be asymmetrically biased by way of a voltage above array ground voltage V.sub.gnd applied to one of array ground voltages nodes V.sub.SSAa, V.sub.SSAb. This asymmetric bias is thus useful in performing a time-zero screen for cells 30′ that are vulnerable to failure due either or both of PBTI and NBTI degradation.

(46) It is contemplated that memory array 20 constructed with cells 30″ as described above in connection with FIG. 6 will include both power supply voltage select circuitry 45 and also ground voltage select circuitry 40. In this regard, it is contemplated that the respective control signals SCRN_a, SCRN_b, SCRN_a/, SCRN_b/, EQ, EQ/ can be combined and generated in an efficient manner by the appropriate control circuitry. It is further contemplated that the layout of FIGS. 4c and 5c can be readily modified by those skilled in the art having reference to this specification so as to incorporate both pairs of power supply and ground conductors V.sub.DDAa, V.sub.DDAb, V.sub.SSAa V.sub.SSAb as appropriate.

(47) It is of course contemplated that the particular schematic circuit arrangement, physical layout, and construction of memory array 20 and its constituent SRAM cells 30, 30′, 30″ may vary significantly from that shown in FIGS. 4a through 4c, 5a through 5c, and 6 and described herein, such variations and alternatives being apparent to those skilled in the art having reference to this specification, yet remain within the scope of this invention. It is therefore to be understood that this description of the architecture, layout, and construction of memory array 20 and SRAM cells 30, 30′, 30″ is provided by way of example only.

(48) Referring now to FIG. 7, a method of testing and screening SRAM cells 30 within RAM 18 of integrated circuit 10, or as a stand-alone memory integrated circuit, as the case may be, according to embodiments of this invention will now be described. It is contemplated that the test process of embodiments of this invention, which involves the application of asymmetric bias voltages to inverter transistors within cells 30 under test within memory array 20 as will be described below, is well suited for wafer-level testing (i.e., “multiprobe” functional testing), prior to packaging of integrated circuit 10, because of the ability to replace marginal cells by way of conventional redundancy techniques at that stage of manufacture. Of course, the test process of FIG. 7 may additionally or instead be performed after packaging, as desired.

(49) It is contemplated that the method of FIG. 7 will typically be performed by way of automated test equipment, for example automated test equipment as used in functionally testing integrated circuits 10. The method of FIG. 7 will be described in connection with the testing of a population of memory cells, for example the testing of array 20 of RAM 18 of FIG. 3. It is contemplated that the particular test sequence may alternatively be applied fully to each memory cell in sequence (i.e., the entire test sequence performed for each cell 30 in turn). Further in the alternative, the test sequence may be applied to cells 30 in a row, column, or sub-array of array 20, or to some other population smaller than the entire array 20. As such, while the method described below in connection with FIG. 7 will refer to a population of cells 30 under test, it is to be understood that the number of cells 30 in that population can number from one to the entire array 20. It is contemplated that those skilled in the art having reference to this specification will be readily able to apply the test sequence of FIG. 7 to the appropriate number of memory cells 30 for specific memory architectures.

(50) The manufacturing test flow shown in FIG. 7 according to embodiments of the invention begins with process 60 in which conventional parametric tests of both the DC and operating type (e.g., continuity, leakage, standby and active power dissipation, etc.) are performed upon RAM 18 under test. As described above and as will be described in further detail below, the screens according to embodiments of this invention are intended to identify those SRAM cells 30 that are vulnerable to failure over operating life. As such, functional tests are performed by the automated test equipment, in process 62, to evaluate the ability of RAM 18 to be written and read with both data states under such operating conditions and timing constraints required by specifications. According to these embodiments of the invention, parametric test process 60 and functional test process 62 are contemplated to be performed using “normal” bias voltages applied symmetrically to the inverters of SRAM cells 30. These “normal” bias voltages applied to cells 30 refer to array power supply voltage levels and array ground voltage levels consistent with normal operating specifications and tolerances for RAM 18. For example, if the performance of RAM 18 is specified over a range of array power supply voltage (V.sub.DDA, for example) of 1.20 volts±5% relative to the array ground voltage (V.sub.SSA for example), a “normal” bias applied to the series-connected load and driver transistors of the inverters of SRAM cell 30.sub.jk will be 1.20 volts±5%, adjusted by any guardbanding in the test process associated with the specified temperature range, noise margin, and the like. The “symmetric” biases contemplated to be applied in processes 60, 62 refers to the application of essentially identical voltages to both load transistors, and to both driver transistors, within each SRAM cell 30 under test. Processes 60 and 62 thus remove, from the population of SRAM cells 30 or of integrated circuits 10 in the aggregate, those devices that do not meet the time-zero specifications desired of those functions. This ensures that the screen processes performed according to embodiments of this invention are applied only to devices that are known to be functionally and parametrically acceptable at normal and symmetric biases. Alternatively, the voltages applied in processes 60, 62 may stray from the “normal” range as desired by the test designer, so long as a known “0” data state is written into cells 30 under test.

(51) According to this embodiment of the invention, asymmetric bias screen process 64 is then performed by the automated test equipment on one or more SRAM cells 30 in RAM 18, to determine whether any of those cells 30 may be vulnerable to shifts in transistor characteristics due to PBTI- and NBTI-caused threshold voltage shifts insofar as such shifts affect the read performance, write performance, read stability, and retention stability of cells 30 under test. According to embodiments of this invention, one or more particular test sequences are included within asymmetric bias screen process 64, each such sequence applying reduced bias to transistors in one of the inverters within each cell 30 under test in order to determine whether that cell is vulnerable to threshold voltage degradation due to PBTI or NBTI, the case may be.

(52) FIG. 8a illustrates a method for performing one of these test sequences, namely read stability test sequence 64a as applied to one or more SRAM cells 30. For purposes of the following description, including the description in connection with FIGS. 8b and 8c, reference will be made to SRAM cells 30 under test, with the understanding that such cells 30 refer to SRAM cells constructed as any of cells 30.sub.jk, 30′.sub.jk, 30″.sub.jk described above or variations thereof. As shown in FIG. 8a, test sequence 64a in this example begins with the writing of a known data state (e.g., “0”) into each of the SRAM cells 30 under test, in process 70. Process 70 is typically performed under normal bias conditions; if desired, a read of those SRAM cells 30 may be performed to verify the written data state into these cells.

(53) As described above, the primary effect of PBTI is a positive shift in the threshold voltage of n-channel transistors, particularly those at which a positive gate voltage (relative to the transistor channel region) has been present for some duration. Conversely, the primary effect of NBTI is a positive shift in the threshold voltage of p-channel transistors receiving a negative gate voltage for some duration. In each case, the increased threshold voltage weakens the drive of the transistor, slowing its switching and also reducing its source/drain current in the “on” state. Also as discussed above, read stability failures occur when the threshold voltage has shifted for either or both of the “on” state load transistor 33a, 33b or the “on” state driver transistor 34b, 34a for the current data state. Following process 70, load transistor 33b and driver transistor 34a are the “on” state transistors.

(54) According to this embodiment of the invention, the effect of BTI threshold shift is mimicked by the application of a reduced bias to either or both of the “on” state transistors, namely load transistor 33b and driver transistor 34a, for each SRAM cell 30 currently under test. The particular transistor receiving the reduced bias will of course depend on the construction of SRAM cell 30, according to the examples described above relative to FIGS. 4a, 5a and 6. For the example of cell 30.sub.jk of FIG. 4a, a higher voltage will be applied at array ground voltage node V.sub.SSAa than at array ground voltage node V.sub.SSAb in process 72. It is contemplated that the voltage differential between array ground voltage nodes V.sub.SSAa and V.sub.SSAb will be on the order of 10% of the nominal bias voltage for the inverters of cell 30. For example, if array power supply voltage V.sub.DDA is nominally at 1.2 volts above normal ground voltage V.sub.gnd, array ground voltage node V.sub.SSAa may receive a voltage that is about 100 mV above array ground voltage V.sub.gnd. To further lighten the screen, array power supply voltage V.sub.DDA may be set at its minimum specification level (e.g., 1.0 volts) in process 72.

(55) Of course, in the cases in which the alternative constructions of cells 30′.sub.jk and 30″.sub.jk are implemented in memory array 20, the asymmetric bias applied in process 72 may instead or additionally apply a lower voltage to array power supply voltage node V.sub.DDAb than at array power supply voltage node V.sub.DDAa, reducing the bias at load transistor 33b for the case of this “0” data state.

(56) Once the asymmetric transistor bias is applied in process 72, read disturb process 74 is then performed by the automated test equipment, upon the cells under test. The particular nature of the disturb cycle or cycles applied in process 74 may vary, depending on the expected read stability vulnerability mechanism. Typically, it is contemplated that process 74 will include an access (read or write) to a cell 30 that is in the same row as each cell 30 under test, to ensure that pass transistor 35a is turned on for the cells 30 under test (i.e., cell 30 is “half-selected”). As discussed above, a typical stability failure is caused by the inability of the “on” state driver transistor 34a to maintain a low level at storage node SNT, for the “0” data state case, if pass transistor 35a is turned on so as to couple storage node SNT to the precharged bit line BLT.sub.k. Other disturb operations may additionally or instead be included within process 72, including a read of each cell under test itself, a write of an opposite data state to a cell 30 in the same column as each cell under test, or the like. Those skilled in the art having reference to this specification will readily identify those disturb conditions suitable for inclusion within process 74.

(57) Following read disturb process 74, normal and symmetric bias is then applied to all transistors of cells 30 under test, in process 76. Cells 30 under test are then read in process 77, to determine whether the read disturb of process 74 under the reduced bias of process 72 caused loss of the stored data state (i.e., the “0” data state written in process 70). The addresses of failing cells may be stored by the automated test equipment for use in redundant repair, or alternatively a first failed cell may trigger a “fail” condition for RAM 18 as a whole.

(58) In decision 78, the automated test equipment determines whether both data states have been tested. If not (decision 78 is “no”), a “1” data state is then written into cells 30 under test in process 79, considering that “normal” bias remains applied as a result of process 76. Processes 72, 74, 76, 77 are then repeated for this opposite data state in the manner described above, except that the reduced bias will be applied to driver transistor 34b, load transistor 33a, or both, depending on the particular cell construction. For the example of cell 30.sub.jk of FIG. 4a, of course, a higher voltage will be applied at array ground voltage node V.sub.SSAb than at array ground voltage node V.sub.SSAa in this instance of process 72 for the “1” data state. Following this pass of the test sequence for the “1” data state (decision 78 is “yes”), read stability test sequence 64a is complete.

(59) FIG. 8b illustrates the method for performing read current test sequence 64b as applied to one or more SRAM cells 30, also as part of screen process 64. As discussed above, the effects of PBTI degradation can weaken the read current sourced at the one of driver transistors 34a, 34b holding a low data state at its storage node; conversely, NBTI degradation can cause the opposite load transistor 33a, 33b to apply a reduced gate voltage at the “on” state driver in the opposing inverter, similarly weakening the read current. Read current test sequence 64b screens cells 30 under test for these potential weaknesses in read current.

(60) Test sequence 64b in this example begins with the writing of a known data state (e.g., “0”) into each of the SRAM cells 30 under test, in process 80, under normal bias. As before, a read of those SRAM cells 30 may be performed to verify the written data state into these cells. For this “0” data state, load transistor 33b and driver transistor 34a are again the “on” state transistors. In process 82 according to this embodiment of the invention, a reduced bias is applied to either or both of the “on” state transistors, namely load transistor 33b and driver transistor 34a, for each SRAM cell 30 under test. This asymmetric bias applied in process 82 is essentially the same as described above in connection with process 72 of FIG. 8a, and as such the particular transistor receiving the reduced bias depends on the construction of SRAM cell 30, according to the examples described above relative to FIGS. 4a, 5a and 6.

(61) Under this reduced transistor bias as applied in process 82, each of cells 30 under test is read by the automated test equipment in process 84. The reduction in transistor bias serves to mimic the effect of threshold voltage degradation due to BTI, as that reduced bias weakens the transistor drive. The read of process 84 thus tests the read current under the reduced bias (e.g., a raised voltage at the source of driver transistor 34a applied by array ground voltage node V.sub.SSAa), thus determining whether that read current is sufficient to convey the correct “0” data state.

(62) Following the read of process 84, the automated test equipment determines whether both data states have been tested in decision 85. If not (decision 85 is “no”), normal symmetric bias is then applied to all transistors of cells 30 under test in process 86, and the opposite “1” data state is written into cells 30 under test in process 87. Processes 82, 84, 85 are then repeated for this opposite data state in the manner described above, except that the reduced bias will be applied to driver transistor 34b, load transistor 33a, or both, depending on the particular cell construction. Following this pass of the test sequence for the “1” data state (decision 85 is “yes”), read test sequence 64b is complete. The addresses of any failing cells 30 are stored for use in redundant repair, or alternatively RAM 18 is considered as “failed” if failing cells were detected.

(63) FIG. 8c illustrates a method for performing writeability test sequence 64c as may be included within screen process 64, according to embodiments of this invention. This test sequence 64c in this example begins with the writing of the “0” data state into each of the SRAM cells 30 under test, in process 90. As before, for this “0” data state, load transistor 33b and driver transistor 34a are again the “on” state transistors.

(64) As discussed above, write failures are commonly due to weakness in a pass transistor 35a, 35b to allow the low-side bit line to overcome the drive of its associated load transistor in pulling its storage node from high to low, and in weakness in the associated driver transistor 34a, 34b to responding to feedback to change the cell state, both due to PBTI in the cell construction described above. NBTI degradation at a load transistor 33a, 33b can also cause a write failure, as weaker drive current will degrade its ability to pull a storage node from low to high in response to the write. As such, write screen process 64c will reduce the bias voltage to “off” state transistors, namely either or both of driver transistor 34b and load transistor 33a, which will also affect pass transistor 35b at storage node SNB (which is at a high level for this “0” state).

(65) In process 92 according to this embodiment of the invention, therefore, BTI threshold shift is mimicked by the application of a reduced bias to either or both of the “off” state transistors, namely driver transistor 34b and load transistor 33a, for each SRAM cell 30 currently under test. This asymmetric bias applied in process 92 is essentially the same as described above in connection with processes 72, 82, but is applied to the opposite transistor or transistors from those screen processes 64a, 64b, and will depend on the construction of SRAM cell 30, according to the examples described above relative to FIGS. 4a, 5a and 6. For the example of cell 30.sub.jk of FIG. 4a, a higher voltage will be applied at array ground voltage node V.sub.SSAb than at array ground voltage node V.sub.SSAa in process 92; for example, this voltage differential can be on the order of 10% of the nominal bias voltage for the inverters of cell 30 (e.g., 100 mV for nominal array power supply voltage V.sub.DDA of 1.2 volts above normal ground voltage V.sub.gnd).

(66) The automated test equipment then performs a write of the opposite (“1”) data state to cells 30 under test in process 94, under the reduced transistor bias applied in process 92 that mimics threshold voltage degradation due to BTI. This write operation of process 94 thus tests the ability of pass transistor 35b and driver transistor 34b, or load transistor 33a (or all those transistors) to successfully change the state of cell 30 under test at the reduced drive current caused by the reduced bias (e.g., a raised voltage at the source of driver transistor 34b applied by array ground voltage node V.sub.SSAb). Following write process 94, normal symmetric bias is then applied to all transistors of cells 30 under test, in process 96, and cells 30 under test are then read in process 97 to determine whether the write of process 94 under the reduced bias of process 92 was successful. The addresses of failing cells may be stored by the automated test equipment for use in redundant repair, or alternatively a first failed cell may trigger a “fail” condition for RAM 18 as a whole.

(67) In decision 98, the automated test equipment determines whether both data states have been tested. If not (decision 98 is “no”), a “1” data state is then written into cells 30 under test in process 99, and processes 92, 94, 96, 97 are then repeated for this opposite data state as described above. Of course, the asymmetric bias applied in process 92 will be reversed for this data state, to evaluate operation should the other transistors be weakened. Following this pass of the write test sequence 64c for the “1” data state (decision 98 is “yes”), write test sequence 64c is complete. The addresses of any failing cells 30 are stored for use in redundant repair, or alternatively RAM 18 is considered as “failed” if failing cells were detected.

(68) FIG. 8d illustrates a method for performing retention-disturb test sequence 64d as may also be included within screen process 64, according to embodiments of this invention. In process 100, the automated test equipment writes a known data state (e.g., “0”) into each of the SRAM cells 30 under test, under normal bias, followed by a read (if desired) to verify the data states written.

(69) In process 102, a reduced bias is applied to either or both of the “on” state transistors, namely load transistor 33b and driver transistor 34a for a “0” data state, in each SRAM cell 30 currently under test. As described above, for the example of cell 30.sub.jk of FIG. 4a, a higher voltage is applied at array ground voltage node V.sub.SSAa than at array ground voltage node V.sub.SSAb in process 102, for example a voltage on the order of 10% of the nominal inverter bias voltage (i.e., about 100 mV above array ground voltage V.sub.gnd at a nominal array power supply voltage of 1.2 V). Also in process 102, array power supply voltage V.sub.DDA may be set at its minimum specification level (e.g., 1.0 volts), if a more stringent screen is desired. The result of process 102 is to mimic the effect of PBTI degradation at the “on” drive transistor (driver transistor 34a for a “0” data state), by way of weakening its drive by reducing its gate-to-source and drain-to-source voltages relative to that of opposing driver transistor 34b.

(70) Following application of the reduced transistor bias in process 102, retention disturb process 104 is then performed by the automated test equipment on the cells under test. According to this embodiment of the invention, in which the reduced bias of process 102 consists of a higher ground level voltage applied to the source of one of driver transistors 34a, 34b, retention disturb process 104 is performed by the automated test equipment reducing the array power supply voltage V.sub.DDA to the desired level. For example, a typical retention disturb involves applying ½ the nominal power supply voltage V.sub.DDA (e.g., 0.6 V where the nominal power supply voltage is 1.2 V). Cells 30 under test are then statically held at this reduced power supply voltage, for example for a duration of on the order of 100 msec, following which the power supply voltage is returned to those cells.

(71) In the case of cells 30′.sub.jk and 30″.sub.jk, the asymmetric bias applied in process 102 and retention disturb process 104 may be performed simultaneously, insofar as retention disturb process 104 involves the reduction of array power supply voltage. For example, asymmetric bias may be applied (for the “0” data state) by reducing the voltages at both array power supply nodes V.sub.DDAa, V.sub.DDAb, but with the voltage at array power supply node V.sub.DDAb being reduced more than the voltage at array power supply voltage node V.sub.DDAa. This operation would reduce the bias for the “on” state load transistor 33b (for the “0” data state), and also reduce the array power supply voltage generally to carry out the retention disturb.

(72) After retention disturb process 104, normal (symmetric) bias is then applied to all transistors of cells 30 under test in process 106. In process 107, cells 30 under test are then read to determine whether the retention disturb of process 104 under the asymmetric bias applied in process 102 caused loss of the stored data state (i.e., the “0” data state written in process 100). The pass/fail results, including the addresses of failing cells, are stored by the automated test equipment in its memory, also in process 107.

(73) In decision 108, the automated test equipment determines whether both data states have been tested. If not (decision 108 is “no”), a “1” data state is then written into cells 30 under test in process 109, under the “normal” bias conditions applied in process 106. Processes 102, 104, 106, 107 are then repeated for this opposite data state in the manner described above, except that the reduced bias will be applied to driver transistor 34b, load transistor 33a, or both, depending on the particular cell construction. For the example of cell 30.sub.jk of FIG. 4a, of course, a higher voltage will be applied at array ground voltage node V.sub.SSAb than at array ground voltage node V.sub.SSAa in the repeated instance of process 102 for the “1” data state. Following this pass of the test sequence for the “1” data state (decision 108 is “yes”), retention stability test sequence 64d is complete.

(74) Referring back to FIG. 7, upon completion of asymmetric bias screen process 64, the remainder of the test program is then completed by the automated test equipment for RAM 18. In this embodiment of the invention, if RAM 18 includes redundant rows or columns (or both) of SRAM cells 30 that are available to replace main array cells that fail screen 64, redundant replacement of any identified failed cells can be performed in the manner shown in FIG. 7. The automated test equipment determines, in decision 65, whether any SRAM cells 30 failed screens 64 by interrogating its memory for any stored addresses of failed cells; if there are none (decision 65 is “pass”), memory array 20 is considered as having passed and is ready for further manufacture. If one or more SRAM cells 30 failed screen 64 than can be replaced by the available redundant cells (decision 465 is “≥n fail”), memory array 20 is considered to have failed, and is disposed of or otherwise reworked as appropriate. If one or more, but fewer than the limit of, SRAM cells 30 failed screen 64, conventional redundant replacement and mapping of redundant cells is performed in process 66, and those newly enabled cells 30 may themselves be screened by screen 64 to ensure their ability to withstand BTI degradation over the expected operating life. Assuming that additional vulnerable bits are not identified (decision 67 is “pass”), memory array 20 is then ready for additional manufacture.

(75) Following the test method shown in FIG. 7, and such other test and wafer-level processing as appropriate, integrated circuit 10 will proceed to the desired packaging and additional test stages of the manufacturing process. In the packaging of integrated circuit 10, it is contemplated that the pads available at the wafer level may enable the hard-wiring of the separate array power supply voltage nodes V.sub.DDAa, V.sub.DDAb and array ground voltage nodes V.sub.SSAa, V.sub.SSAb to one another so that operation of RAM 18 in its system application will be carried out under normal bias conditions.

(76) Embodiments of this invention provide numerous important benefits and advantages over conventional memory test approaches. As described above, the ability to apply asymmetric bias voltage to transistors within memory cells enables the more direct screening of vulnerable cells than is conventionally available by way of conventional “proxy” bias voltages and other test vector conditions. As such, more direct and more robust screening for later life threshold voltage shifts, including both n-channel transistors due to PBTI and p-channel transistors due to NBTI, as well as for variations of operating temperature, is thus provided by embodiments of this invention.

(77) While this invention has been described according to its embodiments, it is of course contemplated that modifications of, and alternatives to, these embodiments, such modifications and alternatives obtaining the advantages and benefits of this invention, will be apparent to those of ordinary skill in the art having reference to this specification and its drawings. It is contemplated that such modifications and alternatives are within the scope of this invention as subsequently claimed herein.