Molded interconnect device
11357112 · 2022-06-07
Assignee
Inventors
- Tsuey Choo Chang (Lisle, IL, US)
- Steven Zeilinger (Carol Stream, IL, US)
- Hyun-Jong Ko (Seoul, KR)
- Patrick Riley (LaGrange, IL, US)
- SukMin Kang (Gwangmyeong, KR)
Cpc classification
H05K3/426
ELECTRICITY
H05K1/0284
ELECTRICITY
H05K3/027
ELECTRICITY
H05K3/242
ELECTRICITY
Y10T29/5193
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
International classification
H01R43/00
ELECTRICITY
H05K3/00
ELECTRICITY
Abstract
In some embodiments, a manufacturing process includes injection molding a palladium-catalyzed material into a substrate, forming a thin copper film over exterior and exposed surfaces of the substrate; ablating or removing copper film from the substrate to provide first, second and optional third portions of the copper film and ablated sections; electrolytically plating each portion to form metallic-plated portions; and ablating or removing the second portion in order to isolate the first portion. The metallic-plated first portion comprises a circuit portion of a molded interconnect device (MID), and where the metallic-plated third portion comprises a Faraday cage portion of a MID. A soft etching step may be included. A solder resist application step can be added, along with an associated solder resist removal step.
Claims
1. A molded interconnect device (MID) comprising: a substrate formed of a resin which is infused with palladium; a circuit portion formed over first surfaces of the substrate, the first surfaces being exterior and exposed surfaces of the substrate; and a Faraday cage portion formed over second surfaces of the substrate, the second surfaces being exterior and exposed surfaces of the substrate, wherein the Faraday cage portion is isolated from the circuit portion.
2. The MID as defined in claim 1, wherein each of the circuit portion and the Faraday cage portion has a metallized layer secured to the substrate and an electrolytic metallic plated layer secured to the metallized layer.
3. The MID as defined in claim 2, wherein the metallized layer is formed of copper.
4. The MID as defined in claim 2, wherein the electrolytic metallic plated layer is formed of an electrolytic copper plated layer, and electrolytic nickel plated layer, and an electrolytic gold plated layer.
Description
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
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DETAILED DESCRIPTION OF THE INVENTION
(26) The present disclosure is directed to novel manufacturing processes 100, 200, 300, 400 for forming a molded interconnect device (MID) 50. The manufacturing processes 100, 200, 300, 400 are useful for the creation of MIDs, such as printed circuit boards, flex circuits, connectors, thermal management features, electromagnetic interference (EMI) shielding, high current conductors, radio frequency identification (RFID) apparatuses, antennas, wireless power, sensors, MEMS apparatuses, LEDs, microprocessors and memory, ASICs, passives, and other electrical and electro-mechanical apparatuses.
(27) Attention is directed to
(28) The molding stage of the manufacturing process 100 advantageously includes only a single step, which step will be referenced by reference numeral 110. Step 110 is an injection-molding step where a palladium-catalyzed material (sometimes called palladium-doped in the art), such as, for example, resins or epoxy molding compounds, is injection-molded in the form of a sheet 112 containing a plurality of connected substrates 114 (each formed in the intended shape) for production purposes. Each substrate 114 may be formed in a desired three-dimensional shape. In some embodiments, each substrate 114 is formed of the same three-dimensional shape.
(29) The circuit forming stage of the manufacturing process 100 includes two steps, which steps will be referred to as steps 120 and 130.
(30) Step 120 is a metallization step where a thin copper film 122 is formed over the exterior and exposed surfaces of the palladium-catalyzed substrates 114 to form a first assembly 123. Metallization step 120 is commonly referred to as copper-striking.
(31) Step 130 is a circuit patterning step where a laser (not shown) ablates or removes portions of the copper film 122 from the first assembly 123 to expose portions 131, 132 of the substrate 114 and form a second assembly 133. This action defines and outlines a circuit pattern within the remaining copper film 122 to be provided for the MID 50.
(32) The plating stage of the manufacturing process 100 includes two steps, which steps will be referred to as steps 140 and 150.
(33) Step 140 is an electrolytic plating step where a probe (not shown) is attached/connected to one of the first, second and third portions 134, 136, 138 and electricity is run through the first, second and third portions 134, 136, 138 and desired metallic molecules from a desired metallic bath are drawn to and secured to the first, second and third portions 134, 136, 138, until the desired metallic plating of the first, second and third portions 134, 136, 138 is built up to the desired thickness, thus forming metallic-plated first, second and third portions 144, 146, 148 (it is to be understood that metallic-plated third portion 148 will only be formed if third portion 138 is provided), thereby forming a third assembly 143.
(34) It is to be understood that the electrolytic plating step 140 can include the electrolytic plating of any metal(s) as desired. In a preferred embodiment, the electrolytic plating step 140 begins with a step 141 wherein a copper material is electrolytic plated onto the first, second and third portions 144, 146, 148 to form a copper plating 173, followed by a step 171 wherein a nickel material is electrolytic plated onto the copper material 173 to form a nickel plating 174, followed by a step 172 wherein a gold material is electrolytic plated onto the nickel material 147 to form a gold plating 175, as illustrated in
(35) Step 150 is a circuit isolation step where a laser (not shown) ablates or removes the formed second (bus) portion(s) 136/146, beginning with second portion 146, and finishing with second portion 136, until the surface of the substrate 114 is provided between the first and third portions 144, 148, thereby providing portions 152 of the substrate 114 which are visible, and thereby forming a fourth assembly 153. The ablated sections 152 are connected to or continuous with the ablated sections 132 such that the first portion 144 (namely the circuit pattern) is isolated from the third portion 148 (namely the Faraday cage portion).
(36) Step 160 is a cutting step where the sheet 112 is diced in order to separate each of the MIDs 50. The sheet 112 can be diced along saw streets 162 (the saw streets 162 are not shown in
(37) Either before or after step 160 of the manufacturing process 100 is performed, one or more of the MIDs 50 can then be inspected, as desired and in any of a number of known manners, to ensure that the MIDs 50 are suitable for their intended use. The MIDs 50 may then be packaged and shipped. If desired, further electronic components may be electrically connected and secured to the first portion 144, namely the circuit portions, before the MIDs 50 are packaged and shipped. It is to be understood that the sheet 112 of MIDs 50 could be packaged and shipped prior to the cutting step 160 being performed.
(38) Attention is directed to
(39) Attention is directed to
(40) Step 380 is a solder resist addition step where solder resist 337 is added non-selectively onto the entire assembly, including the copper plating 173 and the ablated sections 131, 132 as shown in
(41) Attention is directed to
(42) Step 490 is a solder resist addition step where solder resist 337 is added non-selectively onto the entire assembly, including the gold plating 175 and the ablated sections 131, 132 as shown in
(43) The manufacturing processes 100, 200, 300, 400 of forming the MIDs 50 are advantageous as compared to the prior-known MID manufacturing processes, especially as compared to the MIPTEC and laser developed additive technology processes. More specifically, as the injection-molded material is infused with palladium, it is then unnecessary to perform any type of surface activation treatment to the substrate 114 of the type which is required in all prior-known MID manufacturing processes. Thus, the manufacturing processes 100, 200, 300, 400 removes a step which is needed in all prior-known MID manufacturing processes, thereby saving both manufacturing costs and manufacturing time.
(44) MIPTEC and LDS technology processes also have limitations, and in some circumstances even impossibilities, in connection with plating features that are not within a line-of-sight. For instance, as illustrated in
(45) Furthermore, it has been determined that the manufacturing processes 100, 200, 300, 400 provide for improved plating adhesion as compared to the prior-known MID manufacturing processes, thereby making the MIDs 50 formed from the manufacturing processes 100, 200, 300, 400 more robust and reliable than the MIDs formed from the prior-known MID manufacturing processes.
(46) Advantageously, each of the manufacturing processes 100, 200, 300, 400 may provide an MID 50 having a Faraday cage configuration, where the third portions 148 provide the Faraday cage configuration which is useful in providing better EMI shielding for any packaged integrated circuit application. To aid in the provision of the Faraday cage configuration, each substrate 114 provided in the sheet 112 may have one or more vias (not shown) formed along saw street, namely where the sheet 112 is diced during step 160 to provide the individual MIDs 50. These vias allow for the metallization and electrolytic plating, of steps 120 and 140/140a, respectively, of all sides of the MIDs 50. It is to be understood that the size/shape of the Faraday cage configuration, if provided, may vary as desired.
(47) All references, including publications, patent applications, and patents, cited herein are hereby incorporated by reference to the same extent as if each reference were individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein.
(48) The use of the terms “a” and “an” and “the” and “at least one” and similar referents in the context of describing the invention (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The use of the term “at least one” followed by a list of one or more items (for example, “at least one of A and B”) is to be construed to mean one item selected from the listed items (A or B) or any combination of two or more of the listed items (A and B), unless otherwise indicated herein or clearly contradicted by context. The terms “comprising,” “having,” “including,” and “containing” are to be construed as open-ended terms (i.e., meaning “including, but not limited to,”) unless otherwise noted. Recitation of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. All processes described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., “such as”) provided herein, is intended merely to better illuminate the invention, and does not pose a limitation on the scope of the invention unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the invention.
(49) Preferred embodiments of this invention are described herein, including the best mode known to the inventors for carrying out the invention. Variations of those preferred embodiments may become apparent to those of ordinary skill in the art upon reading the foregoing description. The inventors expect skilled artisans to employ such variations as appropriate, and the inventors intend for the invention to be practiced otherwise than as specifically described herein. Accordingly, this invention includes all modifications and equivalents of the subject matter recited in the claims appended hereto as permitted by applicable law. Moreover, any combination of the above-described elements in all possible variations thereof is encompassed by the invention unless otherwise indicated herein or otherwise clearly contradicted by context.