Configurable non-volatile arithmetic memory operators

Abstract

The Non-Volatile Arithmetic Memory Operator (NV-AMO) including a non-volatile memory cell for storing non-volatile data and a first input terminal for receiving volatile variable data is applied to perform the arithmetic operations over the volatile variable data and the non-volatile data. The NV-AMO can also be configured multiple-times for new computations. The constructions of NV-AMO in Arithmetic Logic Units (ALU) can be applied in DSP (Digital Signal Processor) computations and DNN (Deep Neural Network) computations.

Claims

1. A nonvolatile arithmetic memory operator for performing a bit arithmetic operation over a first operand and a second operand, comprising: a nonvolatile memory (NVM) cell for pre-storing a first data bit as the first operand; and a first input terminal coupled to the NVM cell for receiving a second data bit as the second operand; wherein the NVM cell has two conductance states that respectively represent two logic values of the first data bit.

2. The nonvolatile arithmetic memory operator according to claim 1, further comprising: a first output terminal; and a logic gate circuit connected to the first output terminal and at least one of the NVM cell and the first input terminal for performing the bit arithmetic operation over the first operand and the second operand to generate an output bit at the first output terminal.

3. The nonvolatile arithmetic memory operator according to claim 2, wherein the logic gate circuit comprises: a first switch coupled between the first input terminal and the first output terminal; a second switch coupled between the NVM cell and the first output terminal; a first inverter having an input node coupled to the first output terminal; a second inverter having an input node coupled to an output node of the first inverter; and a third switch coupled between the first output terminal and an output node of the second inverter; wherein the bit arithmetic operation is a bit-multiplication operation.

4. The nonvolatile arithmetic memory operator according to claim 3, wherein the first switch is turned on during a first period, the second switch is turned on during a second period, and the third switch is turned on during a third period, and wherein the first period is followed by the second period, and the second period is followed by the third period.

5. The nonvolatile arithmetic memory operator according to claim 2, wherein the logic gate circuit comprises: an inverter coupled between an output node of the NVM cell and the first output terminal; wherein the NVM cell is a floating-gate inverter device coupled between the first input terminal and the inverter; and wherein the bit arithmetic operation is a bit-multiplication operation.

6. The nonvolatile arithmetic memory operator according to claim 5, wherein the floating-gate inverter device comprises a floating-gate PMOS device and a floating-gate NMOS device that are connected in series and share a common floating gate, wherein drain electrodes of the floating-gate PMOS device and the floating-gate NMOS device form an output node of the NVM cell, and control gates of the floating-gate PMOS device and the floating-gate NMOS device are connected together, and wherein the first input terminal is connected to the control gates of the floating-gate PMOS device and the floating-gate NMOS device.

7. The nonvolatile arithmetic memory operator according to claim 6, wherein source electrodes of the floating-gate PMOS device and the floating-gate NMOS device are respectively connected to an operating voltage node and a ground node.

8. The nonvolatile arithmetic memory operator according to claim 2, further comprising: a second input terminal for receiving a third data bit complementary to the second data bit; and a second output terminal for generating a carry-out bit; wherein the NVM cell comprises a first NVM device and a second NVM device in different conductance states, wherein the first NVM device is connected between the first input terminal and a connecting node, and the second NVM device is connected between the second input terminal and the connecting node.

9. The nonvolatile arithmetic memory operator according to claim 8, wherein the logic gate circuit comprises a NOR gate having a first input node connected to the connecting node, a second input node connected to the second input terminal and an output node connected to the second output terminal, and wherein the connecting node is connected to the first output terminal.

10. The nonvolatile arithmetic memory operator according to claim 9, which is an nonvolatile half adder.

11. The nonvolatile arithmetic memory operator according to claim 8, wherein the logic gate circuit further comprises: an OR gate having a first input node connected to the connecting node and a second input node connected to the second input terminal; a XOR gate having a first input node receiving a carry-in bit, a second input node connected to the connecting node and an output node connected to the first output terminal; a first NAND gate having a first input node receiving the carry-in bit and a second input node connected to the connecting node; and a second NAND gate having a first input node connected to an output node of the first NAND gate, a second input node connected to an output node of the OR gate and an output node connected to the second output terminal.

12. The nonvolatile arithmetic memory operator according to claim 11, which is an nonvolatile full adder.

13. The nonvolatile arithmetic memory operator according to claim 1, wherein the NVM cell is re-configurable.

14. An nonvolatile arithmetic memory operator module, comprising: N nonvolatile arithmetic memory operators to pre-store N-bit data in N nonvolatile memory (NVM) cells as a first operand and receive N-bit volatile data as a second operand to perform a predefined arithmetic computation over the first operand and the second operand; wherein each nonvolatile arithmetic memory operator comprises: a corresponding one of the NVM cells for pre-storing a corresponding first bit of the first operand; and a first input terminal coupled to the corresponding one of the NVM cells for receiving a corresponding second bit of the second operand; wherein the NVM cells are arranged in a row to allow their control gates to be applied with a same control gate voltage; and wherein each NVM cell has two conductance states that respectively represent two logic values of its corresponding first bit.

15. The nonvolatile arithmetic memory operator module according to claim 14, wherein the same control gate voltage is greater than (V.sub.thL+V.sub.DD) and less than V.sub.thH, wherein V.sub.thL denotes a low threshold voltage of the NVM cells, V.sub.thH denotes a high threshold voltage of the NVM cells and V.sub.DD denotes a positive digital voltage bias of the NVM cells.

16. The nonvolatile arithmetic memory operator module according to claim 14, wherein each nonvolatile arithmetic memory operator further comprises: a first output terminal; and a logic gate circuit connected to the first output terminal and at least one of the corresponding one of the NVM cells and the first input terminal for performing a bit arithmetic operation corresponding to the predefined arithmetic computation over the corresponding first bit and the corresponding second bit to generate an output bit at the first output terminal.

17. The nonvolatile arithmetic memory operator module according to claim 16, wherein each logic gate circuit comprises: a first switch coupled between the first input terminal and the first output terminal; a second switch coupled between the corresponding one of the NVM cells and the first output terminal; a first inverter having an input node coupled to the first output terminal; a second inverter having an input node coupled to an output node of the first inverter; and a third switch coupled between the first output terminal and an output node of the second inverter; wherein the bit arithmetic computation is a bit-multiplication operation and the predefined arithmetic computation is multiple-bit multiplication.

18. The nonvolatile arithmetic memory operator module according to claim 17, wherein each first switch is turned on during a first period, each second switch is turned on during a second period, and each third switch is turned on during a third period, and wherein the first period is followed by the second period, and the second period is followed by the third period.

19. The nonvolatile arithmetic memory operator module according to claim 16, wherein each logic gate circuit comprises: an inverter coupled between an output node of the corresponding one of the NVM cells and the first output terminal; wherein the corresponding one of the NVM cells is a floating-gate inverter device coupled between the first input terminal and the inverter; and wherein the predefined arithmetic computation is a multiple-bit multiplication and the bit arithmetic operation is a bit-multiplication operation.

20. The nonvolatile arithmetic memory operator module according to claim 19, wherein the floating-gate inverter device comprises a floating-gate PMOS device and a floating-gate NMOS device that are connected in series and share a common floating gate, wherein drain electrodes of the floating-gate PMOS device and the floating-gate NMOS device form an output node of the corresponding one of the NVM cells, and control gates of the floating-gate PMOS device and the floating-gate NMOS device are connected together, and wherein the first input terminal is connected to the control gates of the floating-gate PMOS device and the floating-gate NMOS device.

21. The nonvolatile arithmetic memory operator module according to claim 20, wherein source electrodes of the floating-gate PMOS device and the floating-gate NMOS device are respectively connected to an operating voltage node and a ground node.

22. The nonvolatile arithmetic memory operator module according to claim 16, wherein the N nonvolatile arithmetic memory operators comprise at least (N−1) nonvolatile full adders, wherein a carry-out bit from a previous stage nonvolatile arithmetic memory operator is fed into a carry-in bit of a next stage nonvolatile arithmetic memory operator so that the N nonvolatile arithmetic memory operators are connected in series.

23. The nonvolatile arithmetic memory operator module according to claim 22, wherein each nonvolatile arithmetic memory operator further comprises: a second input terminal for receiving a third bit complementary to the corresponding second bit of the second operand; and a second output terminal for generating the carry-out bit; wherein each NVM cell comprises a first NVM device and a second NVM device in different conductance states, wherein the first NVM device is connected between the first input terminal and a connecting node and the second NVM device is connected between the second input terminal and the connecting node.

24. The nonvolatile arithmetic memory operator module according to claim 23, wherein the N nonvolatile arithmetic memory operators are N nonvolatile full adders, wherein the logic gate circuit for each nonvolatile arithmetic memory operator comprises: an OR gate having a first input node connected to the connecting node and a second input node connected to the second input terminal; a XOR gate having a first input node receiving a carry-in bit, a second input node connected to the connecting node and an output node connected to the first output terminal; a first NAND gate having a first input node receiving the carry-in bit and a second input node connected to the connecting node; and a second NAND gate having a first input node connected to an output node of the first NAND gate, a second input node is connected to an output node of the NOR gate and an output node connected to the second output terminal.

25. The nonvolatile arithmetic memory operator module according to claim 23, wherein one of the N nonvolatile arithmetic memory operators is a nonvolatile half adder.

26. The nonvolatile arithmetic memory operator module according to claim 25, wherein the logic gate circuit for the one of the N nonvolatile arithmetic memory operators comprises: a NOR gate having a first input node connected to the connecting node, a second input node connected to the second input terminal and an output node connected to the second output terminal.

27. The nonvolatile arithmetic memory operator module according to claim 14, wherein each NVM cell is re-configurable.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) For a better understanding of the present invention and to show how it may be carried into effect, reference will now be made to the following drawings, which show the preferred embodiment of the present invention, in which:

(2) FIG. 1a shows the true table for bit addition (or a conventional half adder).

(3) FIG. 1b shows the combinational logic gates for the conventional half adder associated with FIG. 1a.

(4) FIG. 1c shows MOSFET device schematics for the conventional half adder in FIG. 1b.

(5) FIG. 2a shows the truth table for bit multiplication (or a conventional AND gate).

(6) FIG. 2b shows the combinational logic gates for the conventional AND gate associated with FIG. 2a.

(7) FIG. 2c shows MOSFET device schematics for the conventional AND gate in FIG. 2b.

(8) FIG. 3a illustrates two input volatile bit data in the two input registers are passed to the addition operator for the computed bit data stored in the output data registers.

(9) FIG. 3b illustrates two input volatile bit data in the two input registers are passed to the multiplication operator for the computed bit data stored in the output data registers.

(10) FIG. 4a shows schematics of a 1-bit NV-AMO for realizing a 1-bit non-volatile half adder according to one embodiment of the invention.

(11) FIG. 4b shows the definition of volatile data and non-volatile data for the 1-bit NV-AMO in FIG. 4a.

(12) FIG. 4c shows the input voltage signals/logic values and the output voltage signals/logic values for the 1-bit NV-AMO in FIG. 4a.

(13) FIG. 5a shows the schematics of a 1-bit NV-AMO for realizing a 1-bit non-volatile full adder according to one embodiment of the invention.

(14) FIG. 5b shows the definition of volatile data and non-volatile data for the 1-bit NV-AMO in FIG. 5a.

(15) FIG. 5c shows the input voltage signals/logic values and the output voltage signals/logic values for the 1-bit NV-AMO in FIG. 5a.

(16) FIG. 6a shows the truth table for a conventional full adder constructed by two half adder.

(17) FIG. 6b shows the logic equation for the full adder in FIG. 6a.

(18) FIG. 6c shows logic gate schematics for the full adder in FIG. 6a.

(19) FIG. 7a shows a schematic diagram of a 1-bit NV-AMO for bit-multiplication according to an embodiment of the invention.

(20) FIG. 7b shows the operational switching timing sequence for the 1-bit NV-AMO in FIG. 7a.

(21) FIG. 7c shows the definition of volatile data and non-volatile data for the 1-bit NV-AMO in FIG. 7a.

(22) FIG. 7d shows the input voltage signals/logic values and the output voltage signals/logic values for the 1-bit NV-AMO in FIG. 7a.

(23) FIG. 8a shows a schematic diagram of 1-bit NV-AMO for bit-multiplication using a floating-gate non-volatile inverter device according to another embodiment of the invention.

(24) FIG. 8b shows the input/output voltage transfer curve characteristics for the floating-gate non-volatile inverter device in FIG. 8a.

(25) FIG. 8c shows the definition of volatile data and non-volatile data for the 1-bit NV-AMO in FIG. 8a.

(26) FIG. 8d shows the input voltage signals/logic values and the output voltage signals/logic values for the 1-bit NV-AMO in FIG. 8a.

(27) FIG. 9 shows a schematic diagram of an nonvolatile arithmetic memory operator module for an n-bit ripple adder using the SGLNVM devices (disclosed in U.S. Pat. No. 9,048,137 B2) for storing non-volatile data according to an embodiment of the invention.

(28) FIG. 10 shows a schematic diagram of an nonvolatile arithmetic memory operator module for n-bit multiplication using SGLNVM devices for storing non-volatile data according to the operational procedure in FIG. 7a.

DETAILED DESCRIPTION OF THE INVENTION

(29) The following detailed description is meant to be illustrative only and not limiting. It is to be understood that other embodiment may be utilized and element changes may be made without departing from the scope of the present invention. Also, it is to be understood that the phraseology and terminology used herein are for the purpose of description and should not be regarded as limiting. Those of ordinary skill in the art will immediately realize that the embodiments of the present invention described herein in the context of methods and schematics are illustrative only and are not intended to be in any way limiting. Other embodiments of the present invention will readily suggest themselves to such skilled persons having the benefits of this disclosure.

(30) In one embodiment we apply the Scalable Gate Logic Non-Volatile Memory (SGLNVM) devices disclosed in U.S. Pat. No. 9,048,137 B2 (the disclosure of which is incorporated herein by reference in its entirety) to the NV-AMOs for the arithmetic computations. Since the SGLNVM devices are fabricated with the same CMOS logic process technologies as for the digital IC chip fabrications, it is convenient to implement the invented NV-AMOs for arithmetic computations with the SGLNVM devices in Arithmetic Logic Unit (ALU).

(31) FIG. 9 shows the schematics of an nonvolatile arithmetic memory operator module (for realizing a n-bit ripple carry adder) 900 applying the SGLNVM devices for the non-volatile data storage. The nonvolatile arithmetic memory operator module for the n-bit ripple carry adder 900 comprises one non-volatile half adder 9(0) for the bit data input A.sub.0/Ā.sub.0, and “n−1” non-volatile full adders 9(1), . . . , 9(n−1), for the bit data input A.sub.1/Ā.sub.1, . . . , A.sub.n-1/Ā.sub.n-1. The n-bit non-volatile data for NB.sub.0, . . . , NB.sub.n-1 are stored in the complementary pairs of SGLNVM devices 95(0), . . . , 95(n−1) in the non-volatile adders 9(0), 9(1), . . . , 9(n−1). The complementary pairs of SGLNVM devices 95(0), . . . , 95(n−1) are initially erased to a low threshold voltage state V.sub.thL (the “high” conductance state as defined in FIG. 4b and FIG. 5b) and can be also programmed to a high threshold voltage state V.sub.thH (the “low” conductance state as defined in FIG. 4b and FIG. 5b). According to the defined tables for the adders in FIG. 4b and FIG. 5b, the SGLNVM devices 95(0), . . . , 95(n−1) connected with their volatile data input node A.sub.i are programmed to the high threshold voltage state V.sub.thH for non-volatile data NB.sub.i=“1”. While the SGLNVM devices connected with their volatile data input node Ā.sub.i are programmed to the high threshold voltage state V.sub.thH for non-volatile data NB.sub.i=“0”. When the control gates 910 of SGLNVM devices are biased with the applied voltage V.sub.cg for (V.sub.thL+V.sub.DD)<V.sub.cg<V.sub.thH, the SGLNVM devices of the complementary pairs with the low threshold voltage state V.sub.thL pass the voltage V.sub.DD or 0 V from their input voltage nodes and in the meantime, the other SGLNVM devices of the same complementary pairs with the high threshold voltage state V.sub.thH are completely shut off, where V.sub.DD denotes a positive digital voltage bias of the SGLNVM devices. Therefore the output logic function of the complementary pairs at each node 94(x) for x=0, 1, . . . , n−1, for the input data and the non-volatile data behaves like the logic function of XOR for the two input data operation. It is very straight forward for the nonvolatile arithmetic memory operator module 900 in FIG. 9 to obtain the desired logic voltage signal outputs at nodes 91(0), 91(1), . . . , 91(n−1) for the sum bits S.sub.0, S.sub.1, . . . , S.sub.n-1 and the carry-out bit C.sub.n-1 at the node 92(n−1) for n-bit input volatile data and n-bit configurable non-volatile data.

(32) In an alternative embodiment, the non-volatile half adder 9(0) in the nonvolatile arithmetic memory operator module 900 is replaced by a non-volatile full adder with its carry-in bit set to an initial bit depending on different applications. In a similar manner, the nonvolatile arithmetic memory operator module can be used to realize various types of adders, such as a carry look-ahead adder, a ripple-block carry look-ahead adder, a block carry look-ahead adder, . . . etc.

(33) In one embodiment we apply SGLNVM devices to a nonvolatile arithmetic memory operator module for n-bit multiplication as shown in FIG. 10. The nonvolatile arithmetic memory operator module 100 includes “n” non-volatile bit-multiplication units. Each non-volatile bit-multiplication unit “i” comprises (1) a SGLNVM device pair 110(i) for storing a non-volatile bit “i”; (2) a Transmission Gate (TG) switch 1S1(i) for inputting the data voltage signals A; at node 101(i); (3) a TG switch 1S3(i) for closing a latch 120(i) to output the multiplication bit M.sub.i at node 131(i), for i=0, . . . , n−1. Meanwhile, all SGLNVM devices are initially erased to the low threshold voltage state V.sub.thL as the “high” conductance state defined in FIG. 7c. According to a set of non-volatile data bit string (NB.sub.0, NB.sub.1, . . . , NB.sub.n-1), the SGLNVM devices are also selectively programmed to the high threshold voltage state V.sub.thH as the “low” conductance state for NB.sub.i=“1”, while the unselected SGLNVM devices remain in the “low” threshold voltage state V.sub.thL as the “high” conductance state for NB.sub.i=“0”.

(34) For the non-volatile/volatile bit-multiplication operation (refer to FIG. 7b), the voltage signals of the volatile data A.sub.i at nodes 101(i) are passed to the latches 120(i) by turning on the TG switches 1S1(i) with applying V.sub.DD at nodes S1 and 0 V at the complementary node S1 with the TG switches 1S3(i) off, for i=0, . . . , n−1. After turning off the TG switches 1S1(i) with the TG switches 1S3(i) still off, the control gates of the SGLNVM devices are applied with a voltage pulse V.sub.cg with the voltage amplitude (V.sub.thL+V.sub.DD)<V.sub.cg<V.sub.thH for a short period of time. For NB.sub.i=“0” (the “low” threshold voltage state V.sub.thL), the output voltage at the node 131(i) is always 0 V regardless the input voltages for A.sub.i (either by discharging from V.sub.DD to 0 V or remaining at 0 V). For NB.sub.i=“1” (the “high” threshold voltage state V.sub.thH), the output voltage at the node 131(i) remains the same voltage signals as the input voltages for A.sub.i. That is, the voltage signals at the output M.sub.i are ≈V.sub.DD and 0 V for (A.sub.i=“1” and NB.sub.i=“1”) and (A.sub.i=“0” and NB.sub.i=“1”), respectively. As the timing sequence shown in FIG. 7b, the TG switches 1S3(i) are turned on to latch the final output data in the latches 120(i) after the control gate voltage pulse V.sub.cg is turned off. Finally, the output voltage signals, V.sub.DD for logic state “1” and V.sub.SS for logic state “0” at node 131(i) for n-bit multiplication M.sub.i are obtained for the bit-multiplication of the input data A.sub.i and the non-volatile data NB.sub.i, for .sub.i=0, 1, . . . , n−1, as the same AND logic gate operations for two input sets of volatile data.

(35) The aforementioned description of the preferred embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form or to exemplary embodiments disclosed. Accordingly, the description should be regarded as illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to practitioners skilled in this art. The embodiments are chosen and described in order to best explain the principles of the invention and its best mode practical application, thereby to enable persons skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use or implementation contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents in which all terms are meant in their broadest reasonable sense unless otherwise indicated. The abstract of the disclosure is provided to comply with the rules requiring an abstract, which will allow a searcher to quickly ascertain the subject matter of the technical disclosure of any patent issued from this disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Any advantages and benefits described may not apply to all embodiments of the invention. It should be appreciated that variations may be made in the embodiments described by persons skilled in the art without departing from the scope of the present invention as defined by the following claims. Moreover, no element and component in the present disclosure is intended to be dedicated to the public regardless of whether the element or component is explicitly recited in the following claims.