Voltage-to-time converter architecture for time-domain analog-to-digital converter

Abstract

A voltage-to-time converter (VTC) for a time-domain analog-to-digital converter is disclosed, which provides a time-domain analog-to-digital converter (T-ADC) with low power consumption and high precision. By combining the advantages of current-starving technology, current mirror technology, and body biasing technology, compared with the traditional structure, the VTC and T-ADC achieve excellent performance, such as low power consumption, high linearity, wide input dynamic range, and strong anti-interference to PVT variations. Compared with the traditional voltage-to-time converter, the disclosed voltage-to-time converter has a wider input dynamic range and higher linearity. The input voltage is connected to transistors in the circuit as a body bias, resulting in a very small body current, and no apparent increase in power consumption. The design of a low-power voltage-to-time converter is realized.

Claims

1. A voltage-to-time converter structure for a time-domain analog-to-digital converter, comprising: a first PMOS transistor and a first NMOS transistor, a current mirror comprising a current starving NMOS transistor and a second NMOS transistor, a third NMOS transistor with a fixed bias, a fourth NMOS transistor with a first body bias input, a second PMOS transistor with a second body bias input, and a capacitance; wherein the first PMOS transistor has a source connected with a supply voltage, the first PMOS transistor has a drain connected with a drain of the first NMOS transistor and the capacitance, the connected drains of the first PMOS transistor and the first NMOS transistor provide an output voltage, the first PMOS transistor has a gate connected with a gate of the first NMOS transistor that receive a clock signal; the first NMOS transistor has a source connected to a drain of each of the current starving NMOS transistor and the third NMOS transistor, the current starving NMOS transistor and the third NMOS transistor each have a source connected to a ground potential, the third NMOS transistor has a gate connected to the supply voltage, the current starving NMOS transistor has a gate connected to a gate and a drain of the second NMOS transistor and a source of the fourth NMOS transistor, the second NMOS transistor has a source connected to the ground potential, the fourth NMOS transistor has a drain connected to a drain of the second PMOS transistor, the fourth NMOS transistor has a gate connected to a gate of the second PMOS transistor, the second body bias input receives an input voltage, the drains of the fourth NMOS transistor and the second PMOS transistor receive the clock signal, the second PMOS transistor has a source connected with the supply voltage, and the second body bias input receives both the input voltage and the supply voltage.

Description

DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows a traditional architecture of a voltage-to-time converter.

(2) FIG. 2 is a circuit diagram of the voltage-to-time converter of the present invention.

(3) FIG. 3 shows a simulation result of the voltage-delay curve of the invention.

(4) FIG. 4 shows a simulation result of the voltage-delay curve of the conventional VTC and the invention.

(5) FIG. 5 shows a simulation result of the voltage-delay curve for different process corners of the invention.

(6) FIG. 6 shows a simulation result of the voltage-delay curve for different supply voltages of the invention.

(7) FIG. 7 shows a simulation result of the voltage-delay curve for different temperatures of the invention.

EXAMPLES

(8) The invention is characterized in that the input voltage is used as the body terminal or body bias voltage of a PMOS transistor and an NMOS transistor in a current-controlling branch of a current mirror at the same time, thereby generating a high-linearity drain current of an inverter receiving the controlled or mirrored current. The specific working principle of this circuit is as follows.

(9) Transistors M1 and M2 consist of an inverter. The input terminal of the inverter receives the clock signal Clk. The output terminal outputs the output signal V.sub.out. The transistor M3 is used as a current starving transistor and create a discharge path for the output of inverter circuit to ground. The relationship between the drain current of the branch where M3 is located and the delay time (T.sub.d) of the inverter can be simply expressed as:

(10) $T_d\propto \frac{C_L}{I_{cp}{V}_{DD}}$

(11) Where C.sub.L is the output load capacitance of the inverter, I.sub.cp is the drain current of the inverter branch, and V.sub.DD is the supply voltage. It can be seen from the above formula that the delay can be controlled by changing the load capacitance, the inverter drain current, and the supply voltage to the inverter. In FIG. 1, the control voltage is directly connected to the gate of the current starving transistor. The structure is simple, and the operation is convenient, but its input voltage to delay characteristic is highly non-linear. The formula of the drain current of the M3 transistor is:

(12) $I_{D3}=\frac{1}{2}{\mu }_n{C}_{ox}\frac{W_3}{L_3}{\left(V_{GS3}-V_T\right)}^2\left(1+{\lambda }_3{V}_{DS3}\right)$

(13) It can be seen that there is a quadratic nonlinear relationship between the drain current and the gate-to-source voltage. Using the input voltage as the gate voltage (e.g., to M4 as shown in FIG. 1) cannot guarantee the linearity of the VTC. Besides, the current starving transistor M3 is an NMOS transistor. When the gate-to-source voltage is less than its threshold voltage, M3 turns off and the inverter cannot work. Therefore, the present invention (FIG. 2) added the pull-down NMOS transistor M4, and the gate voltage of M4 receives a fixed bias (e.g., the supply voltage), so that it can eliminate the limitation of the threshold voltage on the NMOS transistor and adjust the gain and linearity of the delay circuit. Even if the input voltage V.sub.in is lower than the threshold voltage of the NMOS transistor M3, the inverter still operates. To solve the problem of non-linearity, the transistor M5 is added to form a current mirror with M3. The drain current of transistor M5 is expressed as

(14) $I_{D5}=\frac{1}{2}{\mu }_1{C}_{ox}\frac{W_5}{L_5}{\left(V_{GS5}-V_T\right)}^2\left(1+{\lambda }_5{V}_{DS5}\right)$

(15) Since V.sub.GS3=V.sub.GS5, λ.sub.3 and λ.sub.5 are both equal to 0 when ignoring the channel length modulation effect, therefore

(16) $\frac{I_{D5}}{I_{D3}}=\frac{W_5/L_5}{W_3/L_3}$

(17) There is a proportional relationship between the leakage current of M5 and the leakage current of M3. The present invention can complete the adjustment of the leakage current of the M3 branch by controlling the current of the M5 branch. How to make the M5 branch produce a high-linearity leakage current becomes the key to the design. The invention adopts body bias technology to realize the control of the voltage to the delay of the circuit. This circuit connects the input voltage to the bodies of the transistors M6 and M7, instead of the gate of M3. The body-to-source voltage on the transistors M6 and M7 generates a highly linear drain current at transistor M5 branch, and thus, at transistor M3 branch. The threshold voltage V.sub.T is a function of the body-to-source voltage (which represents the input signal), and its expression is as follows:
V.sub.T=V.sub.T0+γ(√{square root over (|2ϕ.sub.f−V.sub.BS|)}−√{square root over (|−|2ϕ.sub.f|)})
where V.sub.T0 is the threshold voltage without a body bias, γ is the body effect factor, V.sub.BS is the body-to-source voltage, and ϕ.sub.f is the Fermi potential. The current-starving transistor M3 creates a path for the output of inverter to ground (e.g., when the clock signal turns on the NMOS transistor M2), and the transistor M3 discharges the output load capacitance C to ground. It is easy to know that the fall time of the output delay is determined by the following formula:

(18) $dt=C\frac{dV}{I_D}$

(19) Where C is the parasitic capacitance of the output terminal, dV is the voltage change of the output terminal during the discharge of the voltage from logic high to logic low, and dt is the output delay of the fall time. The body bias applied to transistors M6 and M7 provides a linear relationship between the drain current of the current-starving transistor (that is, the discharge current of the load capacitance) and the body-to-source voltage (which represents the input voltage). The threshold voltage formula can be sorted into the following form:

(20) $V_T=V_{T0}-\gamma \sqrt{.Math.2{\varphi }_f.Math.}+\gamma \left(\sqrt{.Math.2{\varphi }_f.Math.}\right)\left(\sqrt{.Math.1-\frac{V_{BS}}{2{\varphi }_f}.Math.}\right)$

(21) The Taylor series expansion of the above formula is

(22) $\begin{array}{c}{V}_T=V_{T0}-\gamma \sqrt{.Math.2{\varphi }_f.Math.}+\gamma \left(\sqrt{.Math.2{\varphi }_f.Math.}\right)\left(1-\frac{V_{BS}}{2.Math.2{\varphi }_f.Math.}\right)\\ =V_{T0}-\left(\frac{\gamma }{2\sqrt{.Math.2{\varphi }_f.Math.}}\right)V_{\mathrm{BS}}\end{array}$

(23) Then

(24) $V_T^2=V_{T0}^2-\left(\frac{V_{T0}\gamma }{\sqrt{.Math.2{\varphi }_f.Math.}}\right)V_{BS}$

(25) Neglecting the channel length modulation effect, the leakage current formula of the transistor is

(26) $\begin{array}{c}{I}_D=\frac{1}{2}{\mu }_n{C}_{ox}\frac{W}{L}{\left(V_{GS}-V_T\right)}^2\\ =\frac{1}{2}{\mu }_n{C}_{\mathrm{ox}}\frac{W}{L}\left(V_{GS}^2+V_T^2-2V_{GS}{V}_T\right)\end{array}$

(27) Substituting the expressions of V.sub.T and VT.sup.2 into the leakage current equation, assuming μ.sub.nC.sub.ox/2=K, we can deduce

(28) 0$I_D=K\left(V_{GS}^2+V_{T0}^2-\left(\frac{V_{T0}\gamma }{\sqrt{.Math.2{\varphi }_f.Math.}}\right)V_{BS}-2V_{GS}\left(V_{T0}-\left(\frac{\gamma }{2\sqrt{.Math.2{\varphi }_f.Math.}}\right)V_{BS}\right)\right)$

(29) The above formula can be written as follows:

(30) $I_D\cong \frac{K}{2}{\left(V_{GS}-V_{T0}\right)}^2+\frac{K\gamma }{2\sqrt{.Math.2{\varphi }_f.Math.}}\left(V_{GS}-V_{T0}\right)V_{BS}$

(31) Substituting I.sub.D into the delay time expression, then

(32) $dt=C\frac{dV}{I_D}=\frac{\mathrm{CdV}}{\frac{K}{2}{\left(V_{GS}-V_{T0}\right)}^2+\frac{K\gamma }{2\sqrt{.Math.2{\varphi }_f.Math.}}\left(V_{GS}-V_{T0}\right)V_{BS}}$

(33) Since V.sub.GS and V.sub.T0 have nothing to do with the input voltage V.sub.B, the above equation can be simplified to make

(34) $K_1=\frac{K}{2}{\left(V_{\mathrm{GS}}-V_{T0}\right)}^2$$K_2=\frac{K\gamma }{2\sqrt{.Math.2{\varphi }_f.Math.}}\left(V_{GS}-V_{T0}\right)$

(35) Therefore, the delay expression is

(36) $dt=\frac{CdV}{K_I+K_2{V}_{\mathrm{BS}}}=\frac{K_{1}CdV}{K_1^2-K_2^2{V}_{\mathrm{BS}}^2}-\frac{V_{BS}{K}_{2}CdV}{K_1^2-K_2^2{V}_{BS}^2}$

(37) When V.sub.BS is relatively small, V.sub.BS is dominant over V.sub.BS.sup.2 on the dt. The expression of delay time (dt) can then be simplified or approximated to dt=a-bV.sub.BS, where a and b are both constants. The fall time delay of the output signal (i.e., the discharge time) thus has a linear relationship with the input voltage of the body terminal (e.g., when V.sub.BS is relatively small). To obtain a balanced inverter, it is necessary to ensure that the rise time and fall time are equal or substantially equal. The input voltage is thus simultaneously connected to the body input terminals of the NMOS transistor M6 and the PMOS transistor M7. The width-to-length ratio of both M1 and M2 may be set to 2:1.

(38) The propagation delay time of the inverter is mainly determined by the transition time t.sub.PHL from the input logic high level to the output logic low level and the transition time t.sub.PLH from the input logic low level to the output logic high level. These two parameters are completely determined by the inverter rise time and fall time. The propagation delay time t.sub.PD is numerically equal to the average value of the two parameters t.sub.PHL and t.sub.PLH.

(39) $t_{PD}=\frac{t_{PHL}+t_{PLH}}{2}$

(40) FIG. 1 is a circuit diagram of a conventional voltage-to-time converter, and FIG. 2 is a circuit diagram of the voltage-time converter of the invention. Based on the XFAB 0.18 μm CMOS standard process, the two circuits are simulated in the Cadence VIRTUOSO IC6.1.6 system design platform. When the power supply voltage V.sub.DD is 1.8V, the input voltage V.sub.in is analyzed by parametric sweep, where the input voltage range is 0˜1.8V, and 10 sweeping points in total are sampled. As shown in FIG. 3, the solid line is the simulation result of the voltage-delay curve corresponding to the present voltage-to-time converter, and the dotted line is the ideal linear curve. It can be seen that the maximum offset between the voltage-delay curve of the invention and the ideal linear curve does not exceed ±0.2 ps, and the overall linearity is relatively high. In the rail-to-rail input voltage range, the propagation delay time range is 385 ps˜396 ps, the voltage-to-time gain is −6.11 ps/V, and the total power consumption of the VTC is 58.2 nW. To better demonstrate the high linearity characteristics of the present circuit, FIG. 4 is the comparison result of simulating the voltage-delay curves corresponding to the two voltage-to-time converters (VTCs) (the traditional one in FIG. 1 and the present invention in FIG. 2) in the same simulation environment. The solid line is the voltage-delay curve of the circuit of the invention, and the dotted line is the voltage-delay curve of the traditional circuit. It can be seen in FIG. 4 that the present invention has a wider linear input dynamic range, and a better linear characteristic than the traditional circuit. To verify that the circuit of the present invention has a strong ability to resist the interference of process, voltage, and temperature (PVT) variations, the parameter sweep is sequentially performed in the same Cadence tool at different process corners, power supply voltages, and temperatures, adopting the Simple Variable Method. When the power supply voltage is 1.8V and the temperature is 27° C., we perform a parameter sweep of the input voltage at each of the process corners SS (slow-slow), TT (typical-typical), and FF (fast-fast), respectively. The simulation results of the voltage-delay curve over different process corners are shown in FIG. 5. It can be seen that the voltage-delay curve has high linearity under different process corners. When the simulation temperature is 27° C. and the process corner is TT, FIG. 6 shows the voltage-delay curves of a simulation in which the input voltage is swept at power supply voltages of 1.9V, 1.8V, 1.7V, and 1.6V respectively. The change in the power supply voltage didn't affect the linearity of the voltage-delay curves. When the power supply voltage is higher, the delay corresponding to the same input voltage is smaller. When the power supply voltage is fixed at 1.8V and the process corner is TT, a parametric sweep of the input voltage in the simulation was conducted at temperatures of −40° C., 0° C., 27° C. and 80° C., respectively. FIG. 7 shows the corresponding simulation results. It can be seen that the voltage-delay curves have high linearity under different temperature conditions. When the temperature is lower, the delay corresponding to the same input voltage is smaller. The simulation results of FIG. 5, FIG. 6, and FIG. 7 show that the voltage-to-time converter (VTC) of the invention is not sensitive to PVT variations, and has a good performance in maintaining high linearity in different simulation environments.