Abstract
An AND or OR logic device has multiple layers of ferromagnetic material separated from each other by non-magnetic layers of electrically conductive material of atomic thickness, sufficient to generate anti-magnetic response in a magnetized layer. The anti-magnetic response in a layer below a layer magnetized with a polarity is summed in a region which is coupled to an output, the output generating at least one of a AND or OR logic function on applied input magnetization.
Claims
1. A logic device comprising: a lower continuous layer of ferromagnetic material; a thin spacer layer sufficient to invoke a Giant MagnetoResistive (GMR) effect with anti-ferromagnetic response to an adjacent magnetic field; an upper layer comprising a plurality of ferromagnetic regions, the plurality of ferromagnetic regions further comprising: an output ferromagnetic region; at least two logic inputs comprising ferromagnetic regions adjacent to each other and also adjacent to the output ferromagnetic region; a mode input comprising a ferromagnetic region adjacent to one of the logic inputs and also adjacent to the output ferromagnetic region; the at least two logic inputs and mode input provided as a planar magnetic field and generating an anti-ferromagnetic field in the lower continuous layer of ferromagnetic material and generating a superposition magnetic field in a region of the lower continuous layer of ferromagnetic material which is below the output ferromagnetic region.
2. The logic device of claim 1 where the logic device performs an AND logic function when the mode input is 0.
3. The logic device of claim 1 where the logic device performs an OR logic function when the mode input is 1.
4. The logic device of claim 1 where the ferromagnetic material is at least one of an alloy of 80% Ni and 20% Fe.
5. The logic device of claim 1 where the ferromagnetic material has a thickness on the order of 1 nm or on the order of 10 nm.
6. The logic device of claim 1 where the thin spacer layer is Copper or Ruthenium.
7. The logic device of claim 1 where the thin spacer layer has a thickness on the order of 5 nm.
8. The logic device of claim 1 where at least one of a logic input ferromagnetic region, a mode input ferromagnetic region, or the output ferromagnetic region has a rectangular shape.
9. The logic device of claim 1 where the mode input maintains a constant logic value while the at least two logic inputs change state.
10. A logic device comprising: a lower layer of ferromagnetic material, the lower layer of ferromagnetic material coupling an applied magnetic field from one region of the lower layer to another region of the lower layer; a thin spacer layer sufficient to invoke a Giant MagnetoResistive (GMR) effect with anti-ferromagnetic response to an adjacent magnetic field; an upper layer comprising a plurality of ferromagnetic regions, the plurality of ferromagnetic regions further comprising: an output ferromagnetic region; at least two logic inputs comprising ferromagnetic regions adjacent to each other and also adjacent to the output ferromagnetic region; a mode input comprising a ferromagnetic region adjacent to one of the logic inputs and also adjacent to the output ferromagnetic region; the at least two logic inputs and mode input provided as a planar magnetic field and generating an anti-ferromagnetic field in the lower layer of ferromagnetic material and generating a superposition magnetic field in a region of the lower layer of ferromagnetic material which is below the output ferromagnetic region.
11. The logic device of claim 10 where the logic device performs an AND logic function when the mode input is 0.
12. The logic device of claim 10 where the logic device performs an OR logic function when the mode input is 1.
13. The logic device of claim 10 where the ferromagnetic material is at least one of an alloy of 80% Ni and 20% Fe.
14. The logic device of claim 10 where the ferromagnetic material has a thickness on the order of lnm or on the order of 10 nm.
15. The logic device of claim 10 where the thin spacer layer is Copper or Ruthenium.
16. The logic device of claim 10 where the thin spacer layer has a thickness on the order of 5 nm.
17. The logic device of claim 10 where at least one of a logic input ferromagnetic region, a mode input ferromagnetic region, or the output ferromagnetic region has a rectangular shape.
18. The logic device of claim 10 where the mode input maintains a constant logic value while the at least two logic inputs change state.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) FIG. 1A is a cross section of ferromagnetic material layers separated by a non-magnetic layer of thickness sufficient to invoke a ferromagnetic response.
(2) FIG. 1B is a cross section as in FIG. 1A with a thin non-magnetic layer of thickness sufficient to invoke an anti-ferromagnetic response.
(3) FIG. 2A is a cross section view of a two layer IEC with co-planar sections shown in FIGS. 2B and 2C.
(4) FIG. 3 is an exploded perspective view of a two layer logic device.
(5) FIGS. 3A, 3B, and 3C are cross section and planar section views of an AND gate for applied magnetizations.
(6) FIGS. 3D and 3E are planar section views of FIG. 3A showing an AND gate configuration for applied magnetizations.
(7) FIGS. 3F and 3G are planar section views of FIG. 3A showing an AND gate for applied magnetizations.
(8) FIGS. 3H and 3I are planar section views of FIG. 3A showing an AND gate for applied magnetizations.
(9) FIGS. 4A, 4B, and 4C are cross section and planar section views of an OR gate for applied magnetizations.
(10) FIGS. 4D and 4E are planar section views of FIG. 4A showing an OR gate for applied magnetizations.
(11) FIGS. 4F and 4G are cross section and planar section views of FIG. 4A showing an OR gate for applied magnetizations.
(12) FIGS. 4H and 4I are cross section and planar section views of FIG. 4A showing an OR gate for applied magnetizations.
(13) FIG. 5 is an exploded perspective view of a three layer logic device.
(14) FIGS. 5A, 5B, 5C, and 5D are cross section and planar section views of a NAND gate for applied magnetizations.
(15) FIGS. 5E, 5F, and 5G are planar section views of FIG. 5A showing a NAND gate for applied magnetizations.
(16) FIGS. 5H, 5I, and 5J are planar section views of FIG. 5A showing a NAND gate for applied magnetizations.
(17) FIGS. 5K, 5L, and 5M are planar section views of FIG. 5A showing a NAND gate for applied magnetizations.
(18) FIGS. 6A, 6B, 6C, and 6D are cross section and planar section views of FIG. 6A showing a NOR gate for applied magnetizations.
(19) FIGS. 6E, 6F, and 6G are planar section views of FIG. 6A showing a NOR gate for applied magnetizations.
(20) FIGS. 6H, 6I, and 6J are planar section views of FIG. 6A showing a NOR gate for applied magnetizations.
(21) FIGS. 6K, 6L, and 6M are planar section views of FIG. 6A showing a NOR gate for applied magnetizations.
DETAILED DESCRIPTION OF THE INVENTION
(22) As described in the background, it is desired to provide a nanomagnetic logic device which operates at higher temperatures than the prior art. The Interlayer Exchange Coupled (IEC) scheme of the present invention has been shown to offer stronger interaction between thin nanomagnets, resulting in greater scalability and better data retention at the deep sub-micron level, hence allowing magnetic interaction to be manipulated both in the vertical and lateral directions at the same time.
(23) FIG. 1A shows a first ferromagnetic layer 102 separated from a second ferromagnetic layer 106 by a non-magnetic electrically conductive layer 104 such as copper. Where the non-magnetic layer 104 is too thick 104a to invoke the Giant MagnetoRestrictive (GMR) effect, the two ferromagnetic layers 102 and 106 couple magnetic field in the same direction, resulting in ferromagnetic coupling shown in FIG. 1A, where the X symbols represent the tail of a magnetic field vector perpendicular to the plane of the figure. When the thickness of the conductive layer 104 is reduced to just a few hundred angstroms thick, or a deposition of thickness on the order of a few atomic thickness, the two layers demonstrate anti-ferromagnetic coupling, where the magnetic fields are of opposite sense, as shown in FIG. 1B with atomic conductor 104 thickness 104b. FIGS. 2A, 2B, and 2C show the anti-ferromagnetic effect for an example device with lower layer 202 and first upper layer 204 and second co-planar upper layer 204. There the two ferromagnetic regions 204 and 206 of FIG. 2B have a planar magnetic vector pointing to the lower right, the bottom ferromagnetic plane 202 will generate an anti-ferromagnetic planar magnetization of the opposite polarity to the upper right as shown in FIG. 2B.
(24) The ferromagnetic regions may be formed from an alloy such as 80% Nickel (Ni) and 20% Iron (Fe), and the conductive non-ferromagnetic layer 104 may be formed of Ruthenium (Ru), Copper (Cu), or other electrically conductive material. The ferromagnetic regions may be formed in a thickness on the order of 5 nm, and of dimensions on the order of 100 nm×100 nm. In one example of the invention, the conductive non-ferromagnetic layer may be in the range 1 nm to 10 nm thickness, or on the order of magnitude of 1 nm to 10 nm thickness.
(25) FIG. 3 shows an exploded perspective view of an example logic device in a first example of the invention. Bottom layer 304 is a continuous ferromagnetic layer separated by discrete ferromagnetic regions 308 (Input A), 310 (Output), 312 (Input C), and 301 (Input B) formed on ferromagnetic upper layer 302 separated by thin spacer 332. In the present series of figures, it is understood that the particular convention of logic “1” and “0” is arbitrary so long as uniformly applied, but for clarity in understanding the present examples, a “1” will represent a magnetic field pointing generally upwards (or a majority of the field direction is upwards) and in the plane of the drawings, and a “0” will represent a magnetic field point downwards (or a majority of the field direction is downwards) and in the plane of the drawings. Other conventions are possible, this convention is used only for clarity in understanding the invention.
(26) The devices operate with two logic inputs and a mode input, which selects the type of logic function performed. The mode input and logic input have identical response times, and since the magnetization is stored in the ferromagnetic layer until it is changed, the device does not dissipate any power when the magnetic field is not being changed. In general, the magnetic field polarization of the logic inputs and mode input in the upper layer establish anti-ferromagnetic responses in the lower layer. The input ferromagnetic layers and mode ferromagnetic layers generate an anti-ferromagnetic response in the lower ferromagnetic layer, and these anti-ferromagnetic responses generate a superposition of magnetic fields in a region of the lower layer which is separated from and anti-ferromagneticly coupled to an upper layer output ferromagnetic region.
(27) FIG. 3A (with 3B and 3C, 3D and 3E, 3F and 3G, 3H and 3i) show an IEC in cross section for an AND gate function (mode input A=0), and with various logic input B and logic input C expressed as magnetic fields. For the AND case (mode input A=0) shown in FIGS. 3B and 3C where inputs B=0 and C=0, the anti-ferromagnetic field coupled into regions 314, 320, 318 generate a superposition magnetic field orientation in region 316 on the same lower layer, which generates opposite polarity field to produce output value 0 on output region 310. FIGS. 3D and 3E, 3F and 3G, 3H and 3I illustrate the AND mode function for inputs [B,C]=[0,1], [1,0], and [1,1] respectively. The top layer is shown in dashed outline 302, but comprises the discrete bounded ferromagnetic areas 308, 301, 312, and 310 which are formed above the thin conductive layer between planes 302 and 304.
(28) FIGS. 4A, 4B and 4C, 4D and 4E, 4F and 4G, 4H and 4I show an IEC in cross section for an OR gate function (mode input A=1), and with various logic input B and logic input C expressed as magnetic fields. For the OR case (mode input A=1) shown in FIG. 4B where inputs B=0 and C=0, the anti-ferromagnetic field coupled into regions 314, 320, 318 generate a superposition magnetic field orientation in region 316 on the same lower layer, which generates opposite polarity field to produce output value 0 on output region 310. FIGS. 4D and 4E, 4F and 4G, 4H and 4I illustrate the OR mode function for inputs [B,C]=[0,1], [1,0], and [1,1] respectively.
(29) FIG. 5 shows an exploded view of a second example of the invention where continuous bottom ferromagnetic layer 502 (shown in planar section C-C in FIGS. 5A, 5B, 5E, 5H, 5K, 6A, 6B, 6E, 6H, and 6K) is separated from middle layer ferromagnetic regions 503, 506, 508, 510 by a thin electrically conductive non-ferromagnetic material as previously described to generate the anti-ferromagnetic response on the adjacent layer. The device output is taken from a top layer of ferromagnetic material 512 positioned above mezzanine layer 508, and separated a second thin non-ferromagnetic conductive layer sufficient to generate an anti-ferromagnetic response with mezzanine layer 508 to form the device output. The solid outlines 503, 506, 508, 510 indicate the ferromagnetic regions applied with a dashed outline to indicate orientation with respect to lower layer 502.
(30) FIG. 5A (with FIGS. 5B, 5C, and 5D; 5E, 5F and 5G; 5H, 5I, and 5J; 5K, 5L, and 5M) show an IEC in cross section for a NAND gate function (mode input A=0), and with various logic input B and logic input C also expressed as magnetic fields. For the NAND case (mode input A=0) shown in FIGS. 5B, 5C, and 5D where inputs B=0 and C=0, the anti-ferromagnetic field coupled into regions 506, 503, 510 generate a superposition magnetic field orientation in the lower layer 502 region below region 508 of the middle layer, which generates opposite polarity field at the M ferromagnetic region 508 with value 0 which is inverted to 1 on output region 512. FIGS. 5E, 5F, 5G; 5H, 5I, 5J; and 5K, 5L and 5M illustrate the NAND mode function for inputs [B,C]=[0,1], [1,0], and [1,1] respectively.
(31) FIG. 6A (with 6B, 6C, 6D; 6E, 6F, 6G; 6H, 6I, 6J; and 6K, 6L, and 6M) show an IEC in cross section for a NOR gate function (mode input A=1), and with various logic input B and logic input C also expressed as magnetic fields. For the NOR case (mode input A=1) shown in FIGS. 6B, 6C, and 6D where inputs B=0 and C=0, the anti-ferromagnetic field coupled into regions 606, 603, 610 generate a superposition magnetic field orientation in the lower layer 602 region below region 608 of the middle layer, which generates opposite polarity field at the M ferromagnetic region 608 with value 0 which is inverted to 1 on output region 612. FIGS. 6E, 6F, 6G; 6H, 6I, 6J; and 6K, 6L, and 6M illustrate the NOR mode function for inputs [B,C]=[0,1], [1,0], and [1,1] respectively.
(32) In one example of the invention, the mode input 308 of the AND gate of FIGS. 3B, 3D, 3F, and 3H, and OR gate of FIGS. 4B, 4D, 4F, and 4H determines whether the mode of operation as a static or persistent value compared to the logic inputs 301 and 312 which may be comparatively transient or dynamic. In another example of the invention, the mode input 506 of FIGS. 5C, 5F, 5I, 5L, and mode input 606 of FIGS. 6C, 6F, 6I and 6L statically determines whether the device operates as a NOR gate of FIG. 5A or NAND gate of FIG. 6A, while the logic inputs 503 and 510 of FIGS. 5C, 5F, 5I and 5L, and logic inputs 603 and 610 of FIGS. 6C, 6F, 6I and 6L are comparatively transient or dynamic in particular logic level.
(33) The present examples are provided for illustrative purposes only, and are not intended to limit the invention to only the embodiments shown.
