High-switching speed and low-phase-noise-analog synthesizer

Abstract

The present invention is directed to a frequency synthesizer with an improved architecture that eliminates a VCO and a method to build frequency synthesizers for generating high-frequency signals with low phase noise, low spurious, extremely fast switching speed and fine frequency resolution. The synthesizer provides significant improvement in performance, phase noise, switching speed, power, size and cost reduction.

Claims

1. An apparatus, comprising: a microwave synthesizer architecture including a direct digital synthesis (DDS) and a stable reference frequency that are mixed and filtered, one or more largest frequency steps controllable by one or more dividers with fine tuning by said direct digital synthesis forming a seed generator.

2. An apparatus of claim 1, further comprising: a voltage-controlled oscillator configured to follow said seed generator to eliminate noise and spurs from a carrier.

3. An apparatus of claim 2, wherein the microwave synthesizer takes a seed frequency generated by said seed generator and multiplies and translates said seed frequency to continuously cover an octave or more by using mixing, filtering and dividing operations to expand the span of frequency coverage with maintaining degradation of phase noise to less than a fraction of a dB by using a frequency stretching scheme.

4. An apparatus of claim 1, wherein the microwave synthesizer takes a seed frequency generated by said seed generator and multiplies and translates said seed frequency to continuously cover an octave or more by using mixing, filtering and dividing operations to expand the span of frequency coverage with maintaining degradation of phase noise to less than a fraction of a dB by using a frequency stretching scheme.

5. The apparatus of claim 3, wherein said microwave synthesizer is configured to raise said seed frequency up to an octave frequency range from a base value to a broader frequency range, by using one or more harmonic multipliers, dividers and filters that are switched in and out to extend an output to between low and high frequencies.

6. The apparatus of claim 4, wherein said microwave synthesizer is configured to raise said seed frequency up to an octave frequency range from a base value to a broader frequency range, by using one or more harmonic multipliers, dividers and filters that are switched in and out to extend an output to between low and high frequencies.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing in which like reference numerals are used to refer to the same or similar elements.

(2) FIG. 1 is a schematic representation illustrating a conventional phase-locked loop synthesizer (“PLL”).

(3) FIG. 2 is a schematic representation illustrating a conventional PLL with direct current (“DC”) tuning and frequency offsetting to improve phase noise and speed of frequency switching.

(4) FIG. 3 is a graphical representation illustrating a polluting spurious signal generated as a mixer product in conventional synthesizer employing a frequency conversion.

(5) FIG. 4 is a schematic representation of a classical analog synthesizer as proposed in U.S. Pat. No. 4,725,786.

(6) FIG. 5 is a schematic representation of a VCO based, fast-switching, low-phase noise synthesizer as proposed in U.S. Pat. No. 9,628,066.

(7) FIG. 6 is an overall schematic representation of an improved architecture for a synthesizer in accordance with the present invention.

(8) FIG. 7 is an expanded view of schematic representation of a seed generator portion for the improved architecture.

(9) FIG. 8 is a schematic representation of another method of the seed generator using a narrow band VCO/Dielectric Resonator Oscillator (“DRO”) source for the improved phase noise performance.

(10) FIG. 9 is a schematic representation of the seed expander generating wide band tuning capability with no penalty of phase noise.

(11) FIG. 10 is a schematic representation of a harmonic multiplier stage for generation of microwaves and multi-decade tuned broad band signal from the output of the expander.

(12) FIG. 11 is a flow chart of the improved overall approach in accordance with the present invention.

DETAILED DESCRIPTION

(13) The following detailed description of embodiments presents various descriptions of specific embodiments of the invention. However, the invention can be embodied in a multitude of different ways as defined and covered by the claims. In this description, reference is made to the drawings, where like reference numerals may indicate identical or functionally similar elements.

(14) The architecture illustrated in FIG. 6 has three portions, namely, a seed generator 610 through 628, a seed expander 629 through 668, and a harmonic multiplier 669 through 682, each of which are shown in FIG. 7, FIG. 8, FIG. 9 and FIG. 10 and are described in detail below.

(15) Referring now to FIG. 7 and FIG. 8, they illustrate two of the many ways by which a narrow band seed may be generated. In the first part shown as a seed generator designated by reference numerals 711, 712, 713 . . . through 728, the improved architecture generates a narrow band of signal, by using a carefully selected band of DDS signal indicated be reference numeral 716 (that provides a very high resolution in tuning), which is added to a very clean high frequency source 718 and filtered at 721, then divided by a very low noise divider 723, resulting in an ultra-clean signal 724 with very low spurious signals, which is then added to a very clean high frequency source 726 to form a seed 729. The phase noise performance of the signal with clean dividers and multipliers is provided by the equation:
F.sub.ref pn+20*log.sub.10(C1*C3)+20*log.sub.10 {(C1*F.sub.ref pn+DDS.sub.output pn)/D1)}.
Under normal conditions, in real world scenarios, the contribution due to:
20*log.sub.10 {(C1*F.sub.ref pn+DDS.sub.output pn)/D1)}
would be negligible. Thus, the improved architecture is able to derive a fine resolution variable frequency seed with near phase noise performance of:
F.sub.ref pn+20*log.sub.10(C1*C3).

(16) Referring now to FIG. 8, the improved architecture uses a narrow-band, low-noise VCO PLL designated by reference numerals 828, 825, 827 as the filter to generate and even enhance phase noise at larger offsets. A reference signal F.sub.ref 810 outputs a high purity signal that is harmonically multiplied by a multiplier C.sub.1 812 to give a signal 818 and another branch feed a DDS 815 after a multiplier C.sub.2 813. The output signal 814 forms the reference to the DDS. The DDS output is then added to signal 818 for translation to a higher frequency band output 820. This signal is filtered by a band pass filter FL1 821 and the cleaned signal 822 is divided by a divider D.sub.1 823 and becomes the reference signal 824 for the phase detector PD, the output of which designated by reference numeral 828 drives a narrow band low noise VCO or DRO 829 to generate seed Fseed 830. A portion of the same signal serves as a feedback to a mixer 825 to be mixed with a reference signal 826 generated by multiplication of signal 818 by a multiplier C3 817. The phase noise performance of the signal with clean dividers and multipliers is provided by the equation:
F.sub.ref pn+20*log.sub.10(C.sub.1*C.sub.3)+20*log.sub.10 {(C.sub.1*F.sub.ref pn+DDS.sub.output pn)/D1)}.

(17) Under normal conditions, in real world scenarios, the contribution due to 20*log.sub.10 {(C.sub.1*F.sub.ref pn+DDS.sub.output pn)/D1)} would be negligible. Thus, the improved architecture is able to derive a fine resolution variable frequency seed with near phase noise performance of F.sub.ref pn+20*log.sub.10(C1*C3).

(18) The second part of the improved architecture is called an expander of the seed. As shown in FIG. 9 a F.sub.seed signal 929 is divided by a divider 931 and its output or its harmonics 932 is mixed using a mixer 936 to generate an expanded form at 937. It is filtered using narrow band filters designated by reference numerals 938, 939, 940, 941, then switched in and out using switches 985 and 986 to eliminate unwanted harmonic mixing products. The same scheme of expansion as in two more stages as those designated by reference numerals 943, 944, 945, 946, 949, forming a stretcher and those designated by reference numerals 951, 952, 953, 954 as filters Switched in and out using Switch 987 and 988 as needed. Depending on the Fbase width required one may add more stages of seed expander. Here a third stage formed by components designated by reference numerals 956, 957, 959, 962 and filters designated by reference numerals 964, 965, 966, 967 Switched in and out using Switch 990 and 991 as needed. The signals from earlier stages may also be forwarded using switches 989 and 992 as shown above to obtain maximum utilization of the various stages. FIG. 9 shows a scheme of F.sub.seed expansion to F.sub.base even up to cover over an octave width, although not always necessary depending on multipliers used in the final section. For example, if harmonics in 669 varies as 3,4,5 then F.sub.base_max/F.sub.base_min=1.33 is sufficient to make the resultant final signal an octave covering.

(19) The seed expander as in FIG. 9 results in phase noise degradation provided by the equation:
20*Log.sub.10 {(C4+C5/D2)*(C6+C7/D3)*(C8+C9/D4)}

(20) As long as C4>5*C5/D2 and C6>5*C7/D3 and C8>5*C9/D4, the total noise added with respect to an ideal case of 20*Log.sub.10 {(C4*C6*C8)} with Fraction of a dB penalty of noise due to tuning width expansion, and is negligible while the tuning range of the seed is expanded by many folds.

(21) With a variable F.sub.seed varying between F.sub.seed1 to F.sub.seed2 by equating:

(22) F.sub.seed1*C4+F.sub.seed1*C5/D2.sub.min to F.sub.seed2*C4+F.sub.seed2*C5/(D2.sub.min+1), a continuous coverage in output spectrum can be ensured. In the simplest case of C4 and C5 equated to one, this reduces such that D2.sub.min can be evaluated as integer part of Square root of the ratio between the F.sub.seed1/(F.sub.seed2−F.sub.seed1) and can be written as D.sub.2min=integer {[F.sub.seed1/(F.sub.seed2−F.sub.seed1)].sup.1/2}.
Similarly, with a variable F.sub.seed varying between F.sub.seed1 to F.sub.seed2 by equating:
F.sub.seed1*C4−F.sub.seed1*C5/(D2.sub.min+1) to F.sub.seed2*C4−F.sub.seed2*C5/D2 mm, a continuous coverage in output spectrum may be ensured. In the simplest case of C4 and C5 equated to one, this reduces such that D2.sub.min may be evaluated as integer one greater than square root of the ratio between the F.sub.seed1/(F.sub.seed2−F.sub.seed1) and the equation may be written as:
D.sub.2min=integer{1+[F.sub.seed1/(F.sub.seed2−F.sub.seed1)].sup.1/2}.

(23) In a normal VCO, for every doubling of tunable band width, the phase noise performance tends to degrade by 6 dB [20 log.sub.10(2)]. However, in the above scheme, the degradation in phase noise may be kept to be a fraction of a dB. Thus, a reference or its multiplied form (with 20 log(n) where n is the multiplication factor) is added to a frequency divided form or its harmonics to give an expanded version of high purity signal. This signal passed through appropriate band limiting filters form a wide tuning source with extremely low-phase noise and very low spurious content. Using a signal source in few GHz range, it is possible to easily expand the tuning range using very clean frequency dividers using this technique. Thus, this improved architecture obtains a wide tuning signal with extremely low phase noise. Even if one was to use multiple phased lock loops to achieve this tuning range expansion, the amount of circuitry required, and the power and space consumption would be greatly increased. The number of stages of the expander used depends on the requirements as calculated depending on the output requirements.

(24) Referring now to FIG. 10, in the third part shown, this signal may further be multiplied up using harmonic multipliers C.sub.i 1069 or divided down using dividers (D.sub.5 1076, D.sub.i 1078, D.sub.n 1080) to and along with appropriate filtering schemes (FL15 1071, FL16 1072, FL17 1073, FL18 1074) along with Switches 1093 and 1094 and Filters (1077,1079,1081 etc) along with switches 1096 and 1097, to obtain signals that stretch from very low frequency to many tens of gigahertz at F.sub.out 1082. In many high frequency applications like 5G communications, these signals with very good near carrier phase noise significantly improve performance of the systems.

(25) An important advantage to point out is that tuning is accomplished by setting simple digital registers for things such as divide numbers. These are inherently fast as opposed to the pre-tuning and frequency slewing of a PLL and its VCOs, regardless of the exact architecture.

(26) Another convenient fact is the complete use of digital circuits, thus avoiding delays associated with PLL tuning time, delays, avoidance of false lock, temperature or time effects resulting in extremely fast switching, highly stable signal source. By careful choice of filters and frequency bands, it is possible to obtain very low spurious signal outputs.

(27) Another possible application of the extremely clean signal obtained from the stretcher is to use it as a reference source to tune the integrated low form factor VCO controlled circuits.

(28) Thus, the improved architecture has several unique advantages as follows:

(29) very high speed of frequency switching; Very low phase Noise; Immunity from Component aging or temperature effects; Very low physical space occupied; architecture is not susceptible to lock errors; and reasonably fine resolution is implemented in one loop (much finer than F.sub.pd), requiring much less tune range in F.sub.ref section.

(30) Therefore, as compared to conventional PLL synthesizers, the improved method provides significant performance improvement, reliability, low phase noise, fast switching speeds and very compact, low-cost synthesizers.

(31) Referring now to FIG. 11, a simplified flow chart is illustrated explaining the various functions involved in this new architecture. This figure illustrates the way by which a high purity fixed reference source 1100 is passed through a seed generator 1110 to generate a high purity narrow band reference signal. This signal tuning band width is expanded using a spreader 1120 which adds almost no noise (as compared to conventional degradation of 6 dB for every doubling of tuning band width. This expanded tuning band width signal F.sub.base is sent through harmonic multiplier, dividers and filter stage 1130 to generate high performance signals varying from few ten MHz to tens of GHz.

(32) In the description above, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of this technology. It will be apparent, however, that this technology can be practiced without some of these specific details. In other instances, structures and devices are shown in block diagram form in order to avoid obscuring the innovative aspects. For example, the present technology is described by an example implementation above with reference to particular hardware and software.

(33) It should be recognized that reference in the specification to “one implementation or embodiment” or “an implementation or embodiment” simply means that a particular feature, structure, or characteristic described in connection with the implementation or embodiment is included in at least one implementation or embodiment of the technology described. The appearances of the phrase “in one implementation or embodiment” in various places in the specification are not necessarily all referring to the same implementation or embodiment.

(34) Some portions of the detailed descriptions above are presented in terms of equations, which are algorithms and symbolic representations of operations that may be implemented in circuitry or on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those knowledgeable in the data processing and electronic arts to most effectively convey the substance of their work to others in the art. An algorithm and or equation is here, and generally, conceived to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers or the like.

(35) It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise, as apparent from the following discussion, it is appreciated that throughout the description here, any discussions utilizing terms such as “processing” or “computing” or “calculating” or “determining” or “displaying” or the like, refer to the action and processes of an electronic or computer system, or similar electronic component or computing device, that may manipulate and transforms data represented as physical (electronic) quantities within associated electronic or computer system's registers and memories into other data similarly represented as physical quantities within the electronic system or computer system memories or registers or other such information storage, transmission or display devices.

(36) The present technology with circuitry maybe used in an apparatus for performing the operations described and more and the processes described may be associated with computer programs for operating algorithms used for the manufacture or operation of the electronic systems described here. This apparatus may be specially constructed for the required purposes, or it may be associated with at least a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer to thereby create a special-purpose computer. Such a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, flash memories including USB keys with non-volatile memory or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

(37) The present technology can take the form of an entirely hardware embodiment or an implementation containing both hardware and software elements. In some implementations, this technology maybe at least partially implemented in software, which includes but is not limited to, firmware, resident software, microcode, etc.

(38) Furthermore, the process of implementing or building this technology may use a computer program product accessible from a computer-usable or computer-readable medium providing program code for use by or in connection with a computer or any instruction execution system. For the purposes of this description, the steps of the overall process are implemented on a computer-usable or computer readable medium, which can be any apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.

(39) The above description of the embodiments of the present invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the present invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching.