COMPENSATION CIRCUIT FOR DELTA-SIGMA MODULATORS, CORRESPONDING DEVICE AND METHOD

Abstract

A delta-sigma modulation circuit has a sampling period and, in operation, generates a delta-sigma modulated signal based on the analog input signal. The delta-sigma modulation circuit includes: a first integrator; an analog-to-digital converter; a feedback-loop coupled between an input of the first integrator and the output interface; a second integrator coupled between the first integrator and the analog-to-digital converter. The delta-sigma modulation circuit has loop-delay compensation circuitry having a plurality of switches. The loop delay compensation circuitry, in operation, controls the plurality of switches based on a time interval of a duration of half the sampling period and generates a loop-delay compensation signal.

Claims

1. A device, comprising: an analog signal input, which, in operation, receives an analog input signal; and a delta-sigma modulation circuit having a sampling period and coupled to the analog signal input, wherein the delta-sigma modulation circuit, in operation, generates a delta-sigma modulated signal based on the analog input signal, the delta-sigma modulation circuit including: a modulated signal output, which, in operation, outputs the delta-sigma modulated signal; a first integrator; an analog-to-digital converter coupled to the modulated signal output; a feedback-loop coupled between the modulated signal output and an input of the first integrator; a second integrator coupled between the first integrator and the analog-to-digital converter; and loop-delay compensation circuitry having a plurality of switches, wherein the loop delay compensation circuitry, in operation, controls the plurality of switches based on a time interval of a duration of half the sampling period and generates a loop-delay compensation signal.

2. The device of claim 1, wherein the loop-delay compensation circuitry includes a derivative circuit coupled between an output of the first integrator and the plurality of switches.

3. The device of claim 2, wherein the loop-delay compensation circuitry comprises a third integrator coupled to an output of the plurality of switches.

4. The device of claim 3, wherein, the feedback-loop includes: a first adder having a first input coupled to the analog signal input and an output coupled to an input of the first integrator; a first digital-to-analog converter coupled between the modulated signal output and a second input of the first adder; a second adder having a first input coupled to an output of the first integrator and an output coupled to an input of the second integrator; and a second digital-to-analog converter coupled between the modulated signal output and a second input of the second adder; and the loop-delay compensation circuitry comprises a third adder having a first input coupled to an output of the second integrator, a second input coupled to an output of the third integrator and an output coupled to the analog-to-digital converter.

5. The device of 4 claim, wherein, the first digital-to-analog converter, in operation, generates a first weighted feedback signal; and the second digital-to-analog converter, in operation, generates a second weighted feedback signal.

6. The device of claim 3, wherein, the feedback-loop includes: a first adder having a first input coupled to the analog signal input and an output coupled to an input of the first integrator; and a first digital-to-analog converter coupled between the modulated signal output and a second input of the first adder; and the loop-delay compensation circuitry comprises a second adder having a first input coupled to an output of the second integrator, a second input coupled to an output of the third integrator and an output coupled to the analog-to-digital converter.

7. The device of claim 6, wherein, the first digital-to-analog converter, in operation, generates a first weighted feedback signal.

8. The device of claim 6, wherein, the delta-sigma modulation circuit includes a third adder coupled between the output of the second integrator and the second adder, the third adder having a first input coupled to an output of the first integrator, a second input coupled to the output of the second integrator and an output coupled to the first input of the second adder.

9. The device of claim 8 wherein the delta-sigma modulation circuit comprises an inverter coupled between the output of the first integrator and the first input of the third adder.

10. The device of claim 2, wherein, the feedback-loop includes: a first adder having a first input coupled to the analog signal input and an output coupled to an input of the first integrator; a first digital-to-analog converter coupled between the modulated signal output and a second input of the first adder; a second adder having a first input coupled to an output of the first integrator and an output coupled to an input of the second integrator; and a second digital-to-analog converter coupled between the modulated signal output and a second input of the second adder; and an output of the loop-delay compensation circuitry is coupled to a third input of the second adder.

11. The device of claim 10, wherein, the first digital-to-analog converter, in operation, generates a first weighted feedback signal; and the second digital-to-analog converter, in operation, generates a second weighted feedback signal.

12. The device of claim 2, wherein, the feedback-loop includes: a first adder having a first input coupled to the analog signal input and an output coupled to an input of the first integrator; and a first digital-to-analog converter coupled between the modulated signal output and a second input of the first adder; and the delta-sigma modulation circuit includes: a second adder having a first input coupled to an output of the first integrator, a second input coupled to an output of the loop-delay compensation circuitry, and an output coupled to the second integrator; and a third adder having a first input coupled to an output of the first integrator, a second input coupled to an output of the second integrator and an output coupled to the analog-to-digital converter.

13. The device of claim 12, wherein, the first digital-to-analog converter, in operation, generates a first weighted feedback signal.

14. The device of claim 12, wherein, the delta-sigma modulation circuit comprises an inverter coupled between the output of the first integrator and the first input of the third adder.

15. The device of claim 2, wherein, the first integrator comprises a first differential amplifier; and the second integrator comprises a second differential amplifier.

16. The device of claim 15, wherein the first differential amplifier has differential input node terminals and differential output node terminals with resistor/capacitor (RC) feedback networks coupled between the differential output node terminals and the differential input node terminals.

17. The device of claim 16, wherein the second differential amplifier has differential input node terminals and differential output node terminals with RC feedback networks coupled between the differential output node terminals and the differential input node terminals, wherein the RC feedback networks of the second differential amplifier, in operation, provide virtual ground nodes; and the differential output node terminals of the first differential amplifier are coupled to the virtual ground nodes of the second differential amplifier via respective capacitances and switches of the plurality of switching circuits.

18. A method, comprising: receiving an analog input signal; and generating a digital delta-sigma modulated signal using a sampling period, wherein the generating the digital delta-sigma modulated signal includes: generating a feed-back signal based on the digital delta-sigma modulated signal; combining the feedback signal with the analog input signal, generating a difference signal; integrating the difference signal; generating a loop-delay compensation signal based on the integrated signal by controlling a plurality of switches based on a time interval of a duration of half the sampling period; and generating an intermediate signal based on the integrated signal and the loop-delay compensation signal; and sampling the intermediate signal using the sampling period, generating the digital delta-sigma modulated signal.

19. The method of claim 18 wherein generating the loop-delay compensation signal includes generating a derivative of the integrated difference signal.

20. The method of claim 19, comprising: generating a second feed-back signal based on the digital delta-sigma modulated signal; and combining the second feedback signal with integrated difference signal; integrating the combined second feedback signal and integrated difference signal, generating a second intermediate signal; and generating the intermediate signal by combining the second intermediate signal and the loop-delay compensation signal.

21. The method of claim 19, comprising: integrating the integrated difference signal, generating a second integrated signal; combining the integrated difference signal and the second integrated signal, generating a second intermediate signal; and combining the second intermediate signal and the loop-delay compensation signal, generating the intermediate signal.

22. The method of claim 19, comprising: generating a second feed-back signal based on the digital delta-sigma modulated signal; combining the second feedback signal with integrated difference signal and the loop-delay compensation signal, generating a second intermediate signal; and generating the intermediate signal by integrating the second intermediate signal.

23. The method of claim 19, comprising: combining the integrated difference signal and the loop-delay compensation signal; integrating the combined integrated difference signal and loop-delay compensation signal, generating a second intermediate signal; and generating the intermediate signal by combining the second intermediate signal and the integrated difference signal.

24. The method of claim 18, comprising: integrating the difference signal using a first differential amplifier; generating a second feed-back signal based on the digital delta-sigma modulated signal; generating a second intermediate signal based on the integrated difference signal, the loop-delay compensation signal and the second feed-back signal; and generating the intermediate signal by integrating the second intermediate signal using a second differential amplifier.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0013] One or more embodiments will now be described, by way of example only, with reference to the annexed figures, wherein:

[0014] FIG. 1 is a general block diagram of a conventional delta-sigma converter;

[0015] FIG. 2 is a block diagram of an exemplary implementation of a converter as illustrated in FIG. 1;

[0016] FIG. 3 is a block diagram exemplary of excess loop delay (ELD) affecting a circuit as exemplified in FIG. 2;

[0017] FIG. 4 is a block diagram exemplary of an approach in evaluating the effects of ELD in a circuit as exemplified in FIGS. 2 and 3;

[0018] FIG. 5 is exemplary of an approach in modelling ELD in a digital-to-analog (DAC) converter;

[0019] FIG. 6 is a diagram exemplary of possible effects of ELD in a circuit as exemplified in FIGS. 2 and 3;

[0020] FIG. 7 is a block diagram exemplary of a possible approach in countering ELD;

[0021] FIG. 8 is a diagram, similar to the diagram of FIG. 6, exemplary of possible results in countering ELD with the approach of FIG. 7;

[0022] FIG. 9 is a block diagram exemplary of another possible approach in countering ELD;

[0023] FIG. 10 is a block diagram of an integrator;

[0024] FIGS. 11 and 12 are block diagrams useful in discussing certain principles underlying certain embodiments as per the instant description;

[0025] FIG. 12A is a diagram, similar to the diagrams of FIGS. 6 and 8, exemplary of possible ELD performance of a block diagram as exemplified in FIG. 12;

[0026] FIGS. 13A and 13B are block diagrams exemplary of embodiments as per the instant description;

[0027] FIGS. 14A to 14E are diagrams exemplary of a possible time behavior of certain signals in embodiments as per the instant description;

[0028] FIG. 15 is a diagram, similar to the diagrams of FIGS. 6, 8 and 12A, exemplary of possible ELD performance of a block diagram as exemplified in FIG. 13A;

[0029] FIGS. 16A and 16B are block diagrams exemplary of possible embodiments as per the instant description; and

[0030] FIGS. 17 and 18 are circuit diagrams exemplary of possible implementation of embodiments.

DETAILED DESCRIPTION

[0031] In the following description, various specific details are given to provide a thorough understanding of various exemplary embodiments of the present specification. The embodiments may be practiced without one or several specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring various aspects of the embodiments. Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the possible appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0032] The headings/references provided herein are for convenience only, and therefore do not interpret the extent of protection or scope of the embodiments.

[0033] A block diagram of a conventional delta-sigma analog-to-digital converter (ADC) 10 is presented in FIG. 1, where H.sub.1(s) denotes the transfer function (TF) of an input loop filter (LF) supplied with an analog input signal V.sub.IN(t).

[0034] The block designated A/D represents a quantizer clocked at a period T.sub.S which generates a (time-discrete) digital output signal D.sub.OUT[n].

[0035] The block designated D/A represents a digital-to-analog converter (briefly, DAC) which is sensitive to the digital output signal D.sub.OUT[n], re-converts that digital signal to analog and supplied the analog re-converted signal to a feedback loop filter transfer function H.sub.2(s).

[0036] As noted, such an arrangement is conventional in the art, which makes it unnecessary to provide a more detailed description herein.

[0037] Also, throughout this description, unless the context indicates otherwise: [0038] like parts or elements will be indicated in the figures with like reference symbols, so that a related description will not be unnecessarily repeated; [0039] a same designation (V.sub.IN, or D.sub.OUT, for instance) will be used for simplicity to refer both to a certain signal and to a circuit node/element at which such a signal may be present, and [0040] the designation “adder node” will be applied to certain circuit nodes where two or more signals are added together: as known to those of skill in the art, such nodes can be “with sign”, namely nodes where a certain signal is added with one or more other signals with a negative sign, that is subtracted from the combination. Stated otherwise, designating a node as an adder node does not imply that the signals added at that node are added with a same sign.

[0041] FIG. 2 is a block diagram exemplary of a possible implementation of an arrangement 10 as exemplified in FIG. 1 in the form of a second-order CIFB (cascade of integrator with feedback) modulator, suited to be implemented using a fully-differential topology, for instance.

[0042] The following designations apply in the diagram of FIG. 2: [0043] V.sub.IN=(analog) input signal; [0044] y.sub.1(t)=output from a first integrator (l/s) 201 supplied with the addition, obtained at a first node 301, of the input signal V.sub.IN and a feedback term obtained from D.sub.OUT via a DAC D/A.sub.2 multiplied by a coefficient k.sub.2 (for simplicity, this can be as assumed to be included in the DAC); as discussed previously, the node 301 can be an adder node “with sign”, where the feedback term obtained via a DAC D/A.sub.2 weighed by k.sub.2 is in fact subtracted from the input signal V.sub.IN as conventional in a delta-sigma modulator; [0045] y.sub.2(t)=output from a second integrator (l/s) 202 supplied with the combination, obtained at a second adder node 302, of the output y.sub.1(t) from the first integrator 201 and a feedback term obtained from D.sub.OUT via a DAC D/A.sub.1 multiplied by a coefficient k.sub.1 which (again for simplicity, this can be assumed to be included in the DAC and/or have associated a negative sign); and [0046] D.sub.OUT=modulator output obtained by sampling the signal y.sub.2(t) at a quantizer A/D with a sampling period T.sub.S.

[0047] In the exemplary structure of FIG. 2, two DACs, D/A.sub.1 and D/A.sub.2, are used to implement two feedback coefficients k.sub.1, k.sub.2 (this is essentially what is indicated as H.sub.2(s) in FIG. 1).

[0048] For simplicity of explanation and without loss of generality, one may assume T.sub.S=1s as an exemplary sampling period plus k.sub.1=1.5 k.sub.1=1.5and k.sub.2=1 as the feedback coefficients, this resulting in a Noise Transfer Function (NTF) for the modulator 10 in the form:

NTF(z)=(1−z.sup.−1).sup.2

[0049] FIG. 3 is an exemplary representation of the phenomenon currently referred to as excess loop delay (ELD) which, as already discussed in the foregoing, may affect a circuit as exemplified in FIG. 2.

[0050] As discussed, throughout this description, unless the context indicates otherwise, like parts or elements will be indicated in the figures with like reference symbols and a description of parts or elements already described will not be repeated for each and every figure. In FIG. 3 the effect of excess loop delay is represented as a delay block z.sup.−r in the feedback signal path from the output D.sub.OUT to the inputs to the two DACs, D/A.sub.1 and D/A.sub.2.

[0051] A practical way of representing the impact of ELD on the impulse response IR of an arrangement as exemplified in FIGS. 2 and 3 is shown in the block diagram of FIG. 4. There, an “open loop” condition is assumed where the quantizer A/D is disconnected and an ideal (time-discrete) digital impulse δ(n) is applied to the inputs of the two DACs, D/A.sub.1 and D/A.sub.2 with a “normalized” delay r applied thereto.

[0052] Referring for simplicity to the (otherwise common) case of No-Return-to-Zero (NRZ) DACs, the output of each DAC, namely D/A.sub.1 and D/A.sub.2, will be a delayed rectangular pulse whose length equals the sampling period T.sub.S as exemplified in FIG. 5.

[0053] One may then assume that, in a system as exemplified in FIGS. 2 and 3 (with the effect of ELD modeled by a delay block z.sup.−r as in FIGS. 3 and 4), the delayed pulse from each DAC pulse is injected in the loop filter weighted with the corresponding coefficient k.sub.1 or k.sub.2 as exemplified in FIG. 4 (which can be generalized to the case of a n-th order modulator with a number n of different DACs D/A.sub.1, D/A.sub.2, . . . , D/A.sub.n and respective coefficients k.sub.1, k.sub.2, . . . , k.sub.n).

[0054] In the exemplary case considered herein of a second order CTDSM, the effect of ELD on the behavior (impulse response or IR) of the circuit can be assessed as illustrated in FIG. 6.

[0055] There, the output signal y.sub.2(t) from the second integrator is plotted as a function of time for τ=0 (ideal behavior, dashed line) and τ=0.25 (ELD-affected impulse response, continuous line) together with sampled versions spaced by the sampling period T.sub.S highlighted by dots.

[0056] FIG. 6 shows that ELD causes an alteration of the impulse response IR of the system resulting in modulator performance degradation.

[0057] Various ELD compensation techniques have been proposed in order to address that drawback.

[0058] For instance, B. Benabes, M. Keramat and R. Kielbasa in: “A methodology for designing continuous-time sigma-delta modulators”, in Proc. Eur. Des. Test Conf., vol. 1, pp. 46-50, 1197 disclose an ELD compensation approach which involves tuning the loop filter coefficients k.sub.1C, k.sub.2C (which correspond to k.sub.1, k.sub.2 discussed previously) and introducing a direct feedback path via a further DAC, namely D/A.sub.0 closed with an associated coefficient k.sub.0C on the quantizer as exemplified in FIG. 7. There, the quantizer D/A is shown supplied with a signal y.sub.3(t) obtained by combining at an adder node 303 at the output of the second integrator 202 the signal y.sub.2(t) with the signal from D/A.sub.0 with an associated coefficient k.sub.0C.

[0059] It is again noted that, throughout this description, unless the context indicates otherwise, like parts or elements are indicated with like reference symbols so that a related description will not be unnecessarily repeated for brevity.

[0060] A solution as exemplified in FIG. 7 facilitates ELD compensation as exemplified in FIG. 8 where an ELD-affected impulse response (ELD—continuous line) as already presented in FIG. 6 is portrayed against an ELD-compensated (CELD—dashed line) together with samples SIIR of the “ideal” impulse response IR spaced by the sampling period T.sub.S highlighted by dots.

[0061] Such a result is however at the expense of an extra DAC (D/A.sub.0 in FIG. 7) and an associated additional summing amplifier for the node 303. This may be expensive in terms of area and current consumption, which makes such a solution hardly appealing for low-power designs.

[0062] The diagram of FIG. 9 (where parts or elements already discussed are again indicated with like reference symbols and are not described for brevity) is exemplary of an alternative approach that avoids the introduction of expensive extra-hardware in compensating ELD by resorting to a PI (proportional-integral) element as discussed in M. Keller, A. Buhmann, J. Sauerbrey, M. Ortmanns and Y. Manoli, “A Comparative Study on Excess-Loop-Delay Compensation Techniques for Continuous-Time Sigma-Delta Modulators”, IEEE Transaction on Circuits and Systems-I: Regular Papers, vol. 55, no. 11, pp. 3480-3487, December 2008.

[0063] In such a solution (as disclosed in M. Vadipour et al., “A 2.1 mW/3.2 mW Delay-Compensated GSM/WCDMA sigma-delta Analog-Digital converter”, in Proc. IEEE Symp. VLSI circuits, pp180-181, 2008) the coefficient k.sub.0C is “embedded” in a modified second integrator 202”.

[0064] In that way, the inner loop coefficient k.sub.1C may concur with the proportional path represented by the coefficient k.sub.0C in providing a contribution to the impulse response IR of the system whose effect is the same of the direct feedback loop presented in Benabes et al. (already cited)—see FIG. 7.

[0065] A possible implementation of this concept may involve using a resistor R.sub.F in series to an integrating capacitance CF in the feedback loop of an otherwise conventional integrator 100 constructed around an amplifier (an OpAmp, for instance) 102 as exemplified in FIG. 10. Such an integrator circuit, providing an integrated output voltage V.sub.OUT(s) as a function of an input current I.sub.IN(s) can be used in the second (active) integrator in a diagram as exemplified in FIG. 9 to embed therein a proportional path with (very) simple hardware.

[0066] It is noted that a loop as exemplified in FIG. 9 provides effective compensation. Removing an (inner) loop as in the case of single-loop architectures definitely militates against using a solution as proposed by Vadipour et al. (as cited previously).

[0067] There, a feedforward path with a weighing coefficient k.sub.FF is introduced around the second integrator 202 to facilitate loop stability saving one feedback DAC. As a result, effectively compensating ELD in an architecture as shown in FIG. 11 involves resorting to the solution of Benabes et al. (already repeatedly cited), at the expense of extra DAC associated with the quantizer.

[0068] It is otherwise noted that compensating ELD in a CTDSM does not involve reshaping the delayed impulse response (IR) to match the ideal IR at each every instant: indeed, a satisfactory result can be achieved acting (even) just when the curves are sampled by the quantizer.

[0069] One or more embodiments provide an ELD compensation approach which facilitates addressing the limitations of the solutions discussed in the foregoing, by facilitating ELD compensation in notionally any loop filter topology, with the use of (much) simpler hardware than an extra DAC and an associated summing amplifier. For instance, one or embodiments may involve using a pair of capacitances and four switches.

[0070] By way of introduction to a detailed description of exemplary embodiments, one may note that ELD compensation schemes as discussed previously are based on a proper tuning of loop coefficients and on the introduction of a term whose value is not null (non-zero) only when the DAC output is not null (non-zero).

[0071] That situation, related to the circuit diagram of FIG. 12 (once more, parts or elements already discussed are indicated with like reference symbols, unless the context indicates otherwise, and are not described again for brevity) is pictured in the diagrams of FIG. 12A, where (by referring to the exemplary case of τ=0.25) behaviors over time t are portrayed for y.sub.3(t) (chain line), y.sub.2(t) (dashed line) and y.sub.3(t)−y.sub.2(t) (continuous line), with sampled values at the sampling period T.sub.S again highlighted by dots.

[0072] A corresponding compensation approach is exemplified by an ELD compensation network 120 represented in connection with both a multi-feedback architecture (FIG. 13A, which basically corresponds to FIGS. 2 and 3) and a single-feedback architecture (FIG. 13B, which basically corresponds to FIG. 11).

[0073] In both instances, parts or elements already discussed in connection with the previous figures are indicated with like reference symbols, unless the context indicates otherwise, and are not described again for brevity.

[0074] By way of recap, in FIG. 13A: [0075] V.sub.IN=(analog) input signal; [0076] y.sub.1(t) =output from the first integrator (l/s) 201 supplied with the addition, obtained at the first adder node 301, of the input signal V.sub.IN and a feedback term from D.sub.OUT (affected by ELD as modelled by z.sup.−r) obtained via the DAC D/A.sub.2 multiplied by a coefficient k.sub.2C (for simplicity, this can be assumed to be included in the DAC); as discussed previously, the node 301 can be an adder node “with sign”, where the feedback term obtained via the DAC D/A.sub.2 weighed by k.sub.2C is in fact subtracted from the input signal V.sub.IN as conventional in a delta-sigma modulator; [0077] y.sub.2(t)=output from the second integrator (l/s) 202 supplied with the addition, obtained at the second adder node 302 (possibly with sign), of the output y.sub.1(t) from the first integrator 201 and a feedback term D.sub.OUT (again affected by ELD as modelled by z.sup.−r) obtained via the DAC D/A.sub.1 multiplied by a coefficient k.sub.1C (again for simplicity, this can be assumed to be included in the DAC); [0078] Y.sub.C[n]=modulator output D.sub.OUT as obtained by sampling with a sampling period T.sub.S a signal y.sub.4(t) obtained by adding, at the adder node 303 (possibly with sign) at the output of the second integrator 202, the output y.sub.2(t) from the second integrator 202 and an ELD compensation term y.sub.3(t) provided by the ELD compensation network 120 as discussed in the following.

[0079] Similarly, in FIG. 13B: [0080] V.sub.IN=(analog) input signal; [0081] y.sub.1(t)=output from the first integrator (l/s) 201 supplied with the addition, obtained at the first adder node 301 (possibly with sign), of the input signal V.sub.IN and a feedback term (affected by ELD as modeled by z.sup.−r) obtained from D.sub.OUT via a (single, in this case) DAC D/A multiplied by a coefficient k.sub.2 (also in this case, the coefficient can be assumed to be included in the DAC); [0082] y.sub.2(t)=signal obtained at a second (feedforward) adder node 302′ (possibly with sign) supplied with the output from the second integrator (l/s) 202 and the output y.sub.1(t) from the first integrator 201 weighed by a term k.sub.FF(via a respective weighing circuit of any known type); [0083] Y.sub.C[n]=modulator output obtained by sampling with a sampling period T.sub.S a signal y.sub.4(t) obtained by adding, at the adder node 303 (possibly with sign) coupled at the output of the second integrator 202 with the node 302′ set there between, the output y.sub.2(t) from the second adder node 302′ and an ELD compensation term y.sub.3(t) provided by the ELD compensation network 120 as discussed in the following.

[0084] In one or more embodiments, the ELD compensation network 120 can include (in both instances of FIG. 13A and FIG. 13B): [0085] a derivative stage (s) 1202 supplied with the output y.sub.1(t) from the first integrator 201 weighed by a coefficient k.sub.0C (again, for simplicity, this can be assumed to be included in stage 1202); [0086] a switch set 1204 (for instance, solid-state switches such as mosfet transistors) including two complementary switches ϕ.sub.C(neg)—that is negated−ϕ.sub.C—and ϕ.sub.C.

[0087] These switches being designated complementary indicates that the one is conductive when the other is non-conductive and vice-versa; [0088] a pair of “sign” stages 1206a and 1206b labelled “+” and “−”; and [0089] a third integrator (l/s) 1208, which supplies the adder node 303 with a signal y.sub.3(t) resulting from integrating the signal received from 1202 with different signs according to whether the output from 1202 is applied to the integrator input with the sign “+” (non-inverted at 1206a) or “−” (inverted at 1206b) as a function of the switching state of the “sign” stages 1206a and 1206b labelled “+” and “−” set between the switches ϕ.sub.C(neg), ϕ.sub.C, and the integrator 1208.

[0090] As discussed, the signal y.sub.3(t) is intended to be added at 303 with y.sub.2(t) in order to provide the signal y.sub.4(t) which—once sampled at the sampling period T.sub.S—yields the output Y.sub.C[n].

[0091] As illustrated in FIGS. 13A and 13B, the switch arrangement 1204 can be operated under the control of a signal SW generated by a clock circuit CLK (of any type known to those of skill in the art). The circuit CLK can be a distinct element from the embodiments and can also be configured to provide the quantizer A/D with the sampling signal at the sampling period T.sub.S to yield the output Yc[n].

[0092] The diagrams of FIGS. 14A to 14E share a common time scale t (abscissa scale) and are exemplary of waveforms of signals which may occur in architectures as exemplified herein in the presence of a sampling signal at a period T.sub.S (FIG. 14A) with ϕ.sub.C(t) being a rectangular waveform having the same period T.sub.S and 50% duty cycle.

[0093] An exemplary waveform for ϕ.sub.C(t) is shown in FIG. 14B: the time behavior of the complementary signal ϕ.sub.C(neg), which is “low” when ϕ.sub.C(t) is “high” and “high” when ϕ.sub.C(t) is “low” is not expressly depicted for simplicity.

[0094] Again, an exemplary case of r=0.25 (with T.sub.S=1, in second units, for instance) can be referred to—with no limiting effect—in order to facilitate comparison with the previous discussion of conventional solutions.

[0095] As discussed previously (see for instance FIG. 5), due to the action of ELD, an impulse on the circuit input will result in delayed integrator input (see FIG. 14C) which, in the case of the first integrator 201 will result in y.sub.1(t) ramping up to k.sub.2C (reference may be had first to the architecture of FIG. 13A for simplicity) as a ramp delayed by τ (see the exemplary diagram of FIG. 14D).

[0096] In the compensation network 120 this ramp is multiplied for a coefficient k.sub.0C, then derived in the derivative stage (s) 1202 and integrated with a sign that depends on the “phase” represented by ϕ.sub.C(t), whose period is given by T.sub.S, which is synchronous with the quantizer sample phase and not afflicted by ELD.

[0097] The resulting waveform at the sampling instants with period T.sub.S, designated y.sub.2C(nT.sub.S)—see FIG. 14E, reaches a value whose value can be expresses as:

[00001]$\begin{array}{cc}{y}_{2C}\left({\mathrm{nT}}_S\right)=\left\{\begin{array}{cc}0& n=0\\ k_{0C}{k}_{2C}\tau & n=1\\ 0& n\ge 2\end{array}\right\}& \left(2\right)\end{array}$

[0098] The contribution of this compensation network to the output signal to the quantizer A/D (see y.sub.3(t) in the exemplary diagram of FIG. 14E) has the same behavior of a signal from a direct-feedback loop proposed in conventional ELD compensation as described previously (see FIGS. 7 and 12, for instance) and is non null (non-zero) only at the first sampling instant.

[0099] The complete impulse response of such compensated modulator and the different compensation contributions are shown in the diagram of FIG. 15, where behaviors over time t are portrayed for y.sub.4(t) (chain line), y.sub.2(t) (dashed line) and y.sub.3(t) (continuous line), with sample values at a period T.sub.S again highlighted by dots.

[0100] It will be appreciated that the previous discussion also extends to the architecture of FIG. 13B, which can be regarded as a sort of simplified version of the architecture of FIG. 13A where the feedback loop through D/A, with the coefficient k.sub.1C is removed and system stability is achieved introducing the feedforward path, from the output of the first integrator 201 to the summing node 303, weighed for the coefficient k.sub.FF.

[0101] The block diagrams of FIGS. 13A and 13B can be modified (simplified) as illustrated in FIGS. 16A and 16B, where same integrator circuit (that is a same component) can be used as the second integrator 202 of the loop filter and as integrator 1208 of the ELD compensation network 120.

[0102] In fact: [0103] in FIG. 13A, the signals from the node 302 and from the “sign reversal” arrangement 1204, 1206a, 1206b in the ELD compensation network 120 are distinctly applied to the integrators 202 and 1208 and then added at the node 303; in FIG. 16A, the signal from the “sign reversal” arrangement 1204, 1206a, 1206b in the ELD compensation network 120 is merely added to the combination (as provided at the node 302) of the signal y.sub.1(t) from the first integrator 201 and the feedback signal from D/A, weighed by k.sub.1C, with the three signals thus combined at 302 supplied to the integrator 202 (acting as a “common” loop/compensation integrator) thus dispensing with one integrator circuit and the adder node 303 at the output of the integrator 202 as shown in FIG. 13A; and [0104] in FIG. 13B, the signals from the first integrator 201 and from the “sign reversal” arrangement 1204, 1206a, 1206b in the ELD compensation network 120 are again distinctly applied to the integrators 202 and 1208 and then added at the node 303 together with the feedforward term K.sub.FF*y.sub.1(t) added at 302″ to the output from the first integrator 201; in FIG. 16B, the signals from the first integrator 201 and from the “sign reversal” arrangement 1204, 1206a, 1206b in the ELD compensation network 120 are merely added 302 with the two signals thus combined supplied to the integrator 202 (again acting as a “common” loop/compensation integrator) while the feedforward term K.sub.FF*y.sub.1(t) is added at the adder node 303 at the output of the integrator 202, thus again dispensing with one integrator circuit in comparison with FIG. 13B.

[0105] The block-scheme description of one or more embodiments as discussed in the foregoing lends itself to a fairly simple implementation in a fully differential architecture.

[0106] For instance, the block diagram of FIG. 17 is exemplary of a possible practical implementation of a second order CTDSM along the lines of FIG. 2 (that is, with no ELD compensation provided).

[0107] While the (otherwise conventional) architecture of the DAC elements D/A, and D/A.sub.2 is not detailed for simplicity in FIG. 17, an exemplary active-RC (fully differential) topology is exemplified for the continuous-time integrators 201, 202 generating y.sub.1(t) and y.sub.2(t) and the associated adder nodes 301, 302. The (digital) output signal D.sub.OUT is exemplified as derived at the output of a quantizer A/D controlled by a sampling signal of period T.sub.S (see the rightmost portion of FIGS. 13A and 13B for immediate reference).

[0108] As exemplified in FIG. 17, a differential topology for the continuous-time integrators 201, 202 may comprise two fully differential amplifiers 1021, 1022 (of any type known to those of skill in the art, OpAmps, for instance) with respective RC feedback loops R.sub.INT.sub.1, C.sub.INT.sub.1 and R.sub.INT.sub.2, C.sub.INT.sub.2. As exemplified in FIG. 17, the feedback inputs from D/A.sub.1 and D/A.sub.2 can be implemented as differential inputs to the (likewise differential) input ports to the fully differential amplifiers 1021, 1022.

[0109] As exemplified in FIG. 18, a compensation network 120 as discussed in the foregoing can be associated with a fully differential amplifier 1022 included in a circuit layout as exemplified in FIG. 17.

[0110] In one or more embodiments, this may include coupling two capacitances C.sub.0 intermediate: [0111] the terminals of the resistors R.sub.INT.sub.2 which receive therebetween the (differential) output y.sub.1(t) from the first integrator 201 (fully differential amplifier 1021 in FIG. 17); and [0112] the virtual ground of the second integrator 202 (fully differential amplifier 1022 in FIG. 17), namely the intermediate nodes GND1, GND2 between R.sub.INT.sub.2 and C.sub.INT.sub.2 which receive applied therebetween the (differential) feedback signal from the DAC D/A,.

[0113] Coupling of the two capacitances C.sub.0 to the virtual ground GND1, GND2 of the second integrator 202 can be through four switches whose state depends on the “phase” signal ϕ.sub.C with these switches (solid-state switches such a mosfet transistors, for instance) configured to couple the two capacitances C.sub.0 to the virtual ground of the second integrator 202 in a “crossed” arrangement.

[0114] In that way, four switches labeled ϕ.sub.C and ϕ.sub.C(neg) can implement the functions exemplified as 1204 and 1206a, 1206b in FIG. 16A, that is: [0115] with ϕ.sub.C(neg) “low” and ϕ.sub.C “high”, the signal y.sub.1(t) is applied with the same polarity (with no sign reversal: see 1206a in FIG. 16A) between the intermediate nodes between R.sub.INT.sub.2 and C.sub.INT.sub.2; and [0116] with ϕ.sub.C(neg) “high” and ϕ.sub.C “low”, the signal y.sub.1(t) is applied with reversed polarity (with sign reversal: see 1206b in FIG. 16A) between the intermediate nodes between R.sub.INT.sub.2 and C.sub.INT.sub.2.

[0117] It is noted that the current flowing through the capacitances C.sub.0 is a function of (equal to, for instance) the first derivative of the output signal y.sub.1(t) from the first integrator 201 multiplied by the capacitance value.

[0118] In that way, a circuit arrangement as exemplified in FIG. 18 can also provide the derivative stage 1202.

[0119] This current is injected in the virtual ground of the second integrator 202 with a sign that depends on the “phase” signal ϕ.sub.C (which can be derived from CLK together with the sampling signal of period T.sub.S in a manner known to those of skill in the art) and integrated using the second integrator feedback capacitances C.sub.INT.sub.2.

[0120] The resulting coefficient k.sub.0.sub.C can be expressed as:

k.sub.0C=C.sub.0/C.sub.INT2.

[0121] It will be appreciated that, while discussed for simplicity in connection with the block diagram of FIG. 16A, the implementation exemplified in FIG. 18 is suited to be also applied, for instance, to the block diagram of FIG. 16B, where the DAC D/A1 has been removed and the feedforward path K.sub.FF can be implemented using known techniques to those skilled in the art.

[0122] As discussed, one or more embodiments as exemplified herein in connection with a second-order layout (two integrators 201, 202) can be applied also to higher order (higher-than-two) modulators introducing a compensation network 120 as exemplified herein between: [0123] the first integrator (that is, the integrator—here the integrator 201—coupled to the input node V.sub.IN); and [0124] the virtual ground of the last (the n-th in a n-th order scheme) integrator before the quantizer A/D (that is, the integrator—here the integrator 202—providing the signal to be sampled with period T.sub.S), the contribution to the impulse response being also in that case the same presented here for a 2-nd order modulator.

[0125] A circuit (for instance, 10) as exemplified herein may comprise: [0126] an input node (for instance, V.sub.IN) configured to receive an analog input signal; [0127] a quantizer circuit (for instance, A/D) having an output node (for instance, D.sub.OUT), the quantizer circuit operable at a certain sampling period (for instance, T.sub.S) to provide at said output node a digital signal resulting from analog-to-digital conversion of the analog input signal at said input node; [0128] a first integrator circuit (for instance, 201) in a signal propagation path (201, 302, 202, 303-FIG. 13A; 201, 202, 302″, 303-FIG. 13B; 201, 302, 202-FIG. 16A; 201, 302, 202, 303 FIG. 16B) from the input node to the quantizer circuit, the first integrator circuit (201) having an input (for instance, 301) coupled to the input node to receive said analog input signal therefrom; [0129] a feedback network (for instance, D/A.sub.1, D/A.sub.2, D/A) sensitive to the digital signal at said output node, the feedback network comprising at least one digital-to-analog converter (for instance, D/A.sub.2 FIGS. 13A and 16A; D/A FIGS. 13B and 16B) configured to inject into the input of the first integrator circuit (201) a weighed (for instance, k.sub.2C; k.sub.2) analog-converted replica of said digital output signal, wherein said first integrator circuit propagates over said signal propagation path towards the quantizer circuit an integrated signal (for instance, y.sub.1(t)) which is a function of said analog input signal and said weighed analog-converted replica of said digital output signal; [0130] an excess delay loop (for instance, z.sup.−r) compensation network (for instance, 120) comprising a derivative circuit (for instance, 1202, possibly comprising capacitances C.sub.0 as exemplified in FIG. 18) configured to receive a weighed (for instance, k.sub.0C) replica of said integrated signal from the first integrator circuit and produce therefrom a derivative signal as well as a sign-reversal circuit (for instance, 1204, 1206a, 1206b, possibly comprising switches ϕ.sub.C, ϕ.sub.C(neg)) configured to alternately reverse the sign of said derivative signal over subsequent time intervals of a duration half (for instance, T.sub.S/2) said certain sampling period (see, for instance, FIG. 14B, showing sign being “+” for T.sub.S/2, then “−” for T.sub.S/2, then again “+” for T.sub.S/2, “−” for T.sub.s/2, “+” for T.sub.S/2 and so on); [0131] at least one further integrator circuit (for instance: 1208 in FIGS. 13A and 13B; 202 in FIGS. 16A and 16B) configured to integrate said derivative signal having the sign thereof alternately reversed over said subsequent time intervals of a duration half said certain sampling period, [0132] an excess delay loop compensation node (for instance: 303 in FIGS. 13A and 13B; 302 in FIGS. 16A and 16B) configured to inject into said signal propagation path towards the quantizer circuit (A/D) an excess delay loop compensation signal, wherein: [0133] i) (as exemplified in FIGS. 13A and 13B) said excess delay loop compensation node (for instance, 303) is arranged at an output of said at least one further integrator circuit (for instance, 1208) and is configured to inject into said signal propagation path towards the quantizer circuit said derivative signal having the sign thereof alternately reversed over said subsequent time intervals of a duration half said certain sampling period after integration of said derivative signal at said at least one further integrator circuit (for instance, 1208), or [0134] ii) (as exemplified in FIGS. 16A and 16B) said excess delay loop compensation node (for instance, 302) is arranged at an input of said at least one further integrator circuit (for instance, 202) and is configured to inject into said signal propagation path towards the quantizer circuit said derivative signal having the sign thereof alternately reversed over said subsequent time intervals of a duration half said certain sampling period before integration of said derivative signal at said at least one further integrator circuit (for instance, 202).

[0135] As discussed previously, in one or more embodiments, the at least one further integrator circuit as exemplified here by 202 may be the n-th integrator circuit in a cascaded arrangement of n integrator circuits in a n-th order loop.

[0136] A circuit as exemplified herein (see FIGS. 13A and 13B) may comprise: [0137] a first further integrator circuit (for instance, 1208) arranged intermediate said sign-reversal circuit (for instance, 1204, 1206a, 1206b, ϕ.sub.C, ϕ.sub.C(neg)) and said excess delay loop compensation node (for instance, 303); and [0138] a second further integrator circuit (for instance, 202) arranged intermediate said first integrator circuit and said excess delay loop compensation node (for instance, 303), [0139] wherein said derivative signal having the sign thereof alternately reversed over said subsequent time intervals of a duration half said certain sampling period is injected after integration at said first further integrator circuit (for instance, 1208) into said signal propagation path towards the quantizer circuit downstream of said second further integrator circuit (for instance, 202).

[0140] In a circuit as exemplified herein (see FIG. 13A) said feedback network sensitive to the digital signal at said output node may comprises at least one further digital-to-analog converter (for instance, D/A.sub.1) configured to inject into said signal propagation path towards the quantizer circuit intermediate said first integrator circuit (for instance, 201) and said second further integrator circuit (for instance, 202) at least one further weighed (for instance, k.sub.1C) analog-converted replica of said digital output signal.

[0141] A circuit as exemplified herein (see FIG. 13B) may comprise a feedforward signal path (for instance, k.sub.FF) coupled to said first integrator circuit to receive therefrom said integrated signal, the feedforward signal path configured to inject (for instance, 302″) a weighed replica of said integrated signal into said signal propagation path towards the quantizer circuit intermediate said second further integrator circuit (for instance, 202) and said quantizer circuit.

[0142] A circuit as exemplified herein (see FIGS. 16A and 16B) may comprise said at least one further integrator circuit (for instance, 202) arranged intermediate said excess delay loop compensation node (for instance, 302) and said quantizer circuit wherein said derivative signal having the sign thereof alternately reversed over said subsequent time intervals of a duration half said certain sampling period is injected into said signal propagation path towards the quantizer circuit upstream of said at least one further integrator circuit (for instance, 202).

[0143] In a circuit as exemplified herein (see FIG. 16A), said feedback network sensitive to the digital signal at said output node may comprises at least one further digital-to-analog converter (for instance, D/A.sub.1) configured to inject into said signal propagation path towards the quantizer circuit intermediate said first integrator circuit (for instance, 201) and said at least one further integrator circuit (for instance, 202) at least one further weighed (for instance, k.sub.1C) analog-converted replica of said digital output signal.

[0144] A circuit as exemplified herein (see FIG. 16B) may comprise a feedforward signal path (for instance, k.sub.FF) coupled to said first integrator circuit to receive therefrom said integrated signal, the feedforward signal path configured to inject (for instance, 303) a weighed replica of said integrated signal into said signal propagation path towards the quantizer circuit intermediate said at least one further integrator circuit (for instance, 202) and said quantizer circuit.

[0145] In a circuit as exemplified herein, said first integrator circuit may comprise a fully differential amplifier (for instance, 1021 in FIG. 17) having differential input node terminals (for instance, 301, R.sub.INT1) and differential output node terminals (for instance, to provide y.sub.1(t) therebetween) with RC feedback networks (for instance, R.sub.INT1, C.sub.INT1) from said differential output node terminals to said differential input node terminals.

[0146] In a circuit as exemplified herein (see FIG. 18) said at least one further integrator circuit (for instance, 202, but might be also 1208) may comprise a fully differential amplifier (for instance, 1022) having differential input node terminals (for instance, R.sub.INT2) and differential input node terminals (for instance, to provide y.sub.2(t) therebetween) with RC feedback networks (for instance, R.sub.INT2, C.sub.INT2) from said differential output node terminals to said differential input node terminals, wherein said RC feedback networks provide virtual ground nodes (for instance, GND1, GND2) of said further integrator circuit, [0147] said differential output node terminals of said first integrator circuit (for instance, 201) are coupled to said virtual ground nodes in said further integrator circuit via respective capacitances (for instance, C.sub.0) providing said derivative circuit and via sign-reversal circuitry (for instance, ϕ.sub.C, ϕ.sub.C(neg)) configured to alternately reverse over subsequent time intervals of a duration half said certain sampling period the polarity of coupling said respective capacitances to said virtual ground nodes in said at least one further integrator circuit, that is with: [0148] the first capacitance C.sub.0 in the pair coupled to GN1 for T.sub.S/2, then to GN2 for T.sub.S/2, then again to GN1 for T.sub.S/2, to GN2 for T.sub.S/2, and so on, and, in a complementary way; and [0149] the second capacitance Coin the pair coupled to GN2 for T.sub.S/2, then to GN1 for T.sub.S/2, then again to GN2 for T.sub.S/2, to GN1 for T.sub.S/2, and so on).

[0150] A delta-sigma modulator device as exemplified herein may comprise a circuit as exemplified herein, the delta-sigma modulator device configured to receive an continuous analog input signal at said input node and to provide at said output node a delta-sigma modulated digital signal resulting from delta-sigma analog-to-digital conversion of the analog input signal at said input node.

[0151] As exemplified herein a method of providing at an output node a digital signal resulting from analog-to-digital conversion of an analog input signal supplied to an input node may comprise: [0152] supplying said analog input signal to said input node; [0153] providing said digital signal to said output node via a quantizer circuit operated at a certain sampling period; [0154] providing a signal propagation path from the input node to the quantizer circuit said signal propagation path comprising a first integrator circuit having an input coupled to the input node to receive said analog input signal therefrom; [0155] providing a feedback network sensitive to the digital signal at said output node, the feedback network comprising at least one digital-to-analog converter configured to inject into the input of the first integrator circuit a weighed analog-converted replica of said digital output signal, wherein said first integrator circuit propagates over said signal propagation path towards the quantizer circuit an integrated signal which is a function of said analog input signal and said weighed analog-converted replica of said digital output signal; [0156] receiving said integrated signal from said at least one integrator circuit at a derivative circuit configured to produce therefrom a derivative signal and alternately reversing the sign of said derivative signal over subsequent time intervals of a duration half said certain sampling period; [0157] providing at least one further integrator circuit configured to integrate said derivative signal having the sign thereof alternately reversed over said subsequent time intervals of a duration half said certain sampling period; injecting into said signal propagation path towards the quantizer circuit an excess delay loop (z.sup.−r) compensation signal, wherein said injecting comprises: [0158] i) as exemplified in FIGS. 13A and 13B—injecting into said signal propagation path towards the quantizer circuit said derivative signal having the sign thereof alternately reversed over said subsequent time intervals of a duration half said certain sampling period after integration of said derivative signal at said at least one further integrator circuit; or [0159] ii) as exemplified in FIGS. 16A and 16B—injecting into said signal propagation path towards the quantizer circuit said derivative signal having the sign thereof alternately reversed over said subsequent time intervals of a duration half said certain sampling period before integration of said derivative signal at said at least one further integrator circuit.

[0160] The details and embodiments may vary with respect to what has been disclosed herein merely by way of example without departing from the extent of protection.

[0161] The extent of protection is determined by the annexed claims.

[0162] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments.

[0163] These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.