SINGLE SUBSTRATE MULTIPLEXER

Abstract

At least three acoustic filters circuits FC are arranged on a single chip CH. At least two of them are electrically connected already on the chip for multiplexing. This reduces space consumption and leads to smaller device size.

Claims

1. A multiplexer, comprising a monolithic stack (ST) of: a carrier substrate (SU); a piezoelectric layer (PL) above the substrate having a main surface; and at least one dielectric layer (DL) arranged between piezoelectric layer and substrate; a metallization on top of the main surface comprising: an antenna terminal (AT) for connection with an antenna; three signal pads (SP); and three SAW filter circuits (FC) connected in parallel between the antenna terminal and a respective signal pad each, wherein each of the filter circuits comprises series signal line (SSL) and a number of SAW resonators (RP,RS) connected in series with or parallel to the series signal line; and a package providing a cavity on top of the stack, wherein the SAW resonators are enclosed in the cavity that is formed between the main surface of the piezoelectric layer and a lid and/or a cover.

2. The multiplexer of claim 1, wherein the carrier substrate comprises Si, wherein the piezoelectric layer is a monocrystalline thin film layer of lithium tantalate or lithium niobate having a thickness of 400 nm to 2000 nm.

3. The multiplexer of claim 1, wherein the dielectric layer is a silicon oxide layer having a thickness of 300 nm to 2000 nm and a smooth top surface.

4. The multiplexer of claim 1, wherein a trap-rich layer (TRL) is provided between substrate and piezoelectric layer, the trap-rich layer comprising a polycrystalline silicon layer having a thickness of 300 nm to 2000 nm.

5. The multiplexer of claim 1, wherein the substrate has a thermal conductivity that is at least ten times larger than the thermal conductivity of the piezoelectric layer.

6. The multiplexer of claim 1, comprising a multilayer board (MLB) having contact pads (CP) on a bottom surface thereof and an integrated wiring, connecting the contact pads with respective external contacts (EC) on the top surface opposite to the bottom surface, wherein the multilayer board is mounted to the stack (ST) by a connection technique to electrically connect the contact pads with respective signal pads (SP) and the antenna terminal (AT), wherein the connection comprises bumps (BU), wherein a sealing means is provided to seal the cavity formed between multilayer board and the main surface.

7. The multiplexer of claim 1, wherein the multilayer board is selected from the group consisting of multilayer laminate, HTCC and LTCC.

8. The multiplexer of claim 1, wherein the SAW resonators are enclosed in a cavity integrally formed as a thin film acoustic package.

9. The multiplexer of claim 1, wherein four SAW filter circuits (FC) are provided to form a quadplexer comprising two duplexers, wherein the two duplexers are configured to operate in bands B1 and B3, or in bands B25 and B66.

10. The multiplexer of claim 1, comprising a trimming layer on top of the stack wherein one or more layers of the stack are trimmed to meet the specifications of band B3 or B25.

11. The multiplexer of claim 1, comprising a filter circuit that is an Rx filter having a DMS filter in the series signal line.

Description

[0034] The invention will be explained in more detail by reference to embodiments and accompanied drawings. The drawings are schematic only and may not be drawn to scale.

[0035] FIG. 1 shows a known multiplexer arrangement of four separate chips on a common multilayer board with necessary chip to chip distances and edge margin

[0036] FIG. 2 shows a one-chip multiplexer and the necessary edge margin according to the invention

[0037] FIG. 3 shows a schematic block diagram of four filter circuits that are arranged on a single chip and connected to a common antenna terminal

[0038] FIG. 4 shows a schematic filter circuit in more detail

[0039] FIG. 5 shows a schematic block diagram of a DMS filter that can be used as a resonator in an Rx filter circuit

[0040] FIG. 6 shows a cross section through a monolithic stack provided with a structured metallization comprising pads, electrode structures and terminals that can be used for the multiplexer

[0041] FIG. 7 shows a possible schematic package for the multiplexer.

[0042] FIG. 1 shows an arrangement of four separate chips CH on a common multilayer board MLB with necessary chip to chip distances and edge margins. Due to these necessary distances the acoustically usable area AA of a chip CH is smaller than the area of the chip. Further, the chips must keep a distance to the edge of multilayer board and between neighboring chips.

[0043] FIG. 2 shows in the same scaling the necessary area of a multiplexer realized on a single chip according to the invention. In such an arrangement no chip to chip distance is necessary and the margin of the single chip requires smaller chip area with respect to the arrangement of FIG. 1. Same is true for the margin of the multilayer board MLB. Hence, up to 50% and more wafer area may be saved and a multiplexer device can be achieved having a size that is accordingly smaller than that of a known multichip assembly according to FIG. 1.

[0044] FIG. 3 shows an exemplary schematic block diagram of four filter circuits FC1 to FC4 that are arranged on a single chip CH and connected to a common antenna terminal AT. Each of the filter circuits FC comprises a series signal line SSL connecting each respective signal pad SP to the antenna terminal AT and a number of SAW resonators. Series resonators RS are connected in series and parallel resonators RP are connected parallel to the series signal line SSL.

[0045] The filter circuits are ladder type arrangements and may comprise further elements that are not shown in the figure for clarity reasons. The number of resonators may be higher to achieve a better selectivity. Some of the resonators may be cascaded for improving the power resistance thereof and to improve the life time and to reduce nonlinear behavior. The filter circuit may consist of series resonators RS only. Passive elements may be connected to resonators or to the series signal line. Capacitors may be circuited in parallel to single resonators to vary the bandwidth thereof. Parallel resonators RP may be connected to ground via an inductance. Some of the ground connections may be combined on the chip. The antenna terminal is connected to ground via a coil for phase shifting and impedance matching. External matching elements may be connected to signal pads or to the series signal line.

[0046] Two filter circuits may be assigned to the same first cellular band and form an Rx filter and a respective Tx filter of that band. The other two filter circuits may be assigned to a second cellular band to allow duplex operation in this second band. Preferably the filter circuits are assigned to band combinations having a not too high frequency distance.

[0047] Preferably the two bands are within the same frequency range selected from high band range and/or mid band range.

[0048] FIG. 4 shows a schematic exemplary filter circuit FC like those depicted in FIG. 3 in more detail. This filter circuit comprises five series resonators RS arranged in the series signal line SSL. Respective nodes between each two neighbored series resonators are connected to ground via a parallel branch and a parallel resonator RP is arranged in every parallel branch. An inductance (not shown) may be circuited between a parallel resonator and ground.

[0049] FIG. 5 shows a schematic block diagram of an exemplary DMS filter that can be used as a series resonator in an Rx filter circuit of the multiplexer. A DMS filter comprises a first number of interdigital transducers/resonators IDTs that are connected to the input terminal IN of the DMS filter. A second number of interdigital transducers IDTs are connected to the output terminal OUT of the DMS filter. All IDTs are arranged in an acoustic track extending between two reflectors REF and are hence acoustically coupled. First and second number may be set higher than depicted according to a required selectivity specification. The bus bars of the IDTs that are not connected to input or output may be connected to ground or floating. Two DMS filters may be circuited in series within a filter circuit. Other elements of the filter circuit as shown in FIGS. 3 and 4 complete the filter circuit.

[0050] FIG. 6 shows a schematic cross section through a monolithic stack that is already provided with a structured metallization on top. From the metallization, pads, electrode structures ES like interdigital transducers, reflectors, conductor lines, terminals AT and signal pads SP1, SP2 may be formed as required for forming the multiplexer of FIG. 3 for example.

[0051] The carrier substrate SU is a crystalline silicon material of a thickness sufficient to provide required mechanical stability. The stability must be high enough to allow handling of a whole wafer on which the stack ST is formed. The crystalline silicon material of the carrier substrate SU may have a top surface that is a crystallographic [111] surface.

[0052] Optionally a trap-rich layer TRL is arranged on top of the carrier substrate SU consisting e.g. of a polycrystalline silicon layer with a thickness in the range of 100 nm to 2000 nm to eliminate e.g. the known free charges at a later Si/SiO2 junction. A dielectric layer DL of SiO2 is formed or deposited to act as a TCF compensating layer. Thickness of the dielectric layer is controlled and set to a value of about 300 nm to 2000 nm, e.g. to 500 nm. All layer junctions can have smooth top and bottom surfaces with small layer roughness.

[0053] After smoothing the surface of the dielectric layer DL e.g. by a CMP method a piezoelectric wafer is bonded to the dielectric layer DL. After atomic bonding the thickness of the piezoelectric wafer is reduced to form a thin film piezoelectric layer PL having a thickness of about 400 nm to 2000 nm, e.g. of 600 nm. This is thin enough to allow fast heat dissipation from the filter circuit to the substrate below and to avoid excitement of spurious mode in counter bands or another band that can be operated by the multiplexer. With a sufficiently thin piezoelectric layer spurious modes occur only at frequencies high above the bands used by the multiplexer.

[0054] After thickness reduction by an appropriate process the thickness of the piezoelectric layer is measured and the whole layer is trimmed to achieve a desired thickness all over the whole wafer with only a small tolerance. This is necessary as the frequency of a filter circuit formed on the piezoelectric layer may depend on the specific thickness thereof and a too high tolerance results in a frequency variation and a frequency distribution over the wafer dependent on remaining thickness variation.

[0055] Lithium tantalate LT and lithium niobate LN are preferred piezoelectric materials. But other materials may be used, too.

[0056] It is important that the thermal conductivity of substrate SU is at least ten times higher than the respective conductivity of the piezoelectric layer PL. The above proposed silicon substrate SU and piezoelectric layer PL of LT are different in conductivity by a factor of about 40.

[0057] The top surface of the stack ST is the main surface on which electrode structures ES and signal pads SP as well as the antenna terminal AT are formed. FIG. 6 shows the metallization in a very schematic depiction. Further pads like ground pads for connecting the parallel branches to ground are present on the main surface but not shown in the schematic figure.

[0058] Preferably the electrode structures are formed from a metallization based on Al or an Al alloy. Further, Cu and/or Ti may be further components in the alloy or may be used as a discrete sub-layer of a multilayer metallization. The surface of the metallization may be protected with a passivation layer. The pads are thickened and provided with a solderable surface layer like Au or Ni for example.

[0059] To complete the multiplexer a package is formed on top of the stack ST. For this reason a multilayer board may be bonded to the main surface of the stack.

[0060] FIG. 7 shows a cross section of such a multiplexer that is already provided with such a covering board.

[0061] The multilayer board MLB may be of any material like an organic laminate like FR4, or formed form a ceramic material like LTCC and HTCC. Ceramic is preferred due to its higher thermal conductivity and due to its thermal expansion that is matched to that of the Si carrier. LTCC is preferred choice for the multilayer board MLB.

[0062] Within the multilayer board a wiring is integrated comprising through-contacts through one or more of the ceramic or laminate layers and wiring planes. The through contacts connect different wiring planes arranged between two such ceramic or laminate layers or a wiring plane with a contact pad CP on the bottom surface or with an external contact EC on the top surface. The wiring serves to interconnect and circuit different signal pads and/or terminals and to provide a connection between the signal pads, the antenna terminal and external contacts EC arranged on top of the multilayer board MLB.

[0063] Further, the multilayer board may comprise integrated passives that can be formed from such an integrated wiring. These passives may support the filter functions of the filter circuits. Such integrated passives may be used to form a coil connected to the antenna terminal and inductances in series with parallel branches. Passives that require a higher quality factor like those used to match the terminals of a filter circuit have to be realized as external discrete elements that may be connected to the external contacts.

[0064] The mounting of the stack ST to the multilayer board MLB can be done on wafer level. In a last step single devices can then be separated by dicing the wafer level package e.g. by sawing.

[0065] Alternatively a large area multilayer board can be used to mount thereon single stacks that have already been singulated before.

[0066] Bumps BU are preferred to connect the multilayer board to the respective pads SP and terminals AT on the main surface of the stack ST. In order to promote heat dissipation from the filter circuit and the respective active piezoelectric layer to the multilayer board a maximum number of bumps is preferred.

[0067] In the example of FIG. 3 at least thirteen pads and terminals need to be contacted by a separate bump each. A higher number of parallel branches allows to perform the mounting with a higher number of bumps. Also bumps without any electric functionality might be used to provide better heat dissipation.

[0068] In the package the areas of stack and multilayer board may comply. However it may be advantageous if a margin of stack or board extends over the edge of the other package layer. Then a sealing layer may be applied from the side of the layer or stack having the smaller area. The sealing layer can then seal the protruding surface in the margin area more easily.

[0069] The sealing can be done with a resin, a laminate or a foil; and a hermetic sealing can be achieved with a metal layer as a top sealing layer. The sealing layer need to be structured to expose at least the external contacts EC of the package.

[0070] As the invention has been described with reference to some embodiments only the invention shall not be limited to any specific embodiment or figure. Features that are specified in more detail in written form or in a figure with reference to an embodiment only shall not be limited to this details as far as the respective feature is disclosed in a more general form and is covered by the claims.

LIST OF USED TERMS AND REFERENCE SYMBOLS

[0071] cavity

[0072] metallization

[0073] package

[0074] Rx filter

[0075] Tx filter

[0076] AA acoustically usable area

[0077] AT antenna terminal

[0078] BU bump

[0079] CH chip

[0080] CP contact pad

[0081] DL dielectric layer

[0082] EC external contact

[0083] ES electrode structure

[0084] FC SAW filter circuit

[0085] IDT interdigital transducer

[0086] IN input terminal of DMS filter

[0087] MLB multilayer board

[0088] OUT output terminal of DMS filter

[0089] PL piezoelectric layer

[0090] REF reflector

[0091] RS,RP series and parallel SAW resonators

[0092] SP signal pads

[0093] SSL series signal line

[0094] ST monolithic stack

[0095] SU carrier substrate

[0096] TRL trap-rich layer