METHOD FOR MANUFACTURING A POLYSILICON SOI SUBSTRATE INCLUDING A CAVITY

Abstract

A method for manufacturing a polysilicon SOI substrate including a cavity. The method includes: providing a silicon substrate including a sacrificial layer thereon; producing a first polysilicon layer on the sacrificial layer; depositing a structuring layer on the first polysilicon layer; introducing trenches through the structuring layer, the first polysilicon layer, and the sacrificial layer up to the silicon substrate; producing a cavity in the silicon substrate by etching, an etching medium being conducted thereto through the trenches; producing a second polysilicon layer on the first polysilicon layer, the trenches being thereby closed. A micromechanical device is also described.

Claims

1-9. (canceled)

10. A method for manufacturing a polysilicon SOI substrate including a cavity, comprising the following steps: A) providing a silicon substrate including a sacrificial layer on the silicon layer; B) producing a first polysilicon layer on the sacrificial layer; C) depositing a structuring layer on the first polysilicon layer; D) introducing trenches through the structuring layer, the first polysilicon layer, and the sacrificial layer up to the silicon substrate; G) producing a cavity in the silicon substrate by etching, an etching medium being conducted thereto through the trenches; H) producing a second polysilicon layer on the first polysilicon layer to close the trenches.

11. The method for manufacturing a polysilicon SOI substrate including a cavity as recited in claim 10, further comprising the following steps: E) producing a thin oxide on surfaces of the trenches, on the first polysilicon layer; F) removing the thin oxide at a base of the trenches; wherein step E is carried out after step D and step F is carried out prior to step G.

12. The method for manufacturing a polysilicon SOI substrate including a cavity as recited in claim 10, wherein the sacrificial layer is a first silicon oxide layer.

13. The method for manufacturing a polysilicon SOI substrate including a cavity as recited in claim 10, wherein the structuring layer is a second silicon oxide layer.

14. The method for manufacturing a polysilicon SOI substrate including a cavity as recited in claim 10, wherein after step B, the first polysilicon layer is planarized by CMP and/or an ion trimming method.

15. The method for manufacturing a polysilicon SOI substrate including a cavity as recited in claim 10, wherein after step H, the second polysilicon layer is planarized using an ion trimming method.

16. A micromechanical device, comprising: a substrate; an insulation layer situated on the substrate; a first polysilicon layer situated on the insulation layer, etching access trenches being situated in the first polysilicon layer; wherein a cavity is etched into the substrate below the etching access trenches in the substrate on a side oriented toward the first polysilicon layer and the etching access trenches are at least partially closed using a second polysilicon layer.

17. The micromechanical device as recited in claim 16, wherein a direct electrical connection exists between the first polysilicon layer and the substrate.

18. The micromechanical device as recited in claim 17, wherein the direct electrical connection exists between the first polysilicon layer and the substrate up to a rear side of the substrate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] FIGS. 1A through 1G show a method for manufacturing an SOI substrate including a cavity in the related art.

[0020] FIGS. 2A through 2J show a method according to an example embodiment of the present invention for manufacturing a polysilicon SOI substrate including a cavity in successive processing steps of the substrate.

[0021] FIGS. 3A and 3B show an optional embodiment of the method according to the present invention for manufacturing a polysilicon SOI substrate including a cavity.

[0022] FIG. 4 schematically shows the example method according to the present invention for manufacturing a polysilicon SOI substrate including a cavity.

[0023] FIG. 5 schematically shows a micromechanical device manufactured using the method according to the present invention.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENT

[0024] FIGS. 1A through 1G show a method for manufacturing an SOI substrate including a cavity in the related art.

[0025] FIGS. 2A through 2J show a method according to the present invention for manufacturing an SOI substrate including a cavity in successive processing steps of the substrate.

[0026] A first oxide layer 6 is deposited or grown on a substrate 30, preferably on a monocrystalline silicon wafer (FIG. 2A). This first layer does not necessarily have to be an oxide layer according to the present invention, another dielectric layer such as a nitride or an oxynitride layer may also be used. An oxide layer is preferably grown via an oxidation process on the silicon wafer. Layers manufactured in this way have a very homogeneous oxide thickness and a very high quality.

[0027] In the next step, a first polysilicon layer 12 is deposited. This may be an LPCVD deposition or a thin LPCVD deposition including a subsequent fast epitaxial poly-deposition (FIG. 2B).

[0028] In an optional step, which is advantageous in particular in the case of thick polysilicon layers (>5 μm), the polysilicon layer, which has a tendency to be rough, is planarized. This may be carried out by a CMP method or also by an ion trimmer. Because a cavity is not yet formed below the polysilicon layer in this method state, in particular thin polysilicon layers (thickness <40 μm) may be planarized very precisely (see FIG. 2C).

[0029] In a further step, a second oxide layer 13 is deposited or grown (see FIG. 2D). This second layer does not necessarily have to be an oxide layer according to the present invention, another layer may also be used, for example, a resist layer. This may be structured more easily than an oxide layer.

[0030] In a further step, second oxide layer 13 is structured. For this purpose, initially a mask 40 is applied to the second oxide layer. Narrow access openings 14 are introduced into the second oxide layer in the area which is later to be provided with a cavity. The width of the holes or trenches is significantly less than the target thickness of the polysilicon layer, in particular less than 3 μm.

[0031] Trenches 15 are introduced into first polysilicon layer 13 by etching (see FIG. 2E). In particular, a trenching process is used which has a certain underetching 16 under the oxide layer on the polysilicon layer. In particular, a trenching process is used which underetches the oxide layer at least 20 nm.

[0032] Furthermore, first oxide layer 6 is removed under first polysilicon layer 12 at the base of trenches 15 using an anisotropic etching process 15, in particular a plasma-based etching process (see FIG. 2E).

[0033] Furthermore, a thin oxide 18 is grown or deposited. The oxide is deposited in particular on the side walls of trenches 15 in first polysilicon layer 12. In particular, a layer is deposited which is thicker than 10 nm and, on the other hand, is thinner than second oxide layer 13 on the surface of the first polysilicon layer (see FIG. 2F). This thin layer does not necessarily have to be an oxide layer according to the present invention, it may also be, for example, a layer deposited using a CF4-containing plasma.

[0034] In a further anisotropic etching step, thin oxide layer 18 is removed in trenches 15 at their bases, thus on substrate 30. The etching is carried out sufficiently briefly that the thick oxide on the surface of the polysilicon layer is not completely removed.

[0035] A cavity 19 is then generated using a trenching process having very strong underetching (see FIG. 2G) or isotropic silicon etching in substrate 30. The underetching in this etching step and the density of trenches 15 is selected in such a way that the entire area under the polysilicon layer in the substrate is underetched.

[0036] Furthermore, the oxide is removed in the area of cavity 19 in substrate 30 and on the surface of first polysilicon layer 12 using an isotropic etching method (for example, liquid HF or using gaseous HF) (see FIG. 2H).

[0037] In a further step, a second polysilicon layer 20 is preferably grown using an epitaxial method. The trench openings are thus closed. A layer 20 is preferably grown, the thickness of which is greater than half the layer thickness of first polysilicon layer 12. A layer 20 is preferably grown which is thinner than already present layer 12. The layer thickness of new layer 20 may thus still remain very precisely defined (see FIG. 2I).

[0038] In a further optional step, second polysilicon layer 20 may be planarized using an ion trimming method. It is advantageous that such methods may be carried out at pressures of less than 10 mbar, and the closure method of the cavity also generates very low pressures (>10 mbar) in the cavity. The polysilicon layer is thus not deflected during the planarization step and may be planarized very well (see FIG. 2J).

[0039] FIGS. 3A and B show an optional embodiment of the method according to the present invention for manufacturing a polysilicon SOI substrate including a cavity.

[0040] After the manufacture of the oxide layer (FIG. 2A), it may also be structured (FIG. 3A). Areas 11 thus opened are then filled using polysilicon (FIG. 3B). The open areas may be used later very well and in a simple manner as substrate contacts, in particular as substrate contacts for TSVs, or also, for example, as an etch stop layer during the gas phase etching. The substrate contacts may also be used to generate particularly tension-free suspensions toward the substrate, under which the oxides, which are usually very tension-filled, are not located.

[0041] FIG. 4 schematically shows the method according to the present invention for manufacturing a polysilicon SOI substrate including a cavity.

[0042] The method includes the required steps:

A: providing a silicon substrate including a first oxide layer thereon;
B: producing a first polysilicon layer on the first oxide layer;
C: depositing a second oxide layer on the first polysilicon layer;
D: introducing trenches through the second oxide layer, the first polysilicon layer, and the first oxide layer up to the silicon substrate;
E: producing a thin oxide on the surfaces of the trenches, in particular on the first polysilicon layer;
F: removing the thin oxide at the base of the trenches;
G: producing a cavity in the silicon substrate by etching, an etching medium being conducted thereto through the trenches;
H: producing a second polysilicon layer on the first polysilicon layer, the trenches being thereby closed.

[0043] FIG. 5 schematically shows a micromechanical device manufactured using the method according to the present invention.

[0044] A device is shown including a silicon substrate 30, a cavity 19, a first oxide layer 6, a first polysilicon layer 12, and a second polysilicon layer 20. Further functional layers 7 are situated on second polysilicon layer 20. Cantilever structures 5 are formed in first and second polysilicon layer 12, 20. A cap substrate 9 is situated with the aid of a bonding frame 8 above second polysilicon layer 20 and connected thereto. In addition, a rear contact is schematically shown. The device additionally includes several direct connections between the first polysilicon layer and the silicon substrate. Using the method according to the present invention including opening the first oxide layer, devices including one or multiple such connections may be manufactured. A fifth direct connection 26 is shown between the substrate and the polysilicon layer in an area under which a cavity is not located. Substrate contacts may thus be generated in a simple manner from the wafer front side. Furthermore, a first direct connection 22 is shown between the substrate and the polysilicon layer in an edge area or in the bonding area. Edge structures, such as diffusion stop structures, may thus be implemented at the chip edge or below the bonding frame. A second direct connection 23 between the substrate and the polysilicon layer is situated in an area which borders a cavity. Etch stop structures may thus be implemented at the edges of the cavity. A third direct connection 24 is situated between the substrate and the polysilicon layer in an area which borders a cavity or is entirely or partially enclosed by a cavity. Stress-free suspensions of the thin silicon layer without oxide substructure may thus be implemented. A fourth direct connection 25 between the substrate and the polysilicon layer is situated in an area under which a cavity is not located. Contact areas may thus be implemented toward the substrate, which may be used in the further course of the process as connections of functional elements of the thin silicon layer at the TSV.

LIST OF REFERENCE NUMERALS

[0045] 1 substrate [0046] 2 dielectric layer [0047] 3 thin monocrystalline silicon layer [0048] 4 cavity [0049] 5 cantilever structures [0050] 6 first oxide layer [0051] 7 further functional layers [0052] 8 bonding frame [0053] 9 cap wafer [0054] 10 thicker layer above cavity [0055] 12 first polysilicon layer [0056] 13 second oxide layer [0057] 14 narrow access openings [0058] 15 trenches [0059] 16 underetching [0060] 17 anisotropic etching process [0061] 18 thin oxide [0062] 19 cavity [0063] 20 second polysilicon layer [0064] 22 first direct connection [0065] 23 second direct connection [0066] 24 third direct connection [0067] 25 fourth direct connection [0068] 26 fifth direct connection [0069] 30 substrate [0070] 32 rear side [0071] 40 mask