Semiconductor sensor and method of manufacturing the same

Abstract

A semiconductor sensor, comprising a gas-sensing device and an integrated circuit is provided. The gas-sensing device includes a substrate having a sensing area and an interconnection area in the vicinity of the sensing area, an inter-metal dielectric (IMD) layer formed above the substrate in the sensing area and in the interconnection area, and an interconnect structure formed in the interconnection area; further includes a sensing electrode, a second TiO.sub.2-patterned portion, and a second Pt-patterned portion on the second TiO.sub.2-patterned portion in the sensing area. The interconnect structure includes a tungsten layer buried in the IMD layer, wherein part of a top surface of the tungsten layer is exposed by at least a via. The interconnect structure further includes a platinum layer formed in said at least the via, a TiO.sub.2 layer formed on the IMD layer, a first TiO.sub.2-patterned portion and a first Pt-patterned portion.

Claims

1. A method of manufacturing a semiconductor sensor, comprising forming a gas-sensing device and an integrated circuit and electrically connecting the gas-sensing device to the integrated circuit, and a method of manufacturing the gas-sensing device comprising: providing a substrate having a sensing area and an interconnection area in the vicinity of the sensing area; forming an inter-metal dielectric (IMD) layer above the substrate in the sensing area and in the interconnection area; forming an interconnect structure in the interconnection area, comprising: forming a tungsten layer in the IMD layer; forming a first TiO.sub.2-patterned portion on the top surface of the tungsten layer; and forming a first Pt-patterned portion on the first TiO.sub.2-patterned portion, wherein the first Pt-patterned portion directly contacts the top surface of the tungsten layer; and forming a sensing electrode on the IMD layer in the sensing area, comprising: forming a patterned TiO.sub.2 layer above the IMD layer; and forming a patterned platinum (Pt) layer above the patterned TiO.sub.2 layer.

2. The method according to claim 1, wherein forming the interconnect structure in the interconnection area further comprises: forming a titanium layer on the IMD layer; oxidizing the titanium layer at 300° C. to 450° C. to form a TiO.sub.2 layer; etching the TiO.sub.2 layer for opening the tungsten layer; and forming a platinum layer on the TiO.sub.2 layer, wherein the platinum layer directly contacts the tungsten layer.

3. The method according to claim 2, wherein forming the interconnect structure in the interconnection area further comprises: patterning the TiO.sub.2 layer and the platinum layer to form the first TiO.sub.2-patterned portion and the first Pt-patterned portion.

4. The method according to claim 3, wherein a second TiO.sub.2-patterned portion and a second Pt-patterned portion on the second TiO.sub.2-patterned portion are formed by patterning the TiO.sub.2 layer and the platinum layer, wherein the second TiO.sub.2-patterned portion and the second Pt-patterned portion are positioned below the sensing electrode, and the second Pt-patterned portion acts as a heater of the gas-sensing device.

5. The method according to claim 1, wherein forming the interconnect structure in the interconnection area further comprises: etching the IMD layer to form at least a via to expose part of a top surface of the first Pt-patterned portion; and forming a platinum layer in said at least the via, wherein the platinum (Pt) layer directly contacts said part of the top surface of the first Pt-patterned portion.

6. The method according to claim 5, wherein forming the interconnect structure in the interconnection area further comprises: forming a titanium layer on the IMD layer; oxidizing the titanium layer at 300° C. to 450° C. to form a TiO.sub.2 layer on the IMD layer; and etching the TiO.sub.2 layer and the IMD layer to form said at least the via.

7. The method according to claim 5, wherein the platinum layer of the interconnect structure and the patterned Pt layer of the sensing electrode are physically connected.

8. The method according to claim 1, wherein the method of manufacturing the gas-sensing device further comprises: forming a second TiO.sub.2-patterned portion buried in the IMD layer and positioned below the sensing electrode; and forming a second Pt-patterned portion directly on the second TiO.sub.2-patterned portion, wherein the second Pt-patterned portion acts as a heater of the gas-sensing device.

9. The method according to claim 1, wherein the method of manufacturing the gas-sensing device comprises: forming a passivation layer on the IMD layer; and removing a portion of the substrate to form a cavity.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 simply depicts a semiconductor sensor having a gas-sensing device according to one embodiment of the present disclosure.

(2) FIG. 2A-FIG. 2F illustrate a method of manufacturing a semiconductor sensor according to the first embodiment of the present disclosure.

(3) FIG. 3A-FIG. 3F illustrate a method of manufacturing a semiconductor sensor according to the second embodiment of the present disclosure.

(4) FIG. 4 illustrates a semiconductor sensor according to the third embodiment of the present disclosure.

(5) FIG. 5 illustrates a semiconductor sensor according to the fourth embodiment of the present disclosure.

DETAILED DESCRIPTION

(6) In the embodiments of the present disclosure, a semiconductor sensor having an interconnect structure with a platinum layer contacting a tungsten layer and a method of manufacturing the same are provided. Configuration of the embodied semiconductor sensor effectively improves not only the stability of the related layers at a high temperature operation, but also the quality of the interconnect structure (i.e. no diffusion issue between Pt and W), thereby improving the properties and performance of the semiconductor sensor. Moreover, the proposed structure of the present embodiments not only significantly improves performance of the semiconductor sensor, but also is compatible with the current fabrication process of the semiconductor sensor, which is suitable for mass production.

(7) FIG. 1 simply depicts a semiconductor sensor having a gas-sensing device according to one embodiment of the present disclosure. In practical application, a semiconductor wafer may include several semiconductor sensors, but FIG. 1 (and the proposed drawings of the embodiments hereinafter) only schematically shows one semiconductor sensor for the purpose of clear demonstration.

(8) According to the embodiment, a semiconductor sensor comprises a gas-sensing device (such as micro-electro-mechanical system (MEMS)) and an integrated circuit (such as the logic circuit) electrically connected to the gas-sensing device. Spatial arrangement and structural details of the gas-sensing device and the integrated circuit would be described in the following embodiments. A gas-sensing device of the embodiment comprises a substrate 10 having a sensing area A.sub.S and an interconnection area A.sub.I in the vicinity of the sensing area A.sub.S; an inter-metal dielectric (IMD) layer 112 formed above the substrate 10 in the sensing area A.sub.S and in the interconnection area A.sub.I; and an interconnect structure Sc formed in the interconnection area A.sub.I.

(9) According to the embodiment, the interconnect structure Sc includes a tungsten (W) layer 12 buried in the IMD layer 112 and a platinum (Pt) layer 151 formed in at least a via 131. Part of a top surface 12a of the tungsten layer 12 is exposed by said at least the via 131, wherein the platinum (Pt) layer 151 directly contacts the exposed part of the top surface 12a of the tungsten layer 12. Two vias 131 are exemplified in FIG. 1, but the number of the vias is not limited thereto and can be varied according to the actual needs.

(10) Additionally, the gas-sensing device of the embodiment further comprises a sensing electrode E.sub.S in the sensing area A.sub.S. In one embodiment, the sensing electrode E.sub.S is formed on the IMD layer 112 and comprises a patterned TiO.sub.2 layer 142 formed on the IMD layer 112, and a patterned platinum (Pt) layer 152 formed on the patterned TiO.sub.2 layer 142.

(11) Several embodiments are provided hereinafter with reference to the accompanying drawings for describing the related procedures and configurations. Related structural details, such as layers and spatial arrangement, are further described in the embodiments. However, the present disclosure is not limited thereto. It is noted that not all embodiments of the invention are shown. The identical and/or similar elements of the embodiments are designated with the same and/or similar reference numerals. Also, it is noted that there may be other embodiments of the present disclosure which are not specifically illustrated. Modifications and variations can be made without departing from the spirit of the disclosure to meet the requirements of the practical applications. It is also important to point out that the illustrations may not be necessarily be drawn to scale. Thus, the specification and the drawings are to be regard as an illustrative sense rather than a restrictive sense.

(12) Moreover, use of ordinal terms such as “first”, “second”, etc., in the specification and claims to describe an element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a certain name from another element having the same name (but for use of the ordinal term) to distinguish the claim elements.

First Embodiment

(13) Please refer to FIG. 2A to FIG. 2F, which illustrate a method of manufacturing a semiconductor sensor according to the first embodiment of the present disclosure. In the first embodiment, the platinum layer 251 directly contacts not only the top surface 22a of the tungsten layer 22 but also the sidewalls 231b of the vias 231. Also, a semiconductor sensor with heater is exemplified.

(14) First, a substrate 20 is provided, with an integrated circuit IC formed on the substrate 20 and buried in an insulating layer 211 (ex: ILD/IMD), as shown in FIG. 2A. The integrated circuit IC (having a logic device 21D, for example) is electrically connected to a gas-sensing device fabricated later.

(15) Moreover, the gas-sensing device of the first embodiment further comprises a heater 23H in the sensing area A.sub.S, and the heater 23H is buried in the IMD layer 212, wherein the heater 23H is spaced apart from the tungsten layer 22 in the interconnection area A.sub.I. The heater 23H is electrically connected to the interconnect structure Sc by routing, which is not shown in the drawing. A method of manufacturing the gas-sensing device of the first embodiment is described below.

(16) As shown in FIG. 2A, a titanium (Ti) layer 24 is formed on the IMD layer 212, such as by deposition. Also, the titanium layer is deposited in the sensing area A.sub.S and in the interconnection area A.sub.I. Then, the titanium layer 24 is oxidized at a sufficient high temperature to form a TiO.sub.2 layer 240, as shown in FIG. 2B. Oxidation of the titanium layer 24 can be performed in furnace. In one embodiment, the temperature of Ti oxidation is in a range of 300° C. to 450° C.

(17) Next, the TiO.sub.2 layer 240 and the IMD layer 212 are etched to form the vias 231 in the interconnection area A.sub.I, wherein the vias 231 expose parts of the top surface 22a of the tungsten layer 22, as shown in FIG. 2C. Then, a platinum (Pt) layer 25 is formed on the TiO.sub.2 layer 240 and the sidewalls 231b of the vias 231, so that the platinum (Pt) layer 25 directly contacts the top surface 22a of the tungsten layer 22, as shown in FIG. 2D.

(18) Afterwards, the platinum (Pt) layer 25 and the TiO.sub.2 layer 240 are patterned to form a sensing electrode E.sub.S in the sensing area A.sub.S and the interconnect structure Sc in the interconnection area A.sub.I, as shown in FIG. 2E. In the first embodiment, after Pt patterning, the interconnect structure Sc comprises the tungsten layer 22 buried in the IMD layer 212, the TiO.sub.2 layer 241 formed on the IMD layer 212 adjacent to the vias 231, and the platinum layer 251 directly formed on the TiO.sub.2 layer 241 and at the sidewalls 231b and the bottom of the vias 231, wherein the platinum layer 251 directly contacts the top surface 22a of the tungsten layer 22. Moreover, after Pt patterning, the sensing electrode E.sub.S of the gas-sensing device includes a patterned TiO.sub.2 layer 242 formed on the IMD layer 212′, and a patterned platinum (Pt) layer 252 formed on the patterned TiO.sub.2 layer 242. Also, the heater 23H is positioned correspondingly to (ex: beneath) the sensing electrode E.sub.S.

(19) According to the method of the first embodiment, since the platinum layer 251 and the patterned platinum layer 252 are formed simultaneously by patterning the Pt layer 25, the platinum layer 251 of the interconnect structure Sc further extends to the sensing area A.sub.S as shown in FIG. 2E, wherein the patterned Pt layer 252 of the sensing electrode E.sub.S are physically connected to the platinum layer 251 of the interconnect structure Sc.

(20) Afterwards, a passivation layer 26 is formed on the IMD layer 212′ to filled up the vias 231 in the interconnection area A.sub.I, followed by patterning the passivation layer 26 so as to expose the sensing electrode E.sub.S in the sensing area A.sub.S and form an opening 27 in the pad region (ex: exposing a pad 21P). Then, a cavity 28 is formed as shown in FIG. 2F (for example, a portion of the substrate 20 is removed by etching to form the cavity 28 correspondingly to the sensing electrode E.sub.S). In the first embodiment, the integrated circuit IC (ex. including the logic device 21D electrically connected to the gas-sensing device GSD) is positioned beneath the gas-sensing device GSD, and is positioned between the substrate 20 and the gas-sensing device GSD, as shown in FIG. 2F.

(21) Additionally, the gas-sensing device GSD of the embodiment further comprises a gas sensing layer (not shown in FIG. 2F) formed on (ex: cover) the sensing electrode so as to span the sensing electrode. In one example, the gas sensing layer can be formed on the sensing electrode E.sub.S after formation of the cavity 28. For a semiconductor sensor, the gas-sensitive layer (ex: a MOS layer) deposited on the sensing electrode is capable of absorbing a gas, depending on the material of the gas sensing layer. The gas sensing layer can be deposited by sputtering, or can be electrochemically grown on the sensing electrode E.sub.S. Also, the gas sensing layer can be made of an inorganic material such as metal oxide (ex: tin oxide), or can be made of an organic material (such as a polymer or phthalocyanine). When the gas interacts with the gas sensing layer, the conductivity of the gas sensing layer changes, and this can be detected by appropriate circuitry. Therefore, the gas-sensing device GSD of the semiconductor sensor, comprising the sensing electrode E.sub.S and the gas-sensitive layer and the interconnect structure Sc, provides an electrical output indicative of gas reaction with the gas-sensitive layer. An electrical output indicative of gas reaction with the gas-sensitive layer is transmitted to the integrated circuit IC through the interconnect structure Sc to carry out the logic operation. The heater 23H is provided for heating the gas sensing layer to promote gas reaction with the gas sensing layer. Although the first embodiment provides a tungsten (W) heater 23H, which can be fabricated with the tungsten layer 22 of the interconnect structure Sc by using the same W material layer, it is noted that the heater 23H can be formed of tungsten or other suitable materials, and the disclosure is not limited thereto.

Second Embodiment

(22) Please refer to FIG. 3A to FIG. 3F, which illustrate a method of manufacturing a semiconductor sensor according to the second embodiment of the present disclosure. In the second embodiment, the platinum layer 251 of the interconnect structure Sc directly contacts not only the top surface 22a of the tungsten layer 22 but also the sidewalls 231b of the vias 231. Also, the second embodiment provides a Pt/TiO.sub.2 heater, which can be fabricated with the Pt/TiO.sub.2 layer of the interconnect structure Sc by using the same Pt/TiO.sub.2 material layers. Also, the identical and/or similar elements of the second and first embodiments are designated with the same and/or similar reference numerals, and the details of the configurations, procedures and working principles of the identical components/layers are not redundantly described.

(23) As shown in FIG. 3A, Ti deposition and oxidation (ex: at a temperature ranged from 300° C. to 450° C.) is conducted to form a TiO.sub.2 layer 2400 on the IMD layer 212. Then, the TiO.sub.2 layer 2400 is patterned (ex: by etching) to form a patterned TiO.sub.2 layer 2400′ for opening the tungsten layer 22, as shown in FIG. 3B. A platinum layer 2500 is formed on the patterned TiO.sub.2 layer 2400′ and fills up the openings 2400v of the patterned TiO.sub.2 layer 2400′, so that the platinum layer 2500 directly contacts the top surface 22a of the tungsten layer 22, as shown in FIG. 3C.

(24) Next, the patterned TiO.sub.2 layer 2400′ and the platinum layer 2500 are patterned to form a Pt/TiO.sub.2 heater 23H′ and a Pt/TiO.sub.2 multi-layer of the interconnect structure Sc, as shown in FIG. 3D. Then, the material of the IMD layer 212 is further formed to cover the Pt/TiO.sub.2 heater 23H′ and the Pt/TiO.sub.2 multi-layer of the interconnect structure Sc (i.e. forming a thickened IMD layer 212′), followed by formation and patterning of another TiO.sub.2 (ex: Ti deposition and oxidation) and another platinum layer, as shown in FIG. 3E. Afterwards, formation of the passivation layer 26, formation of the opening 27 in the pad region (ex: exposing a pad 21P), and removal of a portion of the substrate 20 for forming the cavity 28, are conducted, as shown in FIG. 3F. The steps for forming the structure of FIG. 3F are similar to that of FIG. 2F, which are not repeated herein.

(25) According to the second embodiment, the interconnect structure Sc in the interconnection area A.sub.I comprise a first TiO.sub.2-patterned portion 2401 formed on the top surface 22a of the tungsten layer 22 and a first Pt-patterned portion 2501 formed on the first TiO.sub.2-patterned portion 2401, wherein the first Pt-patterned portion 2501 directly contacts the top surface 22a of the tungsten layer 22. According to the second embodiment, the gas-sensing device GSD in the sensing area A.sub.S further comprises a second TiO.sub.2-patterned portion 2402 (buried in the thickened IMD layer 212′ and positioned below the sensing electrode E.sub.S), and a second Pt-patterned portion 2502 directly formed on the second TiO.sub.2-patterned portion 2402, wherein the second Pt-patterned portion 2502 acts as a heater of the gas-sensing device GSD of the second embodiment. As shown in FIG. 3E and FIG. 3F, the platinum layer 251 in the vias 231 directly contacts the first Pt-patterned portion 2501, so as to form a direct connection between Pt and W of the interconnect structure Sc in the interconnection area A.sub.I.

(26) Accordingly, the first embodiment uses W as the material of the heater 23H and Pt as the material of the sensing electrode E.sub.S. The second embodiment uses Pt as the material of the heater 23H′ and the sensing electrode E.sub.S.

Third Embodiment

(27) In the first and second embodiment, the integrated circuits IC, including the logic device 21D electrically connected to the gas-sensing device GSD, are positioned beneath the gas-sensing devices GSD (ex: the integrated circuits IC positioned between the substrate 20 and the gas-sensing device GSD), as shown in FIG. 2F and FIG. 3F. However, the disclosure is not limited thereto. The gas-sensing devices GSD and the integrated circuit IC can be formed on the different chips and electrically connected to each other by wire bonding, as exemplified in the third embodiment.

(28) FIG. 4 illustrates a semiconductor sensor according to the third embodiment of the present disclosure. In FIG. 4, a gas-sensing device GSD (exemplified by, but not limited to, the gas-sensing device GSD of the second embodiment, as shown in FIG. 3F) is formed on the substrate 20 while an integrated circuit IC (having another pad 32P, for example) is formed on another substrate 30. The gas-sensing devices GSD and the integrated circuit IC formed on the different chips are connected to each other by the bonding the pads 21P and 32P through the wire 34.

Fourth Embodiment

(29) In the first to third embodiments, the drawings depict that the platinum layer 251 of the interconnect structure Sc directly contact the sidewalls 231b of the vias 231. However, the disclosure is not limited thereto. In an alternative configuration, it is also applicable by forming a TiO.sub.2 layer on the sidewalls 231b of the via 231 but not on the top surface 22a of the tungsten layer 22. FIG. 5 illustrates a semiconductor sensor according to the fourth embodiment of the present disclosure. The semiconductor sensor of the fourth embodiment is identical to the semiconductor sensor of the first embodiment (FIG. 2F), except for the positions of the TiO.sub.2 layers 241′ and 241. Details of the identical elements (designated with the same reference numerals) of the fourth and first embodiments are not redundantly described.

(30) As shown in FIG. 5, the TiO.sub.2 layer 241′ is formed on the sidewalls 231b of the via 231 but not formed on the top surface 22a of the tungsten layer 22, and the platinum layer 251 also directly contacts the top surface 22a of the tungsten layer 251. The semiconductor sensor of the fourth embodiment can be manufactured by slightly modifying the method for manufacturing that of the first embodiment (please also refer to FIG. 2A-FIG. 2F for the related layers as mentioned herein). For example, the interconnect structure Sc in the interconnection area A.sub.I according to the fourth embodiment may include steps of etching the IMD layer 212 to form the vias 231 to expose part of the top surface 22a of the tungsten layer 22; forming a titanium layer 24 on the IMD layer 212 and extending as a Ti-liner in the vias 231; oxidizing the titanium layer 24 (ex: at 300° C. to 450° C.) to form a TiO.sub.2 layer 240 on the IMD layer 212 and a TiO.sub.2-liner in the vias 231; removing a bottom portion of the TiO.sub.2-liner to expose the top surface 22a of the tungsten layer 22; and forming a platinum layer on the TiO.sub.2 layer and extending to the vias 231 to form a Pt-liner in the vias 231, wherein the Pt-liner in the vias 231 directly contact the top surface 22a of the tungsten layer 22.

(31) According to the aforementioned descriptions, the semiconductor sensors of the embodiments possess several advantages. Since the gas-sensing device is operated at a high temperature, the stability of the related layers of the gas-sensing device at high temperature would be one of important factors for the performance of the gas-sensing device. During operation of the gas-sensing device having a heater, TiO.sub.2 is more stable than Ti or TiN at a high temperature. Accordingly, compared to the conventional gas-sensing device (ex: using Ti or TiN as a barrier/adhesion layer below a platinum (Pt) layer), the embodied gas-sensing device of the semiconductor sensors having the TiO.sub.2 as the barrier/adhesion layer would be more stable at a high temperature operation. Also, according to the design of the embodied gas-sensing device, the Pt layer 251 directly contacts the W layer 22, and there is no diffusion issue between Pt and W. Therefore, the proposed embodiments significantly improve the properties and performances of the semiconductor sensor in the applications. Moreover, the method for manufacturing the proposed structure of the embodiments is compatible with the current fabrication process of the semiconductor sensor, which is suitable for mass production. For example, in one of practical applications, the W layer 22 can be fabricated with a heater 23H by patterning the same tungsten layer, which is easy and time-saving.

(32) Other embodiments with different configurations of known elements in the semiconductor sensor can be applicable, and the arrangement depends on the actual needs of the practical applications. It is, of course, noted that the configurations of figures are depicted only for demonstration, not for limitation. It is known by people skilled in the art that the shapes or positional relationship of the constituting elements and the procedure details could be adjusted according to the requirements and/or manufacturing steps of the practical applications.

(33) While the disclosure has been described by way of example and in terms of the exemplary embodiment(s), it is to be understood that the disclosure is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.