Method for amplifier load current cancellation in a current integrator and current integrator with amplifier load current cancellation

Abstract

The amplifier load current cancellation in a current integrator comprises applying an input current to an operational transconductance amplifier provided with an integration capacitor for current integration, leading an output current of the operational transconductance amplifier through a sensing resistor, thus producing a voltage drop over the sensing resistor, generating a cancellation current dependent on the voltage drop over the sensing resistor, and injecting the cancellation current to the output current, before or after the output current passes the sensing resistor, thus eliminating a dependence of the output current on the input current.

Claims

1. A method for amplifier load current cancellation in a current integrator, comprising: applying an input current to an operational transconductance amplifier provided with an integration capacitor for current integration, leading an output current of the operational transconductance amplifier through a sensing resistor, thus producing a voltage drop over the sensing resistor, generating a cancellation current dependent on the voltage drop over the sensing resistor, and injecting the cancellation current to the output current, before or after the output current passes the sensing resistor, thus eliminating a dependence of the output current on the input current.

2. The method of claim 1, further comprising: integrating the voltage drop over the sensing resistor and converting the integrated voltage drop into the cancellation current.

3. The method of claim 2, wherein the cancellation current is injected to the output current after the output current passes the sensing resistor.

4. The method of claim 2 further comprising: providing a switched capacitor integrator, and integrating the voltage drop by the switched capacitor integrator.

5. The method of claim 1, wherein the voltage drop over the sensing resistor is sampled on a capacitor, and the sampled voltage drop is converted into the cancellation current.

6. The method of claim 5, wherein the sampled voltage drop is converted into the cancellation current by a further operational transconductance amplifier.

7. The method of claim 5, wherein the cancellation current is injected to the output current before the output current passes the sensing resistor.

8. A current integrator, comprising: an operational transconductance amplifier provided with an integration capacitor for current integration, a sensing resistor connected to an output of the operational transconductance amplifier, a conversion circuit configured for converting a voltage drop over the sensing resistor to a cancellation current, and a connection between an output of the conversion circuit and a node located immediately before or immediately after the sensing resistor.

9. The current integrator of claim 8, wherein the conversion circuit comprises a further integrator configured to integrate the voltage drop over the sensing resistor.

10. The current integrator of claim 9, further comprising: a further operational transconductance amplifier of the conversion circuit, the further operational transconductance amplifier being configured to convert an output of the further integrator into the cancellation current.

11. The current integrator of claim 10, wherein the sensing resistor is arranged between the operational transconductance amplifier and an output node, and an output of the further operational transconductance amplifier is connected to the output node.

12. The current integrator of claim 9, wherein the further integrator is a switched capacitor integrator.

13. The current integrator of claim 8, wherein the conversion circuit is configured to sample the voltage drop over the sensing resistor on a capacitor.

14. The current integrator of claim 13, further comprising: a further operational transconductance amplifier of the conversion circuit, the further operational transconductance amplifier being configured to convert the sampled voltage drop into the cancellation current.

15. The current integrator of claim 14, wherein an output of the further operational transconductance amplifier is connected to a node between the operational transconductance amplifier and the sensing resistor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows diagrams illustrating a load current cancellation method.

(2) FIG. 2 shows diagrams illustrating a further load current cancellation method.

(3) FIG. 3 shows a circuit diagram for an implementation of the further load current cancellation method.

(4) FIG. 4 shows a circuit diagram of a current domain incremental two-step analog-to-digital converter using the load current cancellation circuit.

(5) FIG. 5 is a timing diagram for the circuit of FIG. 4.

(6) FIG. 6 shows a circuit diagram of a basic integration stage used in delta-sigma converters.

(7) FIG. 7 shows a circuit diagram of an assisted operational amplifier technique.

(8) FIG. 8 shows the supply voltage V.sub.DAC and the deviations of the virtual ground potential v.sub.n from the ground potential gnd as functions of time t.

DETAILED DESCRIPTION

(9) FIG. 1 shows diagrams illustrating a load current cancellation method. The operational transconductance amplifier has a transconductance g.sub.m. An integration capacitor C.sub.int is provided for current integration. A sensing resistor R.sub.sense is provided to sense the output current I.sub.out in order to obtain a linear estimate of the output current I.sub.out. The sensing resistor R.sub.sense is sized for a voltage drop of a fraction of the available output swing of the operational transconductance amplifier in order not do degrade the performance of the operational transconductance amplifier. The voltage drop over the sensing resistor R.sub.sense is buffered and integrated, in particular with a switched capacitor integrator, for instance.

(10) The integrator output is converted into a current which is injected at the output via a further operational transconductance amplifier, which has a transconductance g.sub.m2. In turn the output current of the operational transconductance amplifier will decrease, which reduces the voltage drop over the sensing resistor R.sub.sense. Thus a feedback loop is formed, which drives the voltage drop over the sensing resistor R.sub.sense (i. e., the load current of the operational transconductance amplifier) to zero. This feedback loop is nested in the feedback loop of the operational transconductance amplifier and requires low loop gain to guarantee stability.

(11) FIG. 2 shows diagrams illustrating a further load current cancellation method, which does not use feedback. The voltage drop over the sensing resistor R.sub.sense is buffered and sampled, in particular on a capacitor, for instance. For this purpose two separate capacitors may be provided, which are alternatingly switched by a first clock signal clk.sub.1 and a second clock signal clk.sub.2 synchronized with the DAC clock signal clk.sub.DAC, as shown in FIG. 2. The sampled voltage is converted to a cancellation current I.sub.out, cancel, which cancels the load current at the output of the operational transconductance amplifier.

(12) In the circuit according to FIG. 2, there is no feedback loop to pose stability and settling requirements, because the operational transconductance amplifier will always adjust its output current I.sub.out to match the required load current I.sub.load in combination with the injected cancellation current I.sub.out, cancel: I.sub.out=I.sub.out, cancel+I.sub.load

(13) Hence the voltage drop over the sensing resistor R.sub.sense is constant and independent of the cancellation current I.sub.out, cancel. The cancellation current I.sub.out, cancel is injected based on the measured output current I.sub.out from the previous clock cycle. This cancellation scheme is therefore efficient as long as the time constant of the input signal is larger than the period of the DAC clock signal clk.sub.DAC. This is typically the case in oversampled delta-sigma converters. This assumption is valid especially when low-frequency linearity is a concern.

(14) An example of a detailed circuit implementation of the further load current cancellation method is depicted in FIG. 3. The voltage at the sensing resistor R.sub.sense may be differentially sampled to eliminate systematic charge injection errors. A connection of both capacitors during switch transitions can be avoided by a non-overlapping sample clock. Moreover, switching according to the first clock signal clk.sub.1 and the second clock signal clk.sub.2 is performed after the DAC settling finishes. A linear transconductor is employed to convert the sampled voltage at the sensing resistor R.sub.sense to the cancellation current I.sub.out, cancel=I.sub.out.Math.Q.sub.R, where Q.sub.R is the quotient of the electrical resistances of the sensing resistor R.sub.sense and the resistor R.

(15) The achieved cancellation is essentially insensitive to process tolerances and temperature variations, since it only depends on the quotient Q.sub.R, and an exact cancellation by an accurate match of the electrical resistances of the sensing resistor R.sub.sense and the resistor R is comparatively easily obtained. The linear transconductor employs local feedback to achieve linearity and thus is subjected to the same settling constraint as the main integrator itself.

(16) However, owing to the absence of a large load capacitance in the local feedback loop, the settling requirement can be achieved at much lower power consumption than for the main integrator. Besides, noise from the buffer and transconductor is injected at the integrator output so that it is highly suppressed by the OTA open loop gain. Hence, the power and noise penalty of the load current cancellation scheme is low.

(17) FIG. 4 shows a circuit diagram of a current domain incremental two-step analog-to-digital converter. In this circuit the residue of the first analog-to-digital converter is converted by a second stage analog-to-digital converter. The first stage is implemented as current controlled oscillator (CCO). The integrator output is compared to a reference voltage V.sub.ref, and the comparator output is synchronized to the clock signal clk. The synchronized comparator output triggers the DAC feedback pulses. DAC feedback is realized by a precharged capacitor that is discharged into the virtual ground node (SC DAC). The total number of feedback pulses n.sub.count during one full integration period T.sub.int provides the course analog-to-digital conversion value.

(18) The first stage can work as stand-alone or be combined with a fine conversion result by digitization of the output residue V.sub.residue of the CCO in order to increase resolution. As the two-stage concept requires a large sampling capacitor that might not correlate to the integration capacitor C.sub.int in terms of process, voltage and temperature variation (PVT), using the output cancellation technique described above is particularly powerful because it is inherently PVT robust.

(19) FIG. 5 is a timing diagram for the circuit of FIG. 4. FIG. 5 shows the clk signal clk, the sample and reset signal pulses, the pulsed voltage V.sub.pulse, and the integrated output voltage V.sub.out_int as functions of the time t.

(20) An offset in the buffer and linear transconductor translate to increased offset at the OTA input. This does not affect linearity but gives rise to a constant DAC offset error. This is not a drawback, because the operational transconductance amplifier itself exhibits offset, and hence the DAC offset must anyway be calibrated in applications with high gain accuracy requirements.

(21) With the described method the output current is precisely measured and converted into a precise cancellation current. Linearity is thus guaranteed, as opposed to conventional calibration assisted solutions. This method has the advantage that it takes account of the static deviation Δv.sub.n, stat of the virtual ground potential v.sub.n at the end of the DAC pulse. The described method accurately eliminates the static error both for voltage and current domain topologies.