CONVERTING DIGITAL IMAGE DATA

Abstract

The present disclosure relates to a processing arrangement for converting digital image data. Conventional approaches suffer from speed or non-ideal compressing schemes. These drawbacks are overcome by the processing arrangement for determining a digital output value from a digital input value based on a linear function and a square root function. The processing arrangement includes a first calculation block configured to determine a first output value of the linear function, a second calculation block configured to determine a second output value of the square root function. A selector is configured to select, based on a comparison between the digital input value and a threshold value, whether the digital output value is determined by the first calculation block or by the second calculation block.

Claims

1. A processing arrangement for converting digital image data by determining a digital output value from a digital input value based on a linear function and a square root function, the processing arrangement comprising: a first calculation block configured to determine a first output value of the linear function, a second calculation block configured to determine a second output value of the square root function, and a selector configured to select based on a comparison between the digital input value and a threshold value whether the digital output value is determined by the first calculation block or by the second calculation block wherein the linear function is defined by y1 = A .Math. IN, A being a first factor, and wherein the square root function is defined by $y2=C\cdot \sqrt{IN-D}-B,$ C being a second factor, B being a first subtrahend and D being a second subtrahend.

2. (canceled)

3. The processing arrangement according to claim 1, wherein a combined function is formed by applying the linear function for digital input values smaller than the threshold value and by applying the square root function for digital input values larger than the threshold value, the combined function being continuous at the threshold value, so that the first subtrahend is determined by $B=\frac{C^2}{2\cdot A}-A\cdot XLIN,$ the second subtrahend is determined by $D=XLIN-\frac{C^2}{4\cdot A^2},$ and the second factor is determined by $C=\frac{YMAX-A\cdot XLIN}{\sqrt{XMAX-\frac{YMAX}{A}}},$ where YMAX is a maximum digital output value and XMAX is a maximum digital input value of the processing arrangement.

4. The processing arrangement according to claim 1, wherein the second calculation block further comprises at least one left shift operator configured to shift, based on the size of the digital input value, the digital input value and the second subtrahend two-bit-wise to the side of the Most Significant Bit, MSB, and at least one right shift operator configured to shift a digital intermediate value bit-wise to the side of the Least Significant Bit, LSB.

5. The processing arrangement according to claim 1, wherein in the second calculation block the second factor comprises a mantissa term and an exponential term and wherein a multiplication of a digital value with the exponential term corresponds to a shift operation of the digital value.

6. The processing arrangement according to claim 1, wherein the second calculation block further comprises a noise injection operator configured to add a random value to the LSB-side of a further digital intermediate value, and/or a rounding operator configured to round a second further digital intermediate value up to a predetermined accuracy, and/or a clipping operator configured to clip a third further digital intermediate value in case it exceeds the maximum digital output value.

7. The processing arrangement according to claim 1, wherein the second calculation block further comprises a cascade of circuits, the cascade being configured to determine a digital output word forming the square root of a digital input word, and wherein each circuit within the cascade comprises a first input for receiving a portion of the digital input word of maximum two bits, a logic block configured to determine an output bit of the digital output word and a temporary calculation rest based on the portion of the digital input word, and a first output for forwarding of at least a portion of the digital output word as a temporary calculation result.

8. The processing arrangement according to claim 7, wherein each circuit except a first circuit and a last circuit within the cascade further comprises a second input for receiving the temporary calculation rest of a preceding circuit, a third input for receiving the temporary calculation result from the first output of the preceding circuit, and a second output for forwarding the temporary calculation rest of the circuit to the second input of a subsequent circuit .

9. The processing arrangement according to claim 8, wherein the first circuit within the cascade further comprises a second input for receiving a logical “0” as the temporary calculation rest and a second output for forwarding the temporary calculation rest of the first circuit to the second input of the subsequent circuit, and wherein the last circuit within the cascade further comprises a second input for receiving the temporary calculation rest from the second output of the preceding circuit, a third input for receiving the temporary calculation result from the first output of the preceding circuit, and wherein the first output of the last circuit forwards the output word.

10. The processing arrangement according to claim 1, which is implemented as an integrated circuit, in particular as an application-specific integrated circuit, ASIC.

11. An image sensor comprising the processing arrangement according to claim 1, the image sensor providing sensor values from a plurality of image pixels, wherein the processing arrangement converts the sensor values, in particular in a serial fashion.

12. A calculation method for converting digital image data by determining a digital output value from a digital input value based on a linear function and a square root function, the calculation method comprising: selecting based on a comparison between the digital input value and a threshold value whether the digital output value is determined by a first output value or a second output value, determining the first output value of the linear function, and/or determining a second output value of the square root function by conducting a square root calculation procedure wherein the linear function is defined by y1 = A .Math. IN, A being a first factor, and wherein the square root function is defined by $y2=C\cdot \sqrt{IN-D}-B,$ C being a second factor, B being a first subtrahend and D being a second subtrahend.

13. (canceled)

14. The calculation method according to claim 12, wherein determining the second output value further comprises shifting, based on the size of the digital input value the digital input value and the second subtrahend two-bit-wise to the side of the Most Significant Bit, MSB, determining a digital input word INW = IN′ - D′, where IN′ is the shifted digital input value and D′ is the shifted second subtrahend, determining a digital output word $OUTW=\sqrt{INW}$ by performing the square root calculation procedure, providing the second factor as a mantissa term and an exponential term, determining a digital intermediate value by, $IMD1=C\_VAL\cdot OUTW$ shifting, based on the size of the digital input value and the exponential term, the digital intermediate value bit-wise to the side of the Least Significant Bit, LSB, and determining a further digital intermediate value by, $IMD2=IMD1ʹ-B$ where IMD1′ is the shifted digital intermediate value.

15. The calculation method according to claim 12, wherein the square root calculation procedure for determining a digital output word from a digital input word further comprises splitting the digital input word into portions of maximum two bits, assigning each portion of the digital input word to subsequent calculation steps, starting with the portion on the MSB-side of the digital input word and proceeding with subsequent portions towards the LSB-side, wherein each calculation step comprises forming a temporary calculation rest by concatenating the respective portion of the calculation step to the temporary calculation rest of a preceding calculation step, if a preceding calculation step is present, determining an internal calculation error by Y = 4 .Math. R + 1, where R is a temporary calculation result of the preceding calculation step, if a preceding calculation step is present, comparing the temporary calculation rest with the internal calculation error, concatenating a logical “1” bit to the temporary result and adjusting the temporary calculation rest by subtracting the internal calculation error, if the internal calculation error is smaller than or equal as the temporary calculation rest, concatenating a logical “0” bit to the temporary result, if the internal calculation error is larger than the temporary calculation rest.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0079] FIG. 1 shows a transfer curve comprising two distinctive parts according to a linear function and a square root function.

[0080] FIG. 2 shows an embodiment of a processing arrangement.

[0081] FIG. 3 shows another an embodiment of a processing arrangement.

[0082] FIG. 4 shows an embodiment of a cascade of circuits for calculating the square root of a digital input word.

[0083] FIG. 5 shows an embodiment of one exemplary circuit within a cascade of circuits.

[0084] FIG. 6 shows an example for calculating the square root of an exemplary digital input word.

[0085] FIG. 7 shows an image sensor comprising a processing arrangement.

DETAILED DESCRIPTION

[0086] In FIG. 1 a transfer curve is shown, according to which the conversion of digital input values IN into digital output values OUT can be performed. On the x-axis the digital input values are shown, which can reach a maximum digital input value XMAX. On the y-axis the digital output values are shown, which can reach a maximum digital output value YMAX.

[0087] The transfer curve forms a combined function, which comprises two distinctive parts. The first part is formed by a linear function 1 describing the equation OUT =A.square-solid.IN, with a first factor A. The first part of the combined function forming the linear function 1 is only valid for digital input values in the range from zero, IN = 0, to a threshold value XLIN, IN = XLIN. The second part of the combined function is formed by a square root function 2 describing the equation

[00008]$OUT=C\cdot \sqrt{IN-D}-B,$

with a first subtrahend B, a second factor C and a second subtrahend D. The second part of the combined function forming the square root function 2 is only valid for digital input values in the range from the threshold value XLIN, IN = XLIN, to the maximum digital input value XMAX, IN = XMAX.

[0088] The combined function is continuously differentiable at the threshold value XLIN. As such, both function values and the derivatives of the linear function 1 and the square root function 2 are equal at the threshold value XLIN. This can be written as

[00009]$\begin{array}{cc}A=\frac{C}{2\cdot \sqrt{XLIN-D}}& \text{­­­(1)}\end{array}$

[00010]$\begin{array}{cc}A\cdot XLIN=C\cdot \sqrt{XLIN-D}-B& \text{­­­(2)}\end{array}$

[0089] Replacing the square root in formula (2) by the one on formula (1) leads to

[00011]$\begin{array}{cc}B=\frac{C^2}{2\cdot A}-A\cdot XLIN& \text{­­­(3)}\end{array}$

[0090] At the maximum digital input value XMAX, the square root function 2 should obtain the result YMAX. This means that

[00012]$YMAX=C\cdot \sqrt{XMAX-D}-B,$

where the second subtrahend D can be replaced by an expression coming from equation (1) and the first subtrahend B can be replaced by an expression coming from equation (2). This leads to the second factor C:

[00013]$\begin{array}{cc}C=\frac{YMAX-A\cdot XLIN}{\sqrt{XMAX-\frac{YMAX}{A}}}& \text{­­­(4)}\end{array}$

[0091] Inserting this expression for the second factor C into the equations (1) and (2) leads to the second subtrahend D:

[00014]$\begin{array}{cc}D=XLIN-\frac{C^2}{4\cdot A^2}& \text{­­­(5)}\end{array}$

[0092] In practical applications of applying the transfer curve shown in FIG. 1, the first factor A can be chosen to be 1. This further simplifies the equations (3) to (5). However, the first factor A can also be chosen to be different than 1.

[0093] The transfer curve shown in FIG. 1 can be used to convert digital image data. As such, the conversion corresponds to a compression of data. In the following Figures it is shown, how a compression according to the transfer curve can be implemented in a processing arrangement 3 and/or in a calculation method for converting digital image data.

[0094] FIG. 2 shows an embodiment of a processing arrangement 3 for converting digital image data according the transfer curve shown in FIG. 1. However, FIG. 2 can also be interpreted as block diagram for a calculation method for determining a digital input value IN from a digital output value OUT based on the transfer curve shown in FIG. 1. The processing arrangement 3 comprises an input 4 for receiving the digital input value IN. The processing arrangement further comprises a first calculation block 6, which is configured to determine a first output value y1. The first calculation block 6 is connected to the input 4 of the processing arrangement 3, so that the first calculation block 6 receives the digital input value IN. In the embodiment shown in FIG. 2 the first calculation block 6 transmits the digital input value IN unchanged. This means that the first factor A is chosen to be 1, so that the first output value y1 equals the digital input value IN.

[0095] The processing arrangement 3 further comprises a second calculation block 7, which is configured to determine a second output value y2. The second calculation block 7 is connected to the input 4 of the processing arrangement 3, so that the second calculation block 7 receives the digital input value IN. The digital input value IN is forwarded to a first sum operator 8, which is configured to subtract the second subtrahend D from the digital input value IN and to forward the result of this subtraction as a digital input word INW.

[0096] The second calculation block 7 further comprises a first tester 9, which is connected at its input side to the first sum operator 8. The first tester 9 checks if the digital input word INW is positive. If this is the case, the digital input word INW is transmitted unchanged. If this is not the case, the digital input word INW is set to zero.

[0097] The second calculation block 7 further comprises a square root operator 10 connected at its input side with the first tester 9. The square root operator 10 is configured to determine a digital output word OUTW from the digital input word INW by calculating the square root of the digital input word INW.

[0098] The digital output word OUTW is forwarded to a multiplier 11 of the second calculation block 7, which is configured to multiply the second factor C with the digital output word OUTW and to forward the result of this multiplication as digital intermediate value IMD1.

[0099] The digital intermediate value IMD1 is forwarded to a second sum operator 12, which is configured to subtract the first subtrahend B from the digital intermediate value IMD1 and to forward the result of this subtraction as a second output value y2.

[0100] The second calculation block 7 further comprises a second tester 13, which is connected at its input side to the second sum operator 12. The tester 13 checks if the second output value y2 is positive. If this is the case, the second output value y2 is transmitted unchanged. If this is not the case, the second output value y2 is set to zero.

[0101] The second calculation block 7 further comprises a selector 14, which is configured to select, based on a comparison between the digital input value IN and a threshold value XLIN, whether the digital output value OUT is determined by the first calculation block 6 or by the second calculation block 7.

[0102] The result of that selection is forwarded to an output 5 of the processing arrangement 3, where the first output value y1 and the second output value y2 are provided. Based on the selection by the selector 14, either the first output value y1 or the second output value y2 is forwarded by the output 5 as digital output value OUT.

[0103] FIG. 3 shows another embodiment of the processing arrangement 3. However, FIG. 3 can also be interpreted as block diagram for another embodiment of the calculation method for determining a digital input value IN from a digital output value OUT based on the transfer curve shown in FIG. 1.

[0104] The processing arrangement 3 of FIG. 3 differs from the processing arrangement 3 shown in FIG. 2 inter alia in that the first calculation block 6 comprises a multiplier, which is configured to multiply the first factor A with the digital input value IN and to forward the result of this multiplication as first output value y1.

[0105] Besides, the second calculation block 7 comprises a first left shift operator 16, which is configured to shift, based on the size IN_SIZE of the digital input value IN, the digital input value IN two-bit-wise to the side of the Most Significant Bit, MSB. The second calculation block 7 further comprises a second left shift operator 17, which is configured to shift, based on the size IN_SIZE of the digital input value IN, the second subtrahend D two-bit-wise to the MSB side. This means that the number of two-bit-wise left shift operations depends on the size IN_SIZE of the digital input value IN.

[0106] In case that the digital input value IN and the second subtrahend D is shifted, the sum operator 8 is configured to subtract the shifted second subtrahend D from the shifted digital input value IN and to forward the result of this subtraction as a digital input word INW. Therefore, the sum operator 8 is connected at its input side to the first left shift operator 16 and to the second left shift operator 17.

[0107] In the embodiment shown in FIG. 3 the second factor C is provided as a mantissa term C_val and an exponential term C_exp. The multiplier 11 of the second calculation block 7 is configured to multiply the mantissa term C_val with the digital output word OUTW, which has been determined from the digital input word INW by the square root operator 10. Besides, the result of this multiplication is forwarded as digital intermediate value IMD1.

[0108] The second calculation block 7 further comprises a back shifting operator 18, which determines, based on the size IN_SIZE of the digital input value IN, how many bit-wise right shift operations are required for the digital output word OUTW in order to compensate the two-bit-wise left shift operations of the digital input word INW. The number of bit-wise right shift operations may equal the number of two-bit-wise left shift operations in order to compensate the left shift operations.

[0109] The result of the determining by the back shifting operator 18 is added to the exponent of the exponential term C_exp in a third sum operator 19. The second calculation block 7 further comprises a right shift operator 20, which is configured to shift the digital intermediate value IMD1 to the side of the Least Significant Bit, LSB, by a certain number of bits. The number of bit-wise right shift operations is based on the result of the summation performed by the third sum operator 19. The right shift operator 20 forwards the shifted digital intermediate value IMD1′.

[0110] The shifted digital intermediate value IMD1′ is forwarded to the second sum operator 12, which is configured to subtract the first subtrahend B from the shifted digital intermediate value IMD1′ and to forward the result of this subtraction as further digital intermediate value IMD2.

[0111] The embodiment shown in FIG. 3 further comprises a noise injection operator 21, which is connected at its input side to the second sum operator 12. The noise injection operator 21 is configured to add a random value NC to the LSB side of the further digital intermediate value IMD2. The noise injection operator forwards a second further intermediate value IMD3 as result of this operation.

[0112] The embodiment of FIG. 3 further comprises a rounding operator 22, which is connected at its input side to the noise injection operator 21. The rounding operator 22 is configured to round the second further digital intermediate value IMD3 up to a predetermined accuracy. The rounding operator 22 forwards a third further intermediate value IMD4 as result of this operation.

[0113] The embodiment of FIG. 3 further comprises a clipping operator 23 which is connected at its input side to the rounding operator 22. The clipping operator 23 is configured to clip the third further digital intermediate value IMD4 in case it exceeds the maximum digital output value YMAX. For that, the clipping operator 23 compares the size of the third further digital intermediate value IMD4 with the maximum digital output value YMAX. The clipping operator 23 forwards the second output value y2 as result of this operation to the output 5 of the processing arrangement 3.

[0114] In the embodiment of FIG. 3 the processing arrangement 3 further comprises a bypass operator 24 configured to control whether the digital output value OUT is determined by one of the first and the second output values y1, y2, based on the selection made by the selector 14, or by the unchanged digital input value IN. If a bypass control variable BP is activated, the bypass operator 24 assigns the digital input value IN to the digital output value OUT, independently from the selection made by the selector 14. Otherwise, the selection made by the selector 14, i.e. the first output value y1 or the second output value y2, is assigned to the digital output value OUT.

[0115] FIG. 4 shows an embodiment of the square root operator 10. The square root operator 10 comprises a cascade of circuits 25, 26, 27. The cascade of circuits 25, 26, 27 comprises a first circuit 25, further circuits 26 and a last circuit 27. The cascade of circuits 25, 26, 27 is configured to determine the digital output word OUTW forming the square root of the digital input word INW. Each circuit 25, 26, 27 of the cascade of circuits comprises a first input 28 for receiving a portion of the digital input word INW of two bits. The digital input word INW comprises 2n bits, where n is a natural number. Therefore, the digital input word INW comprises an even number of bits. The first circuit 25 receives the first two bits INW(2n-1:2n-2) on the MSB side of the digital input word INW. The next further circuit 26 receives the next two bits INW(2n-3:2n-4) on the MSB side of the digital input word INW. This procedure is continued until the last circuit 27 receives the last two bits INW(1:0) on the LSB side of the digital input word INW. Therefore, the cascade of circuits 25, 25, 27 comprises n circuits.

[0116] Further circuits 26 are indicated in FIG. 4 by an ellipsis and an exemplary k.sup.th circuit 26, where k is another natural number.

[0117] Each circuit 25, 26, 27 of the cascade of circuits further comprises a first output 29 for forwarding of at least a portion of the digital output word OUTW as a temporary calculation result R. The first output 29 of the last circuit 27 forwards the output word OUTW.

[0118] Each circuit 26, 27, 28 further comprises a second input 30 for receiving a temporary calculation rest T. Each circuit 26, 27 except the first circuit 25 receives the temporary calculation rest T from a preceding circuit 25, 26. The first circuit 25 receives a logical “0” at the second input 30.

[0119] Each circuit 26, 27 except the first circuit 25 comprises a third input 31 for receiving the temporary calculation result R from the first output 29 of the preceding circuit 25, 26.

[0120] Each circuit 25, 26 except the last circuit 27 comprises a second output 32 for forwarding the temporary calculation rest T to the second input 30 of a subsequent circuit 26, 27.

[0121] The second output 32 of the circuit 25, 26 is therefore connected to the second input 30 of a subsequent circuit 26, 27 via a data path. The first output 29 of the circuit 25, 26 is connected to the third input 31 of a subsequent circuit 26, 27 via a further data path. The number of bits of the temporary calculation rest T transmitted by the data path increases by one bit after each circuit 25, 26. For example, the temporary calculation rest T comprises two bits after the first circuit 25 and three bits after the next further circuit 26. The number of bits of the temporary calculation result R transmitted by the further data path also increases by one bit after each circuit 25, 26, 27. For example, the temporary calculation result R comprises one bit after the first circuit 25, two bits after the next further circuit 26 and reaches n bits after the last circuit 27, as shown in FIG. 4.

[0122] In FIG. 5 the k.sup.th circuit 26 of the cascade is shown in detail. The circuit 26 further comprises a logic block 33, which is configured to determine an output bit O of the digital output word OUTW and the temporary calculation rest T.

[0123] The logic block 33 comprises a first concatenator 34 connected to the first input 28 and the second input 30. The first concatenator 34 concatenates the respective two bits INW(2*(n-k+1)-1:2*(n-k+1)-2) of the digital input word INW to the temporary calculation rest T of the preceding circuit 26. This means that the temporary calculation rest T is updated by shifting the temporary calculation rest T two bits to the MSB side and replacing the newly added bits on the LSB side by the two bits INW(2*(n-k+1)-1:2*(n-k+1)-2).

[0124] The logic block 33 further comprises a multiplier 35 connected to the third input 31 and a first sum operator 36 connected to the multiplier 35 for calculating an internal calculation error Y. The internal calculation error Y is defined by Y = 4.square-solid.R + 1. The multiplication with the factor 4 may be done by two bit-wise left shift operations.

[0125] The logic block 33 further comprises a comparator 37 which receives the updated temporary calculation rest T and the internal calculation error Y. The comparator 37 compares the updated temporary calculation rest T and the internal calculation error Y. If the internal calculation error Y is larger than the updated temporary calculation rest T the comparator 37 outputs a logical “0” as the output bit O. Otherwise the comparator 37 outputs a logical “1” as the output bit O.

[0126] The logic block 33 further comprises a second concatenator 38, which is connected to the output of the comparator 37 and the third input 31. The second concatenator 38 concatenates the output bit O to the temporary calculation result R of the preceding circuit 26. This means that the temporary calculation result R is updated by shifting the temporary calculation result R one bit to the MSB side and replacing the newly added bit on the LSB side by the output bit O. The result of this operation is forwarded as updated temporary result R to the first output 29 of the circuit 26.

[0127] The logic block 33 further comprises a multiplexer 39 receiving the output bit O and the internal calculation error Y. Only if the output bit O is “1”, the internal calculation error Y is forwarded to a second sum operator 40, where the internal calculation error Y is subtracted from the temporary calculation rest T to form an updated temporary calculation rest T. Otherwise, if the output bit O is “0”, the output bit O is forwarded to the second sum operator 40, which means that the temporary calculation rest T remains unchanged. The result of this operation is forwarded as updated temporary rest T to the second output 32 of the circuit 26.

[0128] FIG. 6 shows an example of the functional principle of the square root operator 10 or of the calculation method as described above. In the example, the square root of the digital input word “01010001”, which corresponds to the number 81 in the decimal system, is calculated. Since the digital input word comprises 8 = 4 x 2 bits, the calculation can be performed by four calculation steps (or by a cascade of four circuits 25, 26, 27, respectively). The four calculations steps are indicated in FIG. 6 by the reference numerals 41, 42, 43, 44. Intermediate results for the temporary calculation rest T, the internal calculation error Y, the output bit O and the temporary calculation result R of those calculation steps are also shown in FIG. 6.

[0129] At the beginning of the calculation the temporary calculation rest T and the temporary calculation result R are set to zero, T = “0”, R = “0”.

[0130] The calculation starts by assigning the first two bits “01” of the digital input word INW to the first calculation step 41 by concatenating them to the present temporary calculation rest T. Hereby, the temporary calculation rest T becomes T = “001”. The internal calculation error Y can be determined to be Y = 4.square-solid.R + 1, so that Y = “1”. Since the internal calculation error Y is less than or equal to the temporary calculation rest T, Y ≤ T, an output bit O = “1” is generated and concatenated to the temporary calculation result R, which becomes “1”. The temporary calculation rest T is updated by subtracting the internal calculation error Y, so that T = “00”.

[0131] In the second calculation step 42 the next two bits “01” of the digital input word INW are concatenated to the present temporary calculation rest T. Hereby, the temporary calculation rest T becomes T = “0001”. The internal calculation error Y can be determined to be Y = “0101”, which is larger than the temporary calculation rest T. Therefore, an output bit O = “0” is generated and concatenated to the temporary calculation result R, which becomes “10”. The temporary calculation rest T is updated by subtracting the output bit O, so that it becomes T = “001”.

[0132] In the third calculation step 43 the next two bits “00” of the digital input word INW are concatenated to the present temporary calculation rest T. Hereby, the temporary calculation rest T becomes T = “00100”. The internal calculation error Y can be determined to be Y = “01001”, which is larger than the temporary calculation rest T. Therefore, an output bit O = “0” is generated and concatenated to the temporary calculation result R, which becomes “100”. The temporary calculation rest T is updated by subtracting the output bit O, so that it becomes T = “0100”.

[0133] In the fourth calculation step 44 the next two bits “01” of the digital input word INW are concatenated to the present temporary calculation rest T. Hereby, the temporary calculation rest T becomes T = “010001”. The internal calculation error Y can be determined to be Y = “010001”, which equals the temporary calculation rest T. Therefore, an output bit O = “1” is generated and concatenated to the temporary calculation result R, which becomes “1001”. The temporary calculation rest T is updated by subtracting the internal calculation error Y, so that T = “0”. This means that no rest is remaining. The temporary calculation result R is the digital output word OUTW = “1001”, which corresponds to the number 9 in the decimal system.

[0134] FIG. 7 shows an image sensor 45 comprising the processing arrangement 3. The image sensor also comprises a plurality of pixels 46. The pixels are configured to receive electromagnetic radiation and to generate an analog signal 47 as response to the electromagnetic radiation. The analog signals 47 may be converted, in particular in a serial fashion, by an analog-to-digital converter 48 into digital input values IN. The processing arrangement 3 receives the digital input values IN. Furthermore, the processing arrangement 3 converts each digital input value IN into a digital output value OUT in the described way. The image sensor 45 may comprise further components, for example an image processor, which is not shown in FIG. 7. The digital output value OUT can be further processed by the image processor.

[0135] The embodiments of the processing arrangement 3 and the calculation method disclosed herein have been discussed for the purpose of familiarizing the reader with novel aspects of the idea. Although preferred embodiments have been shown and described, many changes, modifications, equivalents and substitutions of the disclosed concepts may be made by one having skill in the art without unnecessarily departing from the scope of the claims.

[0136] It will be appreciated that the disclosure is not limited to the disclosed embodiments and to what has been particularly shown and described hereinabove. Rather, features recited in separate dependent claims or in the description may advantageously be combined. Furthermore, the scope of the disclosure includes those variations and modifications, which will be apparent to those skilled in the art and fall within the scope of the appended claims.

[0137] The term “comprising”, insofar it was used in the claims or in the description, does not exclude other elements or steps of a corresponding feature or procedure. In case that the terms “a” or “an” were used in conjunction with features, they do not exclude a plurality of such features. Moreover, any reference signs in the claims should not be construed as limiting the scope.

[0138] This patent application claims the priority of the European patent application 20182937.1, the disclosure content of which is hereby incorporated by reference.

TABLE-US-00001 LIST OF REFERENCE NUMERALS 1 linear function 2 square root function 3 processing arrangement 4 input of processing arrangement 5 output of processing arrangement 6 first calculation block 7 second calculation block 8 first sum operator 9 first tester 10 square root operator 11 multiplier of second calculation block 12 second sum operator 13 second tester 14 selector 15 multiplier of first calculation block 16 first left shift operator 17 second left shift operator 18 back shifting operator 19 third sum operator 20 right shift operator 21 noise injection operator 22 rounding operator 23 clipping operator 24 bypass operator 25 first circuit of cascade of circuits 26 further circuit within the cascade of circuits 27 last circuit of cascade of circuits 28 first input of circuit 29 first output of circuit 30 second input of circuit 31 third input of circuit 32 second output of circuit 33 logic block 34 first concatenator 35 multiplier of logic block 36 first sum operator of logic block 37 comparator 38 second concatenator 39 multiplexer 40 second sum operator of logic block 41 first calculation step 42 second calculation step 43 third calculation step 44 fourth calculation step 45 image sensor 46 pixels 47 analog signal 48 analog-to-digital converter A first factor B first subtrahend BP bypass control variable C second factor D second subtrahend IMD1 digital intermediate value IMD1′ shifted digital intermediate value IMD2 further digital intermediate value IMD3 second further digital intermediate value IMD4 third further digital intermediate value IN digital input value INW digital input word IN_SIZE size of digital input value NC random value n, k natural numbers ◯ output bit OUT digital output value OUTW digital output word XLIN threshold value XMAX maximum digital input value y1 first output value y2 second output value YMAX maximum digital output value