A DIGITAL COMPARATOR FOR A LOW DROPOUT (LDO) REGULATOR

Abstract

This disclosure relates to a digital comparator coupled to a pair of pull-up resistors and a pair of pull-down resistors whereby both pairs of resistors are coupled to an output terminal of a low dropout (LDO) regulator. In particular, the digital comparator comprises an edge detector module, a consecutive two-edge detector module and a consecutive three-edge detector module whereby the edge detector module is configured to receive two clock signals as inputs and after being processed by these three modules, to pull-up or pull-down the resistors at the output terminal of the LDO regulator based on the rising and falling edges of the received clock signals.

Claims

1. A digital comparator coupled to a pair of pull-up resistors and a pair of pull-down resistors whereby both pairs of resistors are coupled to a gate terminal of an output stage, the digital comparator comprising: a single-edge detector stage configured to detect a first rising edge in a received first digital signal, and to detect a first falling edge in a received second digital signal, whereby when the first rising edge is detected and when the first falling edge is not simultaneously detected, a detector node is set to a low voltage level, and when the first falling edge is detected, the detector node is set to a high voltage level; a consecutive two-edge detector stage coupled to the single-edge detector stage, the consecutive two-edge detector stage configured to detect the voltage level of the detector node, a consecutive second rising edge in the received first digital signal and a consecutive second falling edge in the received second digital signal, whereby when the consecutive second rising edge is detected and when the voltage level of the detector node is simultaneously detected to be at a low voltage level, the consecutive two-edge detector stage causes one of the pair of pull-up resistors to pull up a voltage at the gate terminal, and when the consecutive second falling edge is detected and when the voltage level of the detector node is simultaneously detected to be at a high voltage level, the consecutive two-edge detector stage causes one of the pair of pull-down resistors to pull down the voltage at the gate terminal; a consecutive three-edge detector stage coupled to the single-edge and the consecutive two-edge detector stages, the consecutive three-edge detector stage configured to detect the voltage level of the detector node, a consecutive third rising edge in the received first digital signal and a consecutive third falling edge in the received second digital signal, whereby when the consecutive third rising edge is detected and when the voltage level of the detector node is simultaneously detected to be at a low voltage level, the consecutive three-edge detector stage causes the other one of the pair of pull-up resistors to pull up the voltage at the gate terminal, and when the consecutive third falling edge is detected and when the voltage level of the detector node is simultaneously detected to be at a high voltage level, the consecutive three-edge detector stage causes the other one of the pair of pull-down resistors to pull down the voltage at the gate terminal.

2. The digital comparator according to claim 1, whereby when the consecutive two-edge detector stage and the consecutive three-edge detector stage detects a high voltage level at the detector node, the consecutive two-edge and three-edge detector stages cause the pair of pull-up resistors to be disabled.

3. The digital comparator according to claim 1, whereby when the consecutive two-edge detector stage and the consecutive three-edge detector stage detects a low voltage level at the detector node, the consecutive two-edge and three-edge detector stages cause the pair of pull-down resistors to be disabled.

4. The digital comparator according to claim 1, wherein level shifters are provided at inputs of the single-edge detector stage, at outputs of the consecutive two-edge detector stage and the consecutive three-edge detector stage.

5. A digital low-dropout circuit having the digital comparator according to claim 1, the digital low-dropout circuit using the output stage to generate a stable output voltage, the circuit comprising: a first inverter ring oscillator that is controllable by an output voltage of the output stage to generate the first digital signal; and a second inverter ring oscillator that is controllable by a reference voltage to generate the second digital signal.

6. The digital low-dropout circuit according to claim 5 wherein a sub-digital comparator is provided to control a pseudo-voltage of the digital comparator.

7. The digital low-dropout circuit according to claim 6 whereby the sub-digital comparator comprises: a differential amplifier having a first input coupled to a voltage divider and a second input coupled to a third inverter ring oscillator that is controllable by the reference voltage.

8. The digital low-dropout circuit according to claim 5 wherein a Miller capacitor is provided between the gate terminal and an output node of the output stage.

9. The digital low-dropout circuit according to claim 5 wherein a feed-forward capacitor is provided between an output node of the output stage and the input of the second inverter ring oscillator.

10. A method of controlling a digital comparator that is coupled to a pair of pull-up resistors and a pair of pull-down resistors whereby both pairs of resistors are coupled to a gate terminal of an output stage, the method comprising: detecting, using a single-edge detector stage, a first rising edge in a received first digital signal, and a first falling edge in a received second digital signal, whereby when the first rising edge is detected and when the first falling edge is not simultaneously detected, setting a detector node to a low voltage level, and when the first falling edge is detected, setting the detector node to a high voltage level; detecting, using a consecutive two-edge detector stage coupled to the single-edge detector stage, the voltage level of the detector node, a consecutive second rising edge in the received first digital signal and a consecutive second falling edge in the received second digital signal, whereby when the consecutive second rising edge is detected and when the voltage level of the detector node is simultaneously detected to be at a low voltage level, causing one of the pair of pull-up resistors to pull up a voltage at the gate terminal, and when the consecutive second falling edge is detected and when the voltage level of the detector node is simultaneously detected to be at a high voltage level, causing one of the pair of pull-down resistors to pull down the voltage at the gate terminal; detecting, a consecutive three-edge detector stage coupled to the single-edge and the consecutive two-edge detector stages, the voltage level of the detector node, a consecutive third rising edge in the received first digital signal and a consecutive third falling edge in the received second digital signal, whereby when the consecutive third rising edge is detected and when the voltage level of the detector node is simultaneously detected to be at a low voltage level, causing the other one of the pair of pull-up resistors to pull up the voltage at the gate terminal, and when the consecutive third falling edge is detected and when the voltage level of the detector node is simultaneously detected to be at a high voltage level, causing the other one of the pair of pull-down resistors to pull down the voltage at the gate terminal.

11. The method according to claim 10, whereby when the consecutive two-edge detector stage and the consecutive three-edge detector stage detects a high voltage level at the detector node, the method comprises the step of causing the pair of pull-up resistors to be disabled.

12. The method according to claim 10, whereby when the consecutive two-edge detector stage and the consecutive three-edge detector stage detects a low voltage level at the detector node, the method comprises the step of causing the pair of pull-down resistors to be disabled.

13. The method according to claim 10, wherein level shifters are provided at inputs of the single-edge detector stage, at outputs of the consecutive two-edge detector and at outputs of the consecutive three-edge detector stage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above advantages and features in accordance with this invention are described in the following detailed description and are shown in the following drawings:

[0026] FIG. 1 illustrating a block diagram of modules contained within a digital frequency comparator in accordance with embodiments of the invention;

[0027] FIG. 2 illustrating circuit diagrams of modules contained within a digital frequency comparator in accordance with embodiments of the invention;

[0028] FIG. 3 illustrating a timing diagram of the digital frequency comparator illustrated in FIG. 2 in accordance with embodiments of the invention whereby the timing diagram illustrates the pulling up of a pair of pull-up resistors;

[0029] FIG. 4 illustrating a timing diagram of the digital frequency comparator illustrated in FIG. 2 at step 301 of the timing diagram in FIG. 3 in accordance with embodiments of the invention;

[0030] FIG. 5 illustrating a timing diagram of the digital frequency comparator illustrated in FIG. 2 at step 302 of the timing diagram in FIG. 3 in accordance with embodiments of the invention;

[0031] FIG. 6 illustrating a timing diagram of the digital frequency comparator illustrated in FIG. 2 at step 302a of the timing diagram in FIG. 3 in accordance with embodiments of the invention;

[0032] FIG. 7 illustrating a timing diagram of the digital frequency comparator illustrated in FIG. 2 at step 303 of the timing diagram in FIG. 3 in accordance with embodiments of the invention;

[0033] FIG. 8 illustrating a timing diagram of the digital frequency comparator illustrated in FIG. 2 at step 303a of the timing diagram in FIG. 3 in accordance with embodiments of the invention;

[0034] FIG. 9 illustrating a timing diagram of the digital frequency comparator illustrated in FIG. 2 at step 304 of the timing diagram in FIG. 3 in accordance with embodiments of the invention;

[0035] FIG. 10 illustrating a timing diagram of the digital frequency comparator illustrated in FIG. 2 at step 305 of the timing diagram in FIG. 3 in accordance with embodiments of the invention;

[0036] FIG. 11 illustrating a timing diagram of the digital frequency comparator illustrated in FIG. 2 in accordance with embodiments of the invention whereby the timing diagram illustrates the pulling down of a pair of pull-down resistors;

[0037] FIG. 12 illustrating a timing diagram of the digital frequency comparator illustrated in FIG. 2 at step 1101 of the timing diagram in FIG. 11 in accordance with embodiments of the invention;

[0038] FIG. 13 illustrating a timing diagram of the digital frequency comparator illustrated in FIG. 2 at step 1102 of the timing diagram in FIG. 11 in accordance with embodiments of the invention;

[0039] FIG. 14 illustrating a timing diagram of the digital frequency comparator illustrated in FIG. 2 at step 1103 of the timing diagram in FIG. 11 in accordance with embodiments of the invention;

[0040] FIG. 15 illustrating a timing diagram of the digital frequency comparator illustrated in FIG. 2 at step 1103a of the timing diagram in FIG. 11 in accordance with embodiments of the invention;

[0041] FIG. 16 illustrating a timing diagram of the digital frequency comparator illustrated in FIG. 2 at step 1103b of the timing diagram in FIG. 11 in accordance with embodiments of the invention;

[0042] FIG. 17 illustrating a timing diagram of the digital frequency comparator illustrated in FIG. 2 at step 1104 of the timing diagram in FIG. 11 in accordance with embodiments of the invention;

[0043] FIG. 18 illustrating a timing diagram of the digital frequency comparator illustrated in FIG. 2 at step 1105 of the timing diagram in FIG. 11 in accordance with embodiments of the invention;

[0044] FIG. 19 illustrating circuit diagram of an LDO regulator in accordance with embodiments of the invention;

[0045] FIG. 20 illustrating the current consumption of the digital comparator illustrated in FIG. 2 in accordance with embodiments of the invention;

[0046] FIG. 21 illustrating the timing diagram of an LDO regulator in accordance with embodiments of the invention;

[0047] FIG. 22 illustrating the performance of the LDO regulator in accordance with embodiments of the invention; and

[0048] FIGS. 23A, 23B and 23C illustrating the transient response of the LDO regulator in accordance with embodiments of the invention.

DETAILED DESCRIPTION

[0049] This invention relates to a digital comparator coupled to a pair of pull-up resistors and a pair of pull-down resistors whereby both pairs of resistors are coupled to an output terminal of a low dropout (LDO) regulator. In particular, the digital frequency comparator comprises an edge detector module, a consecutive two-edge detector module and a consecutive three-edge detector module whereby the edge detector module is configured to receive two clock signals as inputs. These received signals, after being processed by these three modules, then cause the respective resistors of the LDO regulator to be pulled-up or pulled-down based on the rising and falling edges of the received clock signals.

[0050] A block diagram of a digital comparator in accordance with embodiments of the invention is illustrated in FIG. 1. Digital comparator 100 comprises an edge detector stage 105, a consecutive two-edge detector stage 110 and a consecutive three-edge detector stage 115. Edge detector stage 105 is configured to receive a first digital signal F.sub.U and a second digital signal F.sub.D whereby in embodiments of the invention, edge detector stage 105 is further configured to detect a rising edge in the first digital signal F.sub.U and to detect a falling edge in the second digital signal F.sub.D. When rising or falling edges are detected in either or both signals, edge detector stage 105 then causes a voltage level at its output node D.sub.U to change accordingly.

[0051] The first and second digital signals F.sub.U and F.sub.D, and the output node D.sub.U are coupled to the input of two-edge detector stage 110 such that the two-edge detector stage 110 is configured to cause voltage levels at its output nodes clk.sub.U1 and clk.sub.D1 to change accordingly when another consecutive rising edge in the first digital signal F.sub.U is detected and/or when another consecutive falling edge in the second digital signal F.sub.D is detected.

[0052] The first and second digital signals F.sub.U and F.sub.D, and the output node D.sub.U are also coupled to the input of three-edge detector stage 115 such that the three-edge detector stage 115 is configured to cause voltage levels at its output nodes clk.sub.U2 and clk.sub.D2 to change accordingly when a third consecutive rising edge in the first digital signal F.sub.U is detected and/or when a third consecutive falling edge in the second digital signal F.sub.D is detected.

[0053] In accordance with embodiments of the invention, but not limited to this embodiment, the outputs from the two-edge detector stage 110 and the three-edge detector stage 115 may then be coupled to a pair of pull-up and to a pair pull-down resistors accordingly to control the “pull” timings of these resistors.

[0054] FIG. 2 illustrates the circuit diagrams of the edge detector stage 105, the consecutive two-edge detector stage 110 and the consecutive three-edge detector stage 115 whereby the outputs U.sub.C, U.sub.E, D.sub.C and D.sub.E of digital comparator 100 are provided to output stage 250 after the output signals U.sub.C, U.sub.E, D.sub.C and D.sub.E have been delayed and level-shifted to appropriate levels clk.sub.U1, clk.sub.U2, clk.sub.D1 and clk.sub.D2 to control switches 221, 222, 231 and 232 respectively. Transistors in each of these stages are coupled to either voltage supply V.sub.supply or pseudo-voltage VSS.sub.pseudo whereby the voltage level of VSS.sub.pseudo is understood to be lower than the voltage level of V.sub.supply whereby in embodiments of the invention, the voltage drop between VSS.sub.pseudo and V.sub.supply is about 0.8 Volts.

[0055] When switches 221 and 222 switch on, they cause pull-up resistors R.sub.U1 and R.sub.U2 to pull the gate voltage V.sub.gate of power amplifier 235 up, and when switches 231 and 232 switch on, they cause pull-down resistors R.sub.D1 and R.sub.D2 to pull the gate voltage V.sub.gate of power amplifier 235 down. By doing this, the digital comparator 100 is able to control the output voltage at the LDO_out node by controlling the timings of pull-up resistors R.sub.U1 and R.sub.U2 through switches 221 and 22 and the timings of pull-down resistors R.sub.D1 and R.sub.D2 through switches 231 and 232.

[0056] As illustrated in FIG. 2, edge detector stage 105 comprises sub-circuit 205a for receiving the first digital signal F.sub.U and sub-circuit 205b for receiving the second digital signal F.sub.D.

[0057] In embodiments of the invention, sub-circuits 205a, 210a and 215a were configured to detect rising edges in the first digital signal F.sub.U. As such, sub-circuit 205a comprises a plurality of logic NOT gates (or inverters) and at least two N-type Metal-Oxide-Semiconductor (NMOS) transistors, M.sub.NU1 and M.sub.NU2, that are connected in series whereby a source terminal of NMOS transistor M.sub.NU1 is connected to a supply voltage VSS.sub.pseudo, and a drain terminal of NMOS transistor M.sub.NU2 is connected to a detector node D.sub.U. The logic NOT gates are configured such that when the first digital signal F.sub.U is provided to sub-circuit 205a, the first digital signal is delayed and inverted by the NOT gates thereby producing delayed-first digital signal FP.sub.U. As can be seen, sub-circuit 205a is configured such that the first digital signal F.sub.U is provided directly to NMOS transistor M.sub.NU1 while the delayed-first digital signal FP.sub.U is provided to NMOS transistor M.sub.NU2.

[0058] Consecutive two-edge detector stage 110 comprises sub-circuit 210a for receiving the first digital signal F.sub.U, the delayed-first digital signal FP.sub.U and the detector node voltage D.sub.U. In particular, as illustrated in FIG. 2, sub-circuit 210a comprises at least three NMOS transistors, M.sub.NU4, M.sub.NU5 and M.sub.NU6 that are connected in series whereby the output node U.sub.C is provided at the drain terminal of the NMOS transistor M.sub.NU4, at least two P-type Metal-Oxide-Semiconductor (PMOS) transistors, M.sub.PU1 and M.sub.PU2, that are connected in series, a NMOS transistor M.sub.NU3 whose gate is switched by the voltage at the detector node D.sub.U and has as its drain terminal output node U.sub.B and a PMOS transistor M.sub.PU3 whose gate is coupled to output node U.sub.B and drain is coupled to output node U.sub.C. As can be seen, sub-circuit 210a is configured such that the first digital signal F.sub.U is provided directly to NMOS transistor M.sub.NU6 and PMOS transistor M.sub.PU1, the delayed-first digital signal FP.sub.U is provided to NMOS transistor M.sub.NU5, and the voltage at the detector node D.sub.U is provided to PMOS transistor M.sub.PU2 and NMOS transistor M.sub.NU3.

[0059] As for consecutive three-edge detector stage 115, this stage comprises sub-circuit 215a for receiving first digital signal F.sub.U, the delayed-first digital signal FP.sub.U and the voltage at node U.sub.C. In particular, as illustrated in FIG. 2, sub-circuit 215a comprises at least two NMOS transistors, M.sub.NU9 and M.sub.NU10 that are connected in series, at least two PMOS transistors, M.sub.PU4 and M.sub.PU5, that are connected in series, NMOS transistors M.sub.NU7 and M.sub.NU8 whereby the drain terminal of the NMOS transistor M.sub.NU7 (whose gate is switched by the voltage at output node U.sub.C) has as its drain terminal output node U.sub.D and the drain terminal of the NMOS transistor M.sub.NU8 (whose gate is switched by the voltage at output node U.sub.D) has as its drain terminal output node U.sub.E. As can be seen, sub-circuit 215a is configured such that the first digital signal F.sub.U is provided directly to NMOS transistor M.sub.NU10 and PMOS transistor M.sub.PU5, the delayed-first digital signal FP.sub.U is provided to NMOS transistor M.sub.NU9, and the voltage at the output node U.sub.C is provided to PMOS transistor M.sub.PU4 and NMOS transistor M.sub.NU7.

[0060] Hence, it can be said that when a first digital signal F.sub.U is provided to sub-circuits 205a, 210a and 215a, the output from these sub-circuits may be obtained from output nodes U.sub.E and U.sub.C.

[0061] Sub-circuits 205b, 210b and 215b comprise of an almost similar configuration as that of sub-circuits 205a, 210a and 215a respectively. However, as sub-circuits 205b, 210b and 215b were configured to detect a falling edge in the second digital signal F.sub.D, the type of the transistors used in 205b, 210b and 215b differs from that of sub-circuits 205a, 210a and 215a.

[0062] In particular, sub-circuit 205b similarly comprises a plurality of logic NOT gates (or inverters) and at least two PMOS transistors, M.sub.PD1 and M.sub.PD2, that are connected in series whereby a source terminal of PMOS transistor M.sub.PD1 is connected to a supply voltage V.sub.Supply, and a drain terminal of PMOS transistor M.sub.PD2 is connected to the detector node D.sub.U. The logic NOT gates are configured such that when the second digital signal F.sub.D is provided to sub-circuit 205b, the second digital signal is delayed and inverted by the NOT gates thereby producing delayed-second digital signal FP.sub.D. As can be seen, sub-circuit 205b is configured such that the second digital signal F.sub.D is provided directly to PMOS transistor M.sub.PD1 while the delayed-second digital signal FP.sub.D is provided to PMOS transistor M.sub.PD2.

[0063] Sub-circuit 210b is then configured to receive the second digital signal F.sub.D, the delayed-second digital signal FP.sub.D and the detector node voltage D.sub.U. In particular, as illustrated in FIG. 2, sub-circuit 210b comprises at least three PMOS transistors, M.sub.PD4, M.sub.PD5 and M.sub.PD6 that are connected in series whereby the output node D.sub.C is provided at the drain terminal of the PMOS transistor M.sub.PD6, at least two NMOS transistors, M.sub.ND1 and M.sub.ND2, that are connected in series, a PMOS transistor M.sub.PD3 whose gate is switched by the voltage at the detector node D.sub.U and has as its drain terminal output node D.sub.B and a NMOS transistor M.sub.ND3 whose gate is coupled to output node D.sub.B and drain is coupled to output node D.sub.C. As can be seen, sub-circuit 210b is configured such that the second digital signal F.sub.D is provided directly to PMOS transistor M.sub.PD4 and NMOS transistor M.sub.ND2, the delayed-second digital signal FP.sub.D is provided to PMOS transistor M.sub.PD5, and the voltage at the detector node D.sub.U is provided to PMOS transistor M.sub.PD3 and NMOS transistor M.sub.ND1.

[0064] As for sub-circuit 215b, this circuit is configured to receive second digital signal F.sub.D, the delayed-second digital signal FP.sub.D and the voltage at node D.sub.C. In particular, as illustrated in FIG. 2, sub-circuit 215b comprises at least two PMOS transistors, M.sub.PD9 and M.sub.PD10 that are connected in series, at least two NMOS transistors, M.sub.ND4 and M.sub.ND5, that are connected in series, PMOS transistors M.sub.PD7 and M.sub.PD8 whereby the drain terminal of the PMOS transistor M.sub.PD7 (whose gate is switched by the voltage at output node D.sub.C) has as its drain terminal output node D.sub.D and the drain terminal of the PMOS transistor M.sub.PD8 (whose gate is switched by the voltage at output node D.sub.D) has as its drain terminal output node D.sub.E. As can be seen, sub-circuit 215b is configured such that the second digital signal F.sub.D is provided directly to PMOS transistor M.sub.PD10 and PMOS transistor M.sub.ND5, the delayed-second digital signal FP.sub.D is provided to PMOS transistor M.sub.PD9, and the voltage at the output node D.sub.C is provided to NMOS transistor M.sub.ND4 and PMOS transistor M.sub.PD7.

[0065] Hence, it can be said that when the second digital signal FD is provided to sub-circuits 205b, 210b and 215b, the output from these sub-circuits may be obtained from output nodes D.sub.E and D.sub.C.

[0066] In order to better understand the detailed workings of these sub-circuits, reference is made to the timing diagrams illustrated in FIGS. 3-10. FIG. 3 illustrates the timing diagrams of sub-circuits 205a, 210a and 215a when first and second digital signals F.sub.U and F.sub.D are provided to sub-circuits 205a, 210a and 215a. In particular, this timing diagram provides an overview of the key events/steps 301-305 that occur.

[0067] At step 301, as illustrated in FIG. 4, it can be seen that due to the logic NOT gates in sub-circuit 205a, a delay of period T.sub.2 exists between the first digital signal F.sub.U and the inverted delayed-first digital signal FP.sub.U. Due to this delay, after a rising edge occurs for signal F.sub.U, the signal FP.sub.U only starts falling after the period T.sub.2 has lapsed. During this period T.sub.2, as both signals F.sub.U and FP.sub.U are “high”, this causes NMOS transistors M.sub.NU1 and M.sub.NU2 to switch on and as the second digital signal F.sub.D is “low”, this causes one of PMOS transistors M.sub.PD1 and M.sub.PD2 to switch off. As a result, the voltage at detector node D.sub.U is triggered to become low, i.e. the voltage at detector node D.sub.U is set to VSS.sub.pseudo. It is useful at this stage to recap that the voltage level of VSS.sub.pseudo is understood to be lower than the voltage level of V.sub.supply whereby in embodiments of the invention, the voltage drop between VSS.sub.pseudo and V.sub.supply is about 0.8 Volts.

[0068] At step 302, as illustrated in FIG. 5, it can be seen that due to the logic NOT gates in sub-circuit 205b, a delay of period T.sub.1 similarly exists between the second digital signal F.sub.D and the inverted delayed-first digital signal FP.sub.D. Due to this delay, after a falling edge occurs for signal F.sub.D, the signal FP.sub.D only starts rising after the period T.sub.1 has lapsed. During this period T.sub.1, as both signals F.sub.D and FP.sub.D are “low”, this causes PMOS transistors M.sub.PD1 and M.sub.PD2 to switch on and as the first digital signal F.sub.U is “high”, this causes one of NMOS transistors M.sub.NU1 and M.sub.NU2 to switch off. As a result, the voltage at detector node D.sub.U is triggered to become high, i.e. the voltage at detector node D.sub.U is set to V.sub.supply.

[0069] With reference to FIG. 3, it can be seen that after step 302, the second digital signal F.sub.D does not have another falling edge until step 305. After step 302, a first rising edge 300a occurs at digital signal F.sub.U causing detector node D.sub.U to become low. This in turn switches PMOS transistor M.sub.PU2 on.

[0070] At step 302a, as illustrated in FIG. 6, when signal F.sub.U becomes low and when signal FP.sub.U becomes low for a period of T.sub.2, this causes PMOS transistor M.sub.PU1 to switch on thereby causing a voltage level at node U.sub.B to become high.

[0071] Subsequently, as illustrated in FIG. 7, a second rising edge 300b occurs for digital signal F.sub.U at step 303 whereby for a period of time T.sub.2, signals F.sub.U and FP.sub.U are both high causing the voltage level at node U.sub.C to become low, which in turn after being processed by inverters and a level shifter, causes a voltage level at output node clk.sub.U1 to become low as well.

[0072] As a falling edge is not detected at the second digital signal F.sub.D, when the signal F.sub.U becomes low (and signal FP.sub.U is low as well for a period of time T.sub.2), this causes the voltage at node U.sub.D to become high. This takes place at step 303a as illustrated in FIG. 8.

[0073] Subsequently, as illustrated in FIG. 9, a third rising edge 300c occurs for digital signal F.sub.U at step 304. This causes the voltage level at node U.sub.E to become low as NMOS transistors M.sub.NU8, M.sub.NU9, and M.sub.NU10 are switched on. After the voltage level at node U.sub.E has been processed by inverters and a level shifter, this causes a voltage level at output node clk.sub.U2 to become low as well.

[0074] At step 305, as illustrated in FIG. 10, a falling edge is detected at the second digital signal F.sub.D (and signal FP.sub.D remains low as well for a period of time T.sub.1) and this causes the voltage at detector node D.sub.U to become high. As the voltage at detector node D.sub.U becomes high, it causes the voltage level at node U.sub.B to become low, which in turn triggers the voltage level at node U.sub.C to become high. This then in turn causes the voltage level at U.sub.D to become low and this causes the voltage level at node U.sub.E to become high. As a result, the voltage levels at output nodes clk.sub.U1 and clk.sub.U2 both become high.

[0075] For completeness, the timing diagrams of sub-circuits 205b, 210b and 215b when first and second digital signals F.sub.U and F.sub.D are provided to these sub-circuits will be discussed in FIGS. 11-18. In particular, this timing diagram provides an overview of the key events/steps 1101-1105 that occur in these sub-circuits.

[0076] At step 1101, as illustrated in FIG. 12, a delay of period T.sub.1 exists between the second digital signal F.sub.D and the inverted delayed-second digital signal FP.sub.D. Due to this delay, after a falling edge occurs for signal F.sub.D, the signal FP.sub.D only starts falling after the period T.sub.1 has lapsed. During this period T.sub.1, as both signals F.sub.D and FP.sub.D are “low”, this causes PMOS transistors M.sub.PD1 and M.sub.PD2 to switch on and as the first digital signal F.sub.U is “high”, this causes one of NMOS transistors M.sub.NU1 and M.sub.NU2 to switch off. As a result, the voltage at detector node D.sub.U is triggered to become high.

[0077] At step 1102, as illustrated in FIG. 13, it can be seen that a delay of period T.sub.2 similarly exists between the first digital signal F.sub.U and the inverted delayed-second digital signal FP.sub.U. Due to this delay, after a rising edge occurs for signal F.sub.U, the signal FP.sub.U only starts falling after the period T.sub.2 has lapsed. During this period T.sub.2, as both signals F.sub.U and FP.sub.U are “high”, this causes NMOS transistors M.sub.NU1 and M.sub.NU2 to switch on and as the second digital signal F.sub.D is “low”, this causes one of PMOS transistors M.sub.PD1 and M.sub.PD2 to switch off. As a result, the voltage at detector node D.sub.U is triggered to become low.

[0078] After step 1102, at step 1103, a first falling edge occurs at digital signal F.sub.D causing detector node D.sub.U to become high. This is shown in FIG. 14. This triggering action in turn switches NMOS transistor M.sub.ND1 on.

[0079] At step 1103a, as illustrated in FIG. 15, when signal F.sub.D becomes high and when signal FP.sub.D is high as well for a period of T.sub.1, this causes a voltage level at node D.sub.B to become low.

[0080] Subsequently, at a second falling edge 1501 of digital signal F.sub.D, the voltage level at node D.sub.C becomes high, which in turn after being processed by inverters and a level shifter, causes a voltage level at output node clk.sub.D1 to become high as well.

[0081] As a rising edge is not detected at the first digital signal F.sub.U, when the signal F.sub.D becomes high, this causes the voltage at node D.sub.D to become low. This takes place at step 1103b as illustrated in FIG. 16.

[0082] Subsequently, as illustrated in FIG. 17, a third falling edge 1701 occurs for digital signal F.sub.D at step 1104. This causes the voltage level at node D.sub.E to become high as PMOS transistors M.sub.PD8, M.sub.PD9, and M.sub.PD10 are switched on. After the voltage level at node D.sub.E has been processed by inverters and a level shifter, this causes a voltage level at output node clk.sub.D2 to become high as well.

[0083] At step 1105, as illustrated in FIG. 18, a rising edge is detected at the first digital signal F.sub.U and this causes the voltage at detector node D.sub.U to become low. As the voltage at detector node D.sub.U becomes low, it causes the voltage level at node D.sub.B to become high, which in turn triggers the voltage level at node D.sub.C to become low. This then in turn causes the voltage level at D.sub.D to become high and this causes the voltage level at node D.sub.E to become low. As a result, the voltage levels at output nodes clk.sub.D1 and clk.sub.D2 both become low.

[0084] Hence, as illustrated in the timing diagrams in FIGS. 3-18, sub-circuits 205a/b, 210a/b, and 215a/b may be used to pull up the pair of pull-up resistors R.sub.U1 and R.sub.U2 and to pull down the pair of pull-down resistors R.sub.D1 and R.sub.D2 when certain signals are received by these sub-circuits.

[0085] FIG. 19 illustrates a circuit diagram of hybrid LDO regulator 1900 that includes digital comparator 200, 3-stage inverter ring oscillators (VCOs) VCO.sub.D and VCO.sub.U, a push-pull resistor array 1905, amplifier 220 and VSS.sub.pseudo_bias comparator circuit 1915.

[0086] In embodiments of the invention, the VCOs VCO.sub.D and VCO.sub.U are configured to generate clocks with frequencies that are proportional to the differential voltage inputs. As illustrated in FIG. 19, a pair of common source NMOS transistors, NM.sub.1 and NM.sub.2 are utilized to set the tail currents of two subthreshold inverter ring oscillators, VCO.sub.D and VCO.sub.U. In embodiments of the invention, through simulation, it was found that these VCOs were able to generate 15 MHz oscillating clock signals with oscillating amplitudes between 0.55 V and 0.35 V while drawing only 20 nA of current when a 0.55 V voltage supply was used.

[0087] Two digital clock signals, F.sub.U and F.sub.D, are provided to comparator 200 by VCOs VCO.sub.D and VCO.sub.U, whereby rising/falling edge sequence information of the digital clock signals, F.sub.U and F.sub.D are extracted by comparator 200 and used to control a push-pull resistor array to control the gate voltage of amplifier 220.

[0088] In order to reduce the amount of power consumed by the hybrid-LDO, digital comparator 200's supply voltage VSS.sub.pseudo is controlled by VSS.sub.pseudo_bias comparator circuit 1915 to ensure that sure that digital comparator 200's voltage drop is no more than 3-times (3×) of the mentioned oscillating amplitude, and does not constitute the whole supply. Another ring oscillator, VCO.sub.F, which is identical to VCOs VCO.sub.U and VCO.sub.D, is added to circuit 1915 to provide a reference voltage to differential amplifier AMP.sub.1. Differential amplifier AMP.sub.1 is configured to control NMOS switch NM.sub.VSS such that the current drawn by comparator 200 may be adjusted to ensure that a specific voltage drop exists in comparator 200 between its supply voltage and pseudo supply voltage. When LDO 1900 is in a stable state, digital clock signals F.sub.U and F.sub.D would be almost the same and as a result, LDO 1900 would consume ultra-low power. This means that when LDO 1900 is in a stable state, the push-pull resistor array would be totally OFF and only the differential VCOs and comparator 200 would be active.

[0089] In order to ensure that hybrid-LDO 1900 has a stable transient response or a stable output voltage, the dominant pole at its output is maintained at the gate node of amplifier 220 by a Miller capacitor C.sub.Miller, 1910 (which is connected between the gate node and the output node of amplifier 220). The use of capacitor 1910 also improves the LDO's transient response as changes to its output voltage would be coupled to amplifier 220's gate. For example, when the output voltage of amplifier 220 increases, C.sub.Miller 1910 pulls up the voltage at the V.sub.gate node simultaneously, which in turn reduces the current flowing through amplifier 220. This feedback loop compensates for voltage changes at the output of amplifier 220 and this helps to stabilize the output voltage. To further enhance the transient response of the hybrid-LDO, a feedforward capacitor C.sub.FD 1950 is added to speed up the VCO's frequency response time. When the output voltage of amplifier 220 changes, C.sub.FD 1950 feed forwards the voltage change to VCO.sub.D and causes signal F.sub.D to change accordingly. Without C.sub.FD 1950, the output voltage of amplifier 220 will affect the voltage of V.sub.FB which in turn controls the voltage at VCO.sub.U. When this happens, signal F.sub.U changes accordingly and in general, this takes a much longer time.

[0090] FIG. 20 illustrates a simulated plot of voltage VSS.sub.pseudo and the current consumed by comparator 200 vs. supply voltage V.sub.supply when comparator 200 is used in LDO 1900. It can be seen that the voltage drop between VSS.sub.pseudo and V.sub.supply is about 0.8 V when the supply voltage is more than 0.7 V.

[0091] FIG. 21 shows the simulated waveforms of LDO 1900 from its start up when it's output deviates from a target voltage and the stable mode when the LDO has stabilized and its output is regulated. When V.sub.FB>V.sub.ref, the frequency of signal F.sub.U is higher than the frequency of signal F.sub.D.

[0092] When two consecutive rising edges are detected at signal F.sub.U and when these two rising edges are located in between two F.sub.D falling edges, a pull-up resistor R.sub.U1 that is connected to the gate of the PMOS gate will charge gate's voltage accordingly.

[0093] Further, if three consecutive rising edges are detected at signal F.sub.U, a pull-up resistor R.sub.U2 that is connected to the gate of the PMOS transistor's gate will charge the gate's voltage as well. Hence, when the voltage error at the LDO's output is small, only pull-up resistor R.sub.U1 is required to discretely charge the gate voltage of the PMOS transistor, and the equivalent pole at the PMOS transistor's gate is suppressed at a low frequency. However, if the LDO is in transient response function mode, resistor R.sub.U2 will also be connected to the gate of the PMOS transistor to charge its gate faster in order to reduce the LDO's settling time. In this way, the settling time is shortened and the LDO's stability is maintained.

[0094] When V.sub.FB<V.sub.ref, the frequency of signal F.sub.U is lower than the frequency of signal F.sub.D as such, resistors R.sub.D1 and R.sub.D2 may then be used to pull down the voltage at the PMOS transistor's gate.

[0095] After a certain period of time has lapsed, the LDO's output voltage would have been regulated to the required value, as such, the frequencies of signals F.sub.U and F.sub.D would be almost the same, and output nodes clk.sub.U1/2 and clk.sub.D1/2 would be in their disabled states. Hence, only the VCOs and the digital comparator would be active, and as a result, the LDO consumes very low power.

Experimental Results

[0096] In this experiment, LDO 1900 was fabricated using a 65 nm CMOS process, with 400 nA quiescent current and a 20 pF capacitor. FIG. 22 illustrates the performance of the simulated LDO whereby plot 2205 shows that the output of the LDO remains stable even though the input of the LDO gradually increases and plot 2210 shows that the output of the LDO remains stable even though the input of the LDO gradually decreased.

[0097] FIG. 23 illustrates the measured performance of the LDO's transient response when the current of the LDO l.sub.load is stepped from 0.5 mA to 10.5/20.5/30.5 mA, respectively and back to 0.5 mA with an edging time of 10 ns. As only a 10 pF load capacitor was used, 180/220/250 mV undershoot and 180/270/300 mV overshoot were achieved, respectively. The undershoot and the overshoot settling time was measured to be 0.5 μs and 6 μs, respectively. In particular, FIG. 23A illustrates the transient response of the LDO when the load current shifts between 0.5 mA and 10.5 mA; FIG. 23B illustrates the transient response of the LDO when the load current shifts between 0.5 mA and 20.5 mA; and FIG. 23C illustrates the transient response of the LDO when the load current shifts between 0.5 mA and 30.5 mA.

[0098] The DC characteristics of the LDO are summarized in Table 1 below whereby the line regulation and load regulation were measured to be 2.5 mV/V and 0.5 mV/mA, respectively. When the load current was at 630 nA, a larger than 99.9% current efficiency was achieved in 10mA load regulation current.

TABLE-US-00001 TABLE 1 450 mV Quiescent Load regulation Line regulation output current (0~10 mA) (0.6 V~1.2 V, 10 mA load) TYP, 25 degree 633 nA 500 μV/mA 2.5 mV/V SS, 0 degree 660 nA 470 μV/mA 4.2 mV/V FF, 50 degree 608 nA 1.3 mV/mA 10 mV/V

[0099] The performance of an LDO designed in accordance with embodiments of the invention is compared against other designs known in the art in Table 2 below. Table 2 shows that with 400 nA quiescent current and a 0.5V supply, a 1,000,000× load dynamic range and a 0.004 ps Figure of Merit (FOM) was achievable with the lowest quiescent current, largest load dynamic range and smallest on-chip capacitor compared to other state-of-art digital/hybrid control LDOs. For FOM comparisons, the proposed LDO in 65 nm technology achieved 2 orders of better performance than the LDOs designed using the 40 nm and 65 nm processes and even has a better value than the one designed using the 28 nm process (which is a more matured process and should have power and speed advantages when FOM calculation is performed).

TABLE-US-00002 TABLE 2 [4]   [1] Huang, [5] Salem, [7] Yang, [2] Ma, [3] Kundo, [6] Salem, This work 2017 ISSCC 2017 ISSCC 2017 ISSCC 2017 ISSCC 2018 ISSCC 2018 ISSCC 2018 ISSCC Unit Process 65 nm 40nm 65 nm 65nm 65nm 28 nm 65 nm 65 nm Technology CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS Type Hybrid digital Digital/ digital analog Digital/ digital hybrid hybrid hybrid Clk frequency 15 (internal) N.A. 10 1-240 No 4/1 N.A. Mhz Cap in total 20 20nf 100 400 40 24 40 385 pf Input range 0.5-1.2 0.6-1.1 0.5-1.0 0.5-1.0 0.6 0.4-0.55 0.6-1.2 0.3-0.9 V Output range 0.45-1.15 0.5-1.0 0.45-0.35 0.3-0.45 0.3-0.33 0.35-0.5 0.4-1.1 0.3-0.4 V Load dynamic N.A. 584X 20,000X 332X range 50,000X Max load current 30 210 12 2 50 26 100 1 mA Line regulation 25.8 N.A. N.A. 1.1 N.A. N.A. N.A. N.A. mV/V Load regulation 1.3 <0.075 N.A. 0.65 N.A. N.A. N.A. N.A. mV/V Quinscent Current 0.1 22.6-98.5 1.2 14 32 0.81/0.43 100-1020 48.4 μA Transient response ΔVOUT ® Δ  /edge time Settling time 0.3 1.3 1.7 0.1 15 16 1.13 0.905 FOM 0.39 0.28 305.7 0.34 0.051 1.18 14.3 ps FOM = (I.sub.Q/I.sub.load_max)*(ΔVOUT/ΔI.sub.load )*CAP *Current to resistor divider is 50 nA indicates data missing or illegible when filed

[0100] The above is a description of embodiments of a system and method in accordance with the present invention as set forth in the following claims. It is envisioned that others may and will design alternatives that fall within the scope of the following claims.