Process Method for Improving Reliability of Metal Gate High-Voltage Device

Abstract

The present application provides a process method for improving reliability of a metal gate high-voltage device. Stacks layers formed over the gate oxide layer and spaced apart from each other. An SiCN layer is deposited to cover tops and sidewalls of the stack layers, and cover bottoms of slots between the stack layers. An HARP layer is deposited to covert the SiCN layer. The HARP layer over the stack layers and the slot regions is covered with a photoresist. Photolithography and etching are sequentially performed to open the HARP layer over the stack layers. The photoresist in the slot regions is reserved. The HARP layer over the stack layers outside the slot regions is removed. The operations are repeated for many times until the slot regions are filled with the HARP layer.

Claims

1. A process method for improving reliability of a metal gate high-voltage device, wherein the process method for improving the reliability of the metal gate high-voltage device at least comprises: step 1: providing a semiconductor structure, the semiconductor structure comprising a high-voltage device active area; a gate oxide layer formed over the high-voltage device active area; and stack layers formed over the gate oxide layer and spaced apart from each other, regions between the stack layers being slot regions; step 2: depositing an SiCN layer to cover tops and sidewalls of the stack layers, and cover bottoms of slots between the stack layers; step 3: depositing a high aspect ratio process (HARP) layer to cover the SiCN layer; step 4: covering the HARP layer over the stack layers and the slot regions with a photoresist, sequentially performing photolithography and etching to open the HARP layer over the stack layers, and reserving the photoresist in the slot regions; step 5: removing the HARP layer over the stack layers outside the slot regions; step 6: repeating steps 3 to step 5 for many times until the slot regions are filled with the HARP layer; and step 7: performing etching to remove the SiCN layer over the stack layers.

2. The process method for improving the reliability of the metal gate high-voltage device according to claim 1, wherein in step 1, the stack layers are formed by sequentially stacking at least polysilicon, silicon nitride, and a plasma enhanced oxide (PEOX) layer from bottom to top.

3. The process method for improving the reliability of the metal gate high-voltage device according to claim 1, wherein in step 2, a thickness of the SiCN layer is 90Å.

4. The process method for improving the reliability of the metal gate high-voltage device according to claim 1, wherein in step 2, a method for depositing the SiCN layer is chemical vapor deposition.

5. The process method for improving the reliability of the metal gate high-voltage device according to claim 1, wherein in step 3, a thickness of the deposited HARP layer is 150Å.

6. The process method for improving the reliability of the metal gate high-voltage device according to claim 1, wherein in step 5, a wet etching process is adopted to remove the HARP layer over the stack layers outside the slot regions.

7. The process method for improving the reliability of the metal gate high-voltage device according to claim 6, wherein in step 5, etching solution in the wet etching process is hydrofluoric acid.

8. The process method for improving the reliability of the metal gate high-voltage device according to claim 1, wherein in step 5, a concentration of hydrofluoric acid is 300:1 or 200:1.

9. The process method for improving the reliability of the metal gate high-voltage device according to claim 1, wherein in step 6, step 3 to step 5 are repeated for 1-2 times.

10. The process method for improving the reliability of the metal gate high-voltage device according to claim 1, wherein in step 7, a method for performing etching to remove the SiCN layer is dry etching.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0024] FIG. 1 illustrates a schematic diagram of a semiconductor structure in the present application.

[0025] FIG. 2 illustrates a schematic diagram of a structure after an HARP layer is deposited in the present application.

[0026] FIG. 3 illustrates a schematic diagram of a structure after a photoresist is filled in slots in the present application.

[0027] FIG. 4 illustrates a schematic diagram of a structure after an HARP layer over stack layers outside slot regions is removed in the present application.

[0028] FIG. 5 illustrates a schematic diagram of a structure after slot regions are filled with an HARP layer in the present application.

[0029] FIG. 6 illustrates a schematic diagram of a structure after etching is performed to remove an SiCN layer over stack layers in the present application.

[0030] FIG. 7 illustrates a flowchart of a process method for improving reliability of a metal gate high-voltage device according to the present application.

DETAILED DESCRIPTION OF THE APPLICATION

[0031] The implementation modes of the present application will be described below through specific examples. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in the description. The present application can also be implemented or applied in different specific implementation modes. Various details in the description can also be modified or changed based on different views and applications without departing from the spirit of the present application.

[0032] Refer to FIG. 1 to FIG. 7. It should be noted that the drawings provided in the embodiment only illustrate the basic concept of the present application in a schematic way, only illustrate the components related to the present application, and are not drawn according to the number, shape and size of the components in actual implementation. The type, number and scale of the components in actual implementation may be changed freely, and the layout of the components may be more complex.

[0033] The present application provides a process method for improving reliability of a metal gate high-voltage device. Referring to FIG. 7, it illustrates a flowchart of a process method for improving reliability of a metal gate high-voltage device according to the present application. The method at least includes the following steps:

[0034] In step 1, a semiconductor structure is provided. The semiconductor structure includes a high-voltage device active area; a gate oxide layer formed over the high-voltage device active area; and stack layers formed over the gate oxide layer and spaced apart from each other. Regions between the stack layers are slot regions. Referring to FIG. 1, it illustrates a schematic diagram of a semiconductor structure in the present application. In step 1, a semiconductor structure is provided. The semiconductor structure includes a high-voltage device active area (HVAA); a gate oxide layer (GOX) 01 formed over the high-voltage device active area; and stack layers formed over the gate oxide layer and spaced apart from each other. Regions between the stack layers are slot regions B.

[0035] Further, in this embodiment, in step 1, the stack layers are formed by sequentially stacking at least polysilicon, silicon nitride and a PEOX layer from bottom to top. Referring to FIG. 1, the stack layers sequentially includes polysilicon (poly), silicon nitride (SiN) and a PEOX layer (“PEOX”) 02 from bottom to top.

[0036] In step 2, an SiCN layer is deposited to cover tops and sidewalls of the stack layers, and cover bottoms of slots between the stack layers. Referring to FIG. 1, in step 2, an SiCN layer (SiCN) is deposited to cover tops and sidewalls of the stack layers, and cover bottoms of slots B between the stack layers.

[0037] Further, in this embodiment, in step 2, the thickness of the SiCN layer (SiCN) is 90Å.

[0038] Further, in this embodiment, in step 2, a method for depositing the SiCN layer (SiCN) is chemical vapor deposition.

[0039] In step 3, an HARP layer is deposited to cover the SiCN layer. Referring to FIG. 2, it illustrates a schematic diagram of a structure after an HARP layer is deposited in the present application. In step 3, an HARP layer is deposited to cover the SiCN layer.

[0040] Further, in this embodiment, in step 3, the thickness of the deposited HARP layer is 150Å.

[0041] In step 4, the HARP layer over the stack layers and the slot regions is covered with a photoresist, photolithography and etching are sequentially performed to open the HARP layer over the stack layers, and the photoresist in the slot regions is reserved. Referring to FIG. 3, it illustrates a schematic diagram of a structure after a photoresist is filled in slots in the present application. In step 4, the HARP layer over the stack layers and the slot regions is covered with a photoresist 04, photolithography and etching are sequentially performed to open the HARP layer over the stack layers, and the photoresist 04 in the slot regions is reserved.

[0042] In step 5, the HARP layer over the stack layers outside the slot regions is removed. Referring to FIG. 4, it illustrates a schematic diagram of a structure after an HARP layer over stack layers outside slot regions is removed in the present application. After the HARP layer over the stack layers outside the slot regions is removed, the photoresist in the slot regions is also removed to form a structure illustrated in FIG. 4. The spacer of the slot regions and the HARP layer at the bottom are exposed.

[0043] Further, in this embodiment, in step 5, a wet etching process is adopted to remove the HARP layer over the stack layers outside the slot regions.

[0044] Further, in this embodiment, in step 5, etching solution in the wet etching process is hydrofluoric acid.

[0045] Further, in this embodiment, in step 5, the concentration of hydrofluoric acid is 300:1 or 200:1.

[0046] In step 6, steps 3 to step 5 are repeated for many times until the slot regions are filled with the HARP layer. Referring to FIG. 5, it illustrates a schematic diagram of a structure after slot regions are filled with an HARP layer in the present application. \

[0047] Further, in this embodiment, in step 6, step 3 to step 5 are repeated for 1-2 times.

[0048] In step 7, etching is performed to remove the SiCN layer over the stack layers. Referring to FIG. 6, it illustrates a schematic diagram of a structure after etching is performed to remove an SiCN layer over stack layers in the present application.

[0049] Further, in this embodiment, in step 7, a method for performing etching to remove the SiCN layer is dry etching.

[0050] To sum up, in the present application, by adding the HARP layer in the slot regions and repeating the deposition and etching processes of the HARP layer, an HARP protective layer is formed inside the slot regions and no HARP is remained in other regions, thus improving the reliability of the high-voltage device without affecting other devices. Therefore, the present application effectively overcomes various disadvantages of the existing technology and has a great industrial utilization value.

[0051] The above embodiments are only used for exemplarily describing the principle and effect of the present application, instead of limiting the present application. Those skilled in the art may modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical concept disclosed by the present application shall still be covered by the claims of the present application.