Process for epitaxying gallium selenide on a [111]-oriented silicon substrate

Abstract

A process for epitaxying GaSe on a [111]-oriented silicon substrate, includes a step of selecting a [111]-oriented silicon substrate resulting from cutting a silicon bar in a miscut direction which is one of the three [11-2] crystallographic directions, the miscut angle (α) being smaller than or equal to 0.1°, the obtained surface of the substrate forming a vicinal surface exhibiting a plurality of terraces and at least one step between two terraces; a passivation step consisting of depositing an atomic bilayer of gallium and of selenium on the vicinal surface of the silicon substrate so as to form a passivated vicinal surface made of silicon-gallium-selenium (Si—Ga—Se), said passivated vicinal surface exhibiting a plurality of passivated terraces and at least one passivated step between two passivated terraces; a step of forming a layer of two-dimensional GaSe by epitaxy on the passivated surface, said formation step comprising a step of nucleation from each passivated step and a step of lateral growth on the passivated terraces from the nuclei obtained in the nucleation step. A structure obtained by means of the epitaxying process is also provided.

Claims

1. A process for epitaxying GaSe on a [111]-oriented silicon substrate, comprising: a step of selecting a [111]-oriented silicon substrate, said substrate resulting from cutting a silicon bar in a miscut direction which is one of the three [11-2] crystallographic directions, the miscut angle (α) being smaller than or equal to 0.1°, the obtained surface of the substrate forming a vicinal surface exhibiting a plurality of terraces and at least one step between two terraces; a passivation step consisting of depositing an atomic bilayer of gallium and of selenium on the vicinal surface of the silicon substrate so as to form a passivated vicinal surface made of silicon-gallium-selenium (Si—Ga—Se), said passivated vicinal surface exhibiting a plurality of passivated terraces and at least one passivated step between two passivated terraces; a step of forming a layer of two-dimensional GaSe by epitaxy on the passivated surface, said formation step comprising a step of nucleation from each passivated step and a step of lateral growth on the passivated terraces from the nuclei obtained in the nucleation step.

2. The process according to claim 1, further comprising a step of treating the vicinal surface so as to flatten the terraces of said vicinal surface until a substantially zero roughness is obtained on the terraces, said treatment step being carried out after the substrate selection step and before the passivation step.

3. The process according to claim 2, the treatment step consisting of heat-treating the silicon substrate at high temperature, preferably higher than 800° C.

4. The process according to claim 1, the passivation step consisting of metal-organic chemical vapour deposition (MOCVD) with metal-organic precursors.

5. The process according to claim 4, the metal-organic precursors being trimethylgallium (TMGa) and diisopropyl selenide (DIPSe), the partial pressure of TMGa preferably being between 1 and 200 mTorr.

6. The process according to claim 4, the passivation step being carried out at a temperature of between 400 and 650° C., and for a duration of between 2 and 30 seconds.

7. The process according to claim 1, the nucleation step consisting of metal-organic chemical vapour deposition with metal-organic precursors, the partial pressure of the gallium precursor being lower than or equal to 50 mTorr.

8. The process according to claim 7, the nucleation step being carried out at a temperature of between 400 and 650° C.

9. The process according to claim 7, the nucleation step being carried out for a duration of between 2 and 30 seconds.

10. The process according to claim 1, the lateral growth step consisting of metal-organic chemical vapour deposition with metal-organic precursors, the partial pressure of the gallium precursor being between 0.5 and 5 mTorr.

11. The process according to claim 10, the lateral growth step being carried out at a temperature of between 570 and 650° C.

12. The process according to claim 1, further comprising a step of removing the oxide from the vicinal surface, said deoxidation step being carried out after the substrate selection step and before the passivation step.

13. The process according to claim 1, further comprising an additional step of epitaxying at least one 2D material other than 2D GaSe or at least one 3D semiconductor material, said additional step of epitaxy being formed on the layer of 2D GaSe.

14. A method according to claim 13, the at least one 2D material other than 2D GaSe or the at least one 3D material being chosen from the III-VI materials such as InSe, GaS, GaTe or a combination of III-VI materials, the III-V materials such as GaN, InGaN, GaAs, GaSb or a combination of III-V materials, the II-VI materials such as CdHgTe or a combination of II-VI materials, or the IV-IV materials such as SiGe or Ge—Ge or a combination of IV-IV materials.

15. A structure obtained by means of the process for epitaxying GaSe on a [111]-oriented silicon substrate according to claim 1, comprising: a [111]-oriented silicon substrate, the surface of which is a passivated vicinal surface exhibiting passivated terraces and at least one passivated step between two passivated terraces, the miscut angle (α) of the vicinal surface being smaller than or equal to 0.1°; a layer of 2D GaSe formed on the passivated terraces, and exhibiting a single orientation without antiphase boundaries.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other features and advantages of the invention will become apparent through the description which follows by way of non-limiting illustration, given with reference to the appended figures, among which:

(2) FIG. 1A and FIG. 1B illustrate an Si—Ga—Se surface with two opposing orientations.

(3) FIG. 2 illustrates the formation of grains of 2D GaSe with two orientations at 180° with respect to one another.

(4) FIG. 3A-FIG. 3G show an exemplary process for epitaxying 2D GaSe on an Si(111) substrate according to the invention.

DETAILED DESCRIPTION

(5) FIGS. 1A, 1B and 2 have been described already and will not be revisited here.

(6) FIGS. 3A to 3G show an exemplary process for epitaxying 2D GaSe on an Si(111) substrate according to the invention.

(7) The first step of the process is a selection step which consists in selecting a [111]-oriented silicon substrate obtained from a silicon crystal bar 1 cut into slices according to cutting specifications suitable for obtaining a [111]-oriented silicon vicinal surface 2, which could also be called a vicinal Si(111) substrate.

(8) More precisely, the vicinal Si(111) substrate is produced by cutting the silicon bar along a miscut direction 11, 12, 13 of the substrate which is precisely along one of the three equivalent [11-2] crystallographic directions. In other words, the silicon crystal is cut along one of the following azimuthal angles: 90°, 30° or −30° with respect to the [1-10] direction of the notch for the orientation of the crystal lattice of the substrate.

(9) FIG. 3A illustrates the three equivalent [11-2] crystallographic directions in a top view of the Si(111) silicon crystal bar 1. The bar may for example be cut along direction 11 which corresponds to one of the three equivalent [11-2] crystallographic directions.

(10) FIG. 3B illustrates the misorientation parameters. The misorientation of the crystal is defined by a miscut angle α, which defines the angle between the normal of the vicinal surface 2 and the [111] direction.

(11) As mentioned in the disclosure of the invention, in a vicinal surface, the atoms are not distributed in a plane but are organized in a set of terraces and at least one step spaced apart by two terraces. The height of a step is a multiple of the distance between two successive planes of atoms. Thus, the vicinal surface 2 illustrated appears as a succession of terraces 21 and at least one step 22 between two terraces. The width L of the terraces corresponds to the dimension along the [11-2] crystallographic direction chosen for the cut. The height h of a step corresponds to the dimension along the [111] crystallographic direction.

(12) The miscut angle α makes it possible to determine the width L of the terraces 21, using the following formula:
L=h/(tan α)  [Math1]
where h is the height of the steps.

(13) The height of a step is around 0.3 nm in the case of Si(111).

(14) The misorientation of the crystal is also defined by the miscut direction which is one of the three [11-2] crystallographic directions, as mentioned above.

(15) Additionally, to have wide terraces and therefore a low step density, the miscut angle is chosen so as to be smaller than or equal to 0.1°. A low step density favours a low density of nuclei, thus limiting the potential defects that may occur in the step of nucleation of the GaSe (dislocation in particular). The expression “low step density” is generally understood to mean a step for a terrace width of at least 200 nanometres.

(16) An Si(111) substrate with a slightly misoriented vicinal surface is thus obtained, that is to say one with a miscut angle smaller than or equal to 0.1°.

(17) After the selection step and before the treatment step described below, the process may comprise a step of removing oxide from the (111) silicon surface, for example using a wet treatment using hydrogen fluoride (HF) or using plasma in a Siconi™-type deoxidation chamber.

(18) The second step of the process is a treatment step which consists of a treatment of the vicinal surface 2 obtained so as to flatten the [111]-oriented terraces 21. This allows the steps to be made to appear as precisely oriented in the [11-2] direction, as illustrated in FIG. 3C. This treatment step, carried out at high temperature, consists in surface-diffusing the silicon atoms until they reach their equilibrium position so as to reveal the lowest-energy [111]-oriented silicon planes. The residual roughness of the [111]-oriented terraces of the silicon substrate after cutting and chemical-mechanical polishing (CMP) is thus brought to a value close to zero.

(19) This treatment step is typically carried out by introducing the substrate into an epitaxy chamber. A gas is introduced, for example hydrogen. Alternatively, it may be helium, argon or any other inert gas from column VIII of the periodic table.

(20) The treatment step is generally carried out at between 800° C. at 1100° C.

(21) The pressure in the chamber may come within a large range, for example between 1 mTorr and 750 Torr, or even between 1 mTorr and 600 Torr. Preferably, the pressure in the chamber is low, that is to say typically lower than 20 Torr, preferably lower than 10 Torr. A low pressure prevents the silicon from starting to be etched by the gas, in particular hydrogen, and thus it prevents the formation of pits in the surface of the silicon.

(22) The treatment duration is generally between 5 and 30 minutes.

(23) According to one particular exemplary embodiment, the conditions of the treatment step are:

(24) pressure in the chamber: 5-10 Torr;

(25) temperature: 900° C.;

(26) treatment duration: 10 minutes.

(27) The third step of the process is a step of passivating the vicinal Si(111) surface, and this is done by depositing an atomic bilayer of gallium and of selenium, that is to say one atomic layer of gallium (Ga) and one atomic layer of selenium (Se), on the Si(111) surface. This makes it possible to obtain the formation of a passivated vicinal surface 3 of Si—Ga—Se, as illustrated in FIG. 3D. Specifically, the highly reactive Si—H hydrogen bonds at the surface of the Si(111) are replaced with Si—Ga—Se bonds that are stable to a high temperature (up to around 650-750° C.) and are electronically passivated, i.e. the valence layer of the atoms at the surface is full (the valence electrons are paired). This passivated surface, of very low energy, then allows the epitaxying of a 2D material without covalent bonds with the terraces 21 of the silicon substrate [111], as described further below.

(28) The GaSe passivation bilayer formed of one atomic layer of Ga bonded to one atomic layer of Se also corresponds to a half-sheet of the 2D GaSe material, a sheet consisting of four atomic layers in the sequence Se—Ga—Ga—Se. 2D GaSe denotes gallium selenide structured as one or more sheets.

(29) According to the invention, the expression “electronically passivated” surface, or “electronic passivation” of a surface, is understood to mean a surface that is chemically inert and stable even at a high temperature (up to around 650-750° C.) with atoms having a full valence layer. The expression “electronically saturated surface” may also be used.

(30) To carry out this passivation step, the Si(111) substrate is kept in the epitaxy chamber and the half-sheet of GaSe is deposited using the deposition technique of metal-organic chemical vapour deposition (MOCVD). The MOCVD technique is performed by conveying metal-organic precursors into the epitaxy chamber via a vector gas.

(31) To obtain the GaSe half-sheet using MOCVD, metal-organic precursors, which are typically trimethylgallium (TMGa) and diisopropyl selenide (DIPSe), which are gaseous at the temperature used in the process, are introduced into the chamber simultaneously. Alternatively, any other gallium precursor and/or any other selenium precursor may be used.

(32) The vector gas is typically hydrogen. Alternatively, it may be nitrogen, or an inert gas from column VIII of the periodic table.

(33) The passivation step is generally carried out at between 400° C. at 650° C.

(34) The total pressure in the chamber depends on the equipment but values are typically between 5 and 200 Torr.

(35) The partial pressure of the gallium precursor is generally between 1 and 200 mTorr.

(36) The III/VI (group III precursor/group VI precursor) molar flux ratio is generally between 1 and 10.

(37) The duration of the passivation step is generally between 2 and 30 seconds.

(38) According to one particular exemplary embodiment, the conditions of the passivation step are:

(39) total pressure in the chamber: 10-20 Torr;

(40) partial pressure of TMGa: around 10 mTorr;

(41) Se/Ga (VI/III) molar flux ratio: around 3-4;

(42) temperature: 530-550° C.;

(43) passivation duration t: between 2 and 5 seconds.

(44) The half-sheet of GaSe for obtaining the passivation surface has a thickness of about 2 Å.

(45) The MOCVD technique is advantageous because it allows good reproducibility, good uniformity on the substrate scale and high crystal growth speeds. It is therefore compatible with industrial applications.

(46) Alternatively, it is possible to use other chemical vapour deposition (CVD) techniques such as plasma-enhanced chemical vapour deposition (PECVD), atomic layer deposition (ALD) or hydride vapour phase epitaxy (HVPE).

(47) Alternatively again, it is possible to use the technique of molecular beam epitaxy (MBE) which consists in projecting one or more molecular beams towards the substrate in order to carry out epitaxial growth.

(48) The fourth step of the process is a step of forming a layer of 2D GaSe on the passivated vicinal surface. It consists in growing GaSe two-dimensionally (in order to effectively obtain a layer of 2D GaSe) on the passivated surface 3. It thus consists of epitaxy which comprises a step of nucleation and a step of lateral growth from the nuclei until a continuous buffer layer is formed. The steps of nucleation and of lateral growth are described below.

(49) The step of nucleation is carried out by depositing grains (or nuclei) 41 of GaSe on the passivation surface, as illustrated in FIG. 3E, and more precisely on the surface of a terrace against the step of this terrace. The nuclei 41 of GaSe have an initial width that is typically between 1 and 20 nanometres.

(50) To carry out the nucleation, the substrate is kept in the growth chamber and the MOCVD technique is used. The precursors that may be used are the same as for the passivation step. The pressures employed are lower than those of the passivation step.

(51) The vector gas is typically hydrogen. Alternatively, it may be nitrogen, helium, or any other inert gas from column VIII of the periodic table.

(52) To promote nucleation against the steps rather than within the terraces, the partial pressure of the precursor (TMGa for example) is advantageously low or moderate (lower than or equal to 50 mTorr) in order to minimize encounters of the Ga and Se atoms with one another within the terraces instead of against the steps, and the temperature is high enough (at least 400° C. but preferably at least 500° C.) to allow the surface diffusion of the atoms to the steps.

(53) Thus, the nucleation step is generally carried out at between 400° C. at 650° C.

(54) The total pressure is adjusted according to the geometry of the chamber, but values are typically between 5 and 80 Torr.

(55) The partial pressure of the gallium precursor is generally between 1 and 50 mTorr.

(56) The VI/III molar flux ratio will depend on the type of precursor; values are typically between 3 and 4 Torr.

(57) The duration of the nucleation step is generally between 2 and 30 seconds.

(58) These conditions are thus chosen so as to promote the diffusion and the attachment of the Ga and Se atoms from the steps, which is the minimum-energy configuration. The growth of the 2D GaSe may thus be preferentially initiated from the steps instead of in an uncontrolled manner on the terraces, such as for example in the middle of the terraces.

(59) During this nucleation step, the GaSe nuclei will align from the steps with a single orientation, and precisely with the [11-2] direction of the silicon surface aligned with the [11-20] direction of the GaSe ([11-2].sub.Si//[11-20].sub.GaSe).

(60) According to one particular exemplary embodiment, the conditions of the nucleation step are as follows:

(61) total pressure of the chamber: 5-20 Torr;

(62) partial pressure of TMGa: around 2-3 mTorr;

(63) Se/Ga (VI/III) molar flux ratio: around 3-4;

(64) temperature: 530-550° C.;

(65) nucleation duration: 2-15 seconds.

(66) The step of lateral growth of the grains of GaSe consists in laterally growing, i.e. laterally with respect to the plane of the terrace on which the grains have been deposited, the grains 41 of GaSe deposited in the nucleation step, and to do so over several microns, as illustrated in FIGS. 3F and 3G, until the grains coalesce into a continuous layer 4, of single orientation without grain boundaries.

(67) The step of lateral growth of the grains of GaSe is carried out at lower partial pressure and higher temperature than the nucleation step.

(68) The substrate is kept in the growth chamber.

(69) The lateral growth step is generally carried out at between 570° C. at 650° C.

(70) The total pressure depends on the equipment used but values are typically between 5 and 80 Torr.

(71) The partial pressure of the precursors is generally between 0.5 and 5 mTorr.

(72) The VI/III molar flux ratio is generally between 3 and 4.

(73) The duration of the lateral growth step is generally between 5 and 120 minutes.

(74) According to one particular exemplary embodiment, the conditions of the growth step are as follows:

(75) total pressure of the chamber: 5-20 Torr;

(76) partial pressure of TMGa: around 1 mTorr;

(77) Se/Ga (VI/III) molar flux ratio: around 3-4;

(78) temperature: 600-640° C.;

(79) growth duration: 1000-2000 seconds.

(80) The process according to the invention makes it possible to carry out epitaxy by advancing from the steps of GeSe nuclei and thus obtain a layer of 2D GaSe of single orientation and without grain boundaries.

(81) The structure formed by the process comprises:

(82) a [111]-oriented silicon substrate, the surface of which is a passivated vicinal surface 3 exhibiting passivated terraces 31 and at least one passivated step 32 between two passivated terraces;

(83) a layer 4 of 2D GaSe formed on the passivated terraces, and exhibiting a single orientation without antiphase boundaries.

(84) The miscut angle α of the vicinal surface 3 of the [111]-oriented silicon substrate is smaller than or equal to 0.1°.

(85) Preferably, the structure of the orientation of the GaSe with respect to the silicon surface is ([11-2].sub.Si/[11-20].sub.GaSe).

(86) The structure thus obtained is therefore of high crystal quality and allows its integration in electronic, optical, energy, etc. applications.

(87) The process used may be on a large scale and with a high yield, thus making it compatible with use in the industry.

(88) The layer of 2D GaSe formed may act as a buffer layer on which other 2D materials may be grown by van der Waals epitaxy, using for example the MOCVD technique. These other 2D materials may be for example chosen from other III-VI semiconductors such as InSe, GaS, GaTe, etc., or a combination of several III-VI materials, so as to obtain the band alignment corresponding to the type of component that is to be manufactured (photodetector, LED, MOSFET, TFET and generally all “more-than-Moore” components).

(89) These additional layers may thus grow, in epitaxial relation with the layer of 2D GaSe, with a single orientation.

(90) Instead of a 2D material, it may be a 3D material, which may be: a III-V material such as GaN, InGaN GaAs, GaSb or a combination of several III-V materials, a II-VI material such as CdHgTe or a combination of several II-VI materials, or a IV-IV material such as SiGe or Ge—Ge or a combination of several IV-IV materials.

(91) Unless stated otherwise or obvious, the different embodiments may be combined. The present invention is not limited to the embodiments described above but rather extends to any embodiment that comes within the scope of the claims.

(92) Among the numerous applications of the invention, mention may be made of microelectronics, photonics, sensors, radiofrequency-related technologies, micro-electromechanical systems (MEMS), components for the Internet of Things, battery chargers, high-voltage components, microprocessors, static and dynamic memory, photovoltaics and more broadly anything to do with “more-than-Moore” technologies or what are referred to as “derivative” technologies, that is to say technologies which incorporate several functions on a single silicon chip.