Bonded substrate including polycrystalline diamond film

Abstract

A wafer has a layer containing silicon, a layer of polycrystalline diamond deposited on the silicon-containing layer, and a bow-compensation layer on the other side of the silicon-containing layer for reducing wafer-bow. A method of making a bonded structure includes an activation process for creating dangling bonds on the surface of one substrate, followed by contact-bonding the surface to a second substrate at low temperature. A bonded structure may include two substrates contact bonded to each other, one substrate including a layer containing silicon, a layer of polycrystalline diamond, a bow-compensation layer for reducing wafer-bow of the first substrate, and the other substrate including gallium nitride, silicon carbide, lithium niobate, lithium tantalate, gallium arsenide, indium phosphide, or another suitable material other than diamond.

Claims

1. A wafer comprising: a layer containing silicon; a layer of polycrystalline diamond deposited on the layer containing silicon; a polished silicon layer on the layer of polycrystalline diamond; and a bow-compensation layer for reducing wafer-bow of the layer containing silicon and the layer of polycrystalline diamond; and wherein the layer containing silicon is located between the layer of polycrystalline diamond and the bow-compensation layer, and wherein the layer of polycrystalline diamond is located between the polished silicon layer and the layer containing silicon.

2. The wafer of claim 1, wherein the wafer-bow is less than 50 microns.

3. The wafer of claim 1, further comprising acoustic mirror layers deposited on the polished silicon layer.

4. The wafer of claim 3, wherein the acoustic mirror layers have alternating low acoustic and high acoustic impedances.

5. A method of making a bonded structure comprising: forming a first substrate by depositing a silicon material on a layer of polycrystalline diamond; performing an activation process on a surface of the first substrate; and contact bonding the surface of the first substrate to a surface of a second substrate to form a bonded structure; wherein the contact bonding is performed at room temperature, or the bonded structure is thermally annealed at a low temperature.

6. The method of claim 5, wherein the activation process includes a plasma activation process.

7. The method of claim 5, wherein the activation process includes a chemical activation process.

8. The method of claim 6, further comprising reducing surface roughness of the silicon material.

9. The method of claim 8, wherein the surface roughness of the silicon material is reduced by chemical-mechanical polishing.

10. The method of claim 8, wherein the surface roughness of the silicon material is reduced by ion milling or magnetorheological finishing.

11. The method of claim 6, wherein plasma for the plasma activation process includes nitrogen, oxygen, a chemically active gas, or an inert gas, and is used to create dangling bonds on the surface of the first substrate.

12. The method of claim 11, further comprising performing a plasma activation process on the surface of the second substrate to create dangling bonds on the surface of the second substrate.

13. The method of claim 6, further comprising performing a water treatment process on the surface of the first substrate.

14. The method of claim 13, wherein the water treatment process includes a megasonic cleaning process.

15. The method of claim 6, further comprising aligning the first and second substrates.

16. The method of claim 6, wherein the contact bonding of the first and second substrates is achieved by Van der Waals forces between the surface of the first and the surface of the second substrate.

17. The method of claim 16, wherein the contact bonding of the surface of the first substrate to the surface of the second substrate is performed at room temperature.

18. The method of claim 16, wherein the bonded structure is thermally annealed at a low temperature, and wherein the low temperature is ≤300° C.

19. The method of claim 16, wherein the bonded structure is thermally annealed at a low temperature, and wherein the low temperature is ≤450° C.

20. The method of claim 16, wherein the bonded structure is thermally annealed at a low temperature, and wherein the low temperature is ≤600° C.

21. A bonded structure comprising: a first substrate including a layer containing silicon, a layer of polycrystalline diamond, a bow-compensation layer for reducing wafer-bow of the first substrate, and a first bonding surface; and a second substrate including gallium nitride, silicon carbide, lithium niobate, lithium tantalate, gallium arsenide, or indium phosphide, and a second bonding surface comprising an aluminum nitride nucleation layer, wherein the first bonding surface of the first substrate is contact-bonded to the second bonding surface of the second substrate.

22. The bonded structure of claim 21, wherein the second substrate includes a removable carrier substrate, and wherein the gallium nitride, silicon carbide, lithium niobate, lithium tantalate, gallium arsenide, or indium phosphide of the second substrate is located between the removable carrier substrate and the second bonding surface of the second substrate.

23. The bonded structure of claim 21, wherein the first substrate includes an aluminum nitride layer, and the aluminum nitride layer and the aluminum nitride nucleation layer include the first bonding surface of the first substrate and the second bonding surface of the second substrate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a cross-sectional view of a wafer structure constructed in accordance with the present disclosure;

(2) FIG. 2 is a cross-sectional view of another wafer structure constructed in accordance with the present disclosure;

(3) FIG. 3 is a schematic illustration of a method of bonding first and second wafer structures to each other;

(4) FIG. 4 is a cross-sectional view of a bonded structure constructed in accordance with the present disclosure;

(5) FIG. 5 is a cross-sectional view of a layered structure, not containing diamond, constructed in accordance with the present disclosure;

(6) FIG. 6 is a cross-sectional view of yet another wafer structure constructed in accordance with the present disclosure;

(7) FIG. 7 is cross-sectional view of a bonded structure including the layered and wafer structures of FIGS. 5 and 6; and

(8) FIG. 8 is a cross-sectional view of the bonded structure of FIG. 7 at a subsequent stage of production.

DETAILED DESCRIPTION

(9) Referring now to the drawings, where like elements are designated by like reference numerals, there is shown in FIG. 1 an example of a wafer structure 10 constructed in accordance with the present disclosure. The wafer structure 10 includes a wafer 12 which contains silicon (Si), a diamond layer 14 deposited on the front side 16 of the wafer 12, formed of polycrystalline diamond, and a bow-compensation layer 18 deposited on the back side 20 of the wafer 12. If desired, the wafer 12 may be formed of elemental silicon. The bow-compensation layer 18 may be a film or layer of high compression-strength material.

(10) A mis-match between the coefficients of thermal expansion (CTE) of the materials of the silicon-containing wafer 12 and the diamond layer 14 tends to induce an undesirable wafer-bow within the wafer structure 10. The bow compensation layer 18 prevents or at least reduces the extent of such wafer-bow by providing wafer back-side compensation. The bow-compensation layer 18 may be a film of high compression-strength material such as aluminum nitride (AlN), silicon nitride (SiN), or some other suitable dielectric material. Alternatively, the bow-compensation layer 18 may include high compression-strength metal or some other high compression-strength material.

(11) The term “wafer-bow,” as used herein, means the extent to which a central portion 22 of the back side 20 of the wafer 12 is deflected upwardly (as viewed in FIG. 1) from a corresponding central portion of a plane 24 which extends through the back-side edges 26, 28 of the wafer 12. In other words, the term “wafer-bow,” as used herein, means the distance between (A) the back-side central portion 22 of the wafer 12 and (B) the plane 24, in a direction normal to the plane 24. If desired, the wafer structure 10 may have a wafer-bow of <50 μm, more preferably <35 μm, even more preferably <25 μm, and even more preferably <15 μm.

(12) In the example illustrated in FIG. 1, the diamond layer 14 is formed by depositing or bonding polycrystalline diamond on or to the front side 16 of the wafer 12, and then polishing the front side 30 of the diamond layer 14. If the surface roughness of the diamond-layer front-side 30 is too rough for surface bonding despite such polishing, then one or more foreign materials may be deposited on the diamond-layer front-side 30 and polished to a surface roughness that is low enough and suitable for wafer bonding.

(13) The one or more foreign materials deposited on the diamond-layer front-side 30 may include, for example, a dielectric material such as silicon dioxide (SiO.sub.2), a metallic layer, or a semiconductor layer such as silicon (Si). Chemical-mechanical polishing (CMP) may be performed on the one or more foreign materials to provide a surface roughness that is low enough and suitable for wafer bonding. If the chemical-mechanical polishing results in undesirable within-wafer-non-uniformity (WWNU), then the polishing may be supplemented or replaced by magnetorheological finishing (MRF) or ion milling.

(14) According to one aspect of the present disclosure, the chemical-mechanical polishing process is optional. If desired, the one or more foreign materials may be deposited on or otherwise applied to the diamond-layer front-side 30 with a sufficiently smooth surface according to a process which does not require chemical-mechanical polishing. For example, a SiO.sub.2 layer may be deposited on or otherwise applied to the diamond-layer front-side 30 with a sufficiently smooth surface such that chemical-mechanical polishing of the SiO.sub.2 layer is not required. According to another embodiment of the present disclosure, for example, a spin-on-glass process may be applied on the diamond layer to provide a sufficiently smooth surface for a desired bonding process such that chemical-mechanical polishing is not required.

(15) A suitable process for forming the wafer structure 10 may be as follows: Polycrystalline diamond is grown on the front side 16 of the silicon-containing wafer 12 (an example of a substrate) to produce the diamond layer 14 (but with a rough surface). Then, the rough surface of the diamond layer 14 is polished to a mirror surface finish along with other processing steps to achieve desired wafer specifications. Then, a compensation process is performed by depositing a layer 18 of aluminum nitride on the back side 20 of the wafer 12 so that bowing caused by a mis-match between the coefficients of thermal expansion of the wafer 12 and the polycrystalline diamond layer 14 is prevented or at least reduced.

(16) FIG. 2 shows a wafer structure 100 which has a suitably low surface roughness on a front side 102. The wafer structure 100 includes a stack of acoustic mirror layers 104, 106, 108, in order, on the diamond-layer front-side 30 of the wafer structure 10 of FIG. 1. The first layer 104 may include SiO.sub.2. The second layer 106 may include W, AlN, or SiC. The third layer 108 may include SiO.sub.2 or Si. The wafer structure 100 may be produced by depositing the acoustic mirror layers 104, 106, 108 or other combinations of low acoustic/high acoustic materials, or by alternatingly depositing, in the same order or in different orders, low acoustic impedance and high acoustic impedance layers to construct an effective acoustic mirror for reflecting an acoustic wave. Additional layers (not shown), similar to the illustrated layers 104, 106, 108, may be deposited on the wafer structure 10 in a repeating pattern, if desired, to obtain desired physical, acoustic, thermal, or other benefits and characteristics.

(17) If desired, the top-most layer 108 of the wafer structure 100 may be tens of microns thick, or less than ten microns thick, or less than one micron thick. The top-most layer 108 may be, for example, a layer of about 1.5 μm of low acoustic impedance material (SiO.sub.2 or Si, preferably amorphous silicon). The surface 102 of the top-most layer 108 may be chemically-mechanically polished to achieve a desirable surface roughness which may be Ra≤2 nm, or more preferably ≤1 nm. If the polished surface 102 has unacceptable within-wafer-non-uniformity, then ion-trimming or magnetorheological finishing may be employed to further reduce the SiO.sub.2/Si top-most layer 108 to a uniform thickness.

(18) In an alternative embodiment, at least a transition layer (not shown) may be deposited on the wafer structure 10 to achieve acceptable surface roughness.

(19) The process for preparing a bonded substrate including a layer of polycrystalline diamond material, to produce the device 100 illustrated in FIG. 2, may include surface preparation for achieving a desirable low surface roughness for wafer-to-wafer bonding, as follows: First, at least one layer 108 of foreign material is deposited on the front-side 30 of the polycrystalline diamond layer 14. The foreign material which is used to achieve a desirable low surface roughness may be one or more of a variety of different materials or devices, including, but not limited to, a dielectric material, a metallic material, or a semiconductor material such as PECVD silicon dioxide. Then, the surface 102 of the foreign material is polished to a surface roughness that is suitable for wafer-to-wafer bonding. Then, as an optional step, the polished foreign layer 108 is reduced to a uniform, desirable thickness by a suitable method such as ion-milling or magnetorheological finishing.

(20) The process illustrated in FIG. 3 may be used to bond one or more layers including gallium nitride (GaN), silicon carbide (SiC), lithium niobate (LiNbO3), lithium tantalate (LiTaO3), or another suitable material to a layered structure 100 which includes polycrystalline diamond, where the bonding occurs at low temperature (for example, at a bonding temperature<250° C.). First, in a plasma activation step 202, the surface 102 of the top-most layer 108 of the wafer structure 100 is activated by a plasma to create dangling bonds on the wafer surface 102. The plasma may contain nitrogen, oxygen, chemically active gas, or an inert gas. If desired, a surface of another substrate may also be activated using a similar or suitable surface-activation process.

(21) If desired, according to other embodiments of the present disclosure, the surface activation processes described herein may be used in connection with materials other than diamond. In general, one or more of the activation processes may be used to facilitate contact bonding of substrates neither of which contain diamond.

(22) Then, in an optional water treatment step 206, the plasma-activated surface 102 is further activated by water which may be provided by a megasonic cleaning process, or by moisture in the environment. If desired, the surfaces of the two substrates to be bonded together may be activated by water or by moisture in the air.

(23) Then, during an optional alignment step 208, the wafers are aligned as desired. Then, during a bonding step 210, the wafers are contact-bonded to each other to establish a bond therebetween by, for example, Van der Waals forces, and then, during an annealing step 212, the bonded wafers are thermally annealed at low temperature. The annealing temperature may be, for example, ≤300° C., or ≤450° C., or ≤600° C. The bonded structure may then be further processed into a desired device, which may be a passive device or an active device.

(24) According to another aspect of the present disclosure, to accomplish low temperature, or room temperature, wafer-to-wafer bonding, the surface 102 of the substrate containing diamond may be activated by fast atom beam (FAB) processing under vacuum. The desired activation produces dangling bonds on the activated surface. The surface of the other substrate (the one that does not include diamond) may be activated by a similar process. After one or both of the surfaces are activated, they may be aligned under high vacuum, and then bonded to each other. The bonding process may optionally be performed under pressure.

(25) If it is desired to bond a layer of GaN, SiC, LiNbO.sub.3, or LiTaO.sub.3 to a substrate that includes diamond, then the bonding process may be performed at an even lower temperature, such as room temperature. The wafer surface preparation for a room-temperature bonding process may be the same as that for the low-temperature process; however, if desired, the wafer surface may be activated by fast atom beam processing, and the bonding pressure may be <1.0×10.sup.−5 Pa.

(26) FIG. 4 shows another example of a wafer structure constructed in accordance with the present disclosure, where a substrate 300 includes a polycrystalline diamond layer 14 and a lithium niobate (LiNbO.sub.3) layer 302. The substrate 300 shown in FIG. 4 includes the wafer structure 10 shown in FIG. 1. As illustrated in FIG. 4, the polished front side 102 of a layer 108 of SiO.sub.2 deposited on the diamond layer 14 may be bonded to the layer 302 of lithium niobate. If desired, the thickness of the SiO.sub.2 layer 108 may be reduced to less than 2 microns, more preferably to less than 1 micron, before the lithium niobate layer 302 is bonded to the SiO.sub.2 layer 108.

(27) FIG. 5 shows an example of a layered structure 400 that contains a channel layer 402 of gallium nitride (GaN) epitaxially deposited on an epitaxially deposited substrate. Although the layer 402 includes gallium nitride in the illustrated example, the epitaxially deposited layer 402 may alternatively include silicon carbide, lithium niobate, lithium tantalate, or another suitable material. The illustrated structure 400 has an aluminum nitride (AlN) nucleation layer 404 deposited on a silicon or silicon carbide substrate 406. An AlGaN transition layer 408 is deposited on the nucleation layer 404. A GaN buffer layer 410 is deposited on the transition layer 408, and the GaN layer 402 is deposited on the buffer layer 410.

(28) A barrier 412, which may be formed of AlGaN, is deposited on the GaN channel layer 402, and then a SiN passivation layer 414 may be deposited on the barrier 412. A carrier substrate 416 may be deposited on or bonded to the passivation layer 414, and then the Si or SiC substrate 406 may be removed. If desired, the nucleation layer 404, the transition layer 408, and/or part of, or all of, the buffer layer 410 may be removed along with or after the removal of the Si or SiC substrate 406.

(29) FIG. 6 illustrates a layered structure 500 which includes diamond and which is adapted to be bonded to the GaN-containing layered structure 400 (FIG. 5). The layered structure 500 of FIG. 6 has a top-most film 502 that includes aluminum nitride. The layered structure 500 is prepared by depositing the aluminum nitride film 502 on the surface of the polycrystalline diamond layer 14. The deposited film 502 may alternatively be a dielectric layer, a metallic layer, or a semiconductor layer. The deposited film 502 may be subjected to chemical-mechanical polishing, ion trimming, and/or magnetorheological finishing to achieve a desired low surface roughness which may be, for example, Ra≤1 nm. The thickness of the aluminum nitride layer 502, after polishing, that is, as illustrated in FIG. 6, may be in the range of from 40 nm to 50 nm.

(30) FIG. 7 shows the result of bonding the layered structures of FIGS. 5 and 6. The bonding may be performed using the room temperature process described above after activation by fast atom beam processing. The present disclosure is not limited, however, to the examples described herein. Thus, the process may be used not only to bond a layered structure containing gallium nitride to a layered structure containing diamond deposited on a silicon wafer, but also to bond a layered structure containing silicon carbide, lithium niobate, lithium tantalate, or another suitable material to a layered structure containing diamond deposited on a silicon wafer. Also, the nucleation, transition, and buffer layers 404, 408, 410 shown in FIGS. 5 and 7 may be removed for improved physical, thermal, electrical, or electromagnetic benefits. The carrier substrate 416 may be used to handle the layered structure 400 before the layered structure 400 is bonded to the layered structure 500 (FIG. 6). After the bonding process, the carrier substrate 416 may be removed (FIG. 8).

(31) In the example illustrated in FIG. 8, the bonded structure includes a bow-compensation layer 18. However, according to other preferred embodiments of the present disclosure, if the substrates being bonded do not induce a large amount of wafer-bow, because, for example, the substrates are sufficiently small, or for some other reason, then the bow-compensation layer 18 may not be included.

(32) The present disclosure provides a method for bonding a first substrate (such as a wafer) to a second substrate (such as another wafer) at a low temperature or at an even-lower room temperature. The first substrate may contain a layer of polycrystalline diamond deposited on silicon. The second substrate may contain gallium nitride, silicon nitride, lithium niobate, lithium tantalate, and/or another suitable material. Low-temperature or room-temperature bonding of such substrates may be especially advantageous where it is desired to overcome a mis-match between the coefficients of thermal expansion of diamond, silicon, lithium niobate, lithium tantalate, and other related materials that may be in a stack of deposited or bonded materials.

(33) According to the present disclosure, wafer-to-wafer bonding at low temperature may be achieved by performing a surface activation process on one or more of the wafer surfaces by a plasma of N.sub.2, O.sub.2, and/or an inert gas, to create dangling bonds on the activated surface(s), following by bonding of the surfaces to each other. If desired, the surfaces may be further activated after the plasma activation, and before bonding, by atmospheric moisture or cleaning water.

(34) Wafer-to-wafer bonding at room temperature may be achieved by performing a surface activation process on one or more of the wafer surfaces by fast atom beam activation or ion beam milling, to create dangling bonds on the activated surface(s), followed by bonding the surfaces to each other under vacuum and at room temperature. If desired, the activation process may be supplemented or replaced by a chemical activation process which employs a suitable material for achieving activation of the surface(s) of one or more of the substrates to be bonded, where the suitable material is an oxidizing agent, an acid, a base, etc.

(35) What have been described above are examples. This disclosure is intended to embrace alterations, modifications, and variations to the subject matter described herein that fall within the scope of this application, including the appended claims. As used herein, the term “includes” means including but not limited to. The term “based on” means based at least in part on. Additionally, where the disclosure or claims recite “a,” “an,” “a first,” or “another” element, or the equivalent thereof, it should be interpreted to include one or more than one such element, neither requiring nor excluding two or more such elements.