Low power modulator with VCO quantizer

Abstract

Disclosed is a low power modulator with a VCO quantizer. The low power modulator with the VCO quantizer may include an integrator converting an input current to a voltage, a quantizer converting the converted voltage to digital information, a filter unit filtering the converted digital information, a DAC converting the filtered digital information into a feedback current, and a controller calculating the digital information output based on a difference value between the input current and the feedback current for each sampling time.

Claims

1. A low power modulator with a VCO quantizer comprising: an integrator converting an input current to a voltage; a quantizer converting the converted voltage to digital information; a filter unit filtering the converted digital information; a DAC converting the filtered digital information into a feedback current; and a controller calculating a digital information output based on a difference value between the input current and the feedback current for each sampling time, wherein the filter unit comprises a digital Infinite Impulse Response (IIR) filter, and wherein the filter unit is configured to receive a signal of the converted digital information from the quantizer, process a first signal passing through the digital IIR filter, process a second signal without passing through the digital IIR filter, combine the first signal and the second signal to transmit the combined signal to the DAC as the digital information.

2. The low power modulator with the VCO quantizer of claim 1, further comprising: a PWM adjusting a bit of the DAC to 1 bit.

3. The low power modulator with the VCO quantizer of claim 1, wherein the integrator outputs a feedback voltage that accumulates the difference value between the input current and the feedback current.

4. The low power modulator with the VCO quantizer of claim 3, wherein the quantizer outputs digital information corresponding to the feedback voltage.

5. The low power modulator with the VCO quantizer of claim 3, wherein the feedback voltage is increased or decreased for each sampling time.

6. The low power modulator with the VCO quantizer of claim 5, wherein the controller calculates an average value of the digital information corresponding to the feedback voltage for each sampling time.

7. The low power modulator with the VCO quantizer of claim 3, wherein a threshold value of the converted digital information is determined based on a voltage readable by the quantizer.

8. The low power modulator with the VCO quantizer of claim 1, wherein the difference value between the input current and the feedback current is accumulated in the integrator for each sampling time, and the integrator outputs a feedback voltage corresponding to the accumulated feedback current.

9. The low power modulator with the VCO quantizer of claim 1, wherein the filter unit filters a low frequency bandwidth of the digital information.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The above and other aspects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

(2) FIG. 1 is a diagram illustrating a low power modulator with a VCO quantizer according to an embodiment of the present disclosure;

(3) FIG. 2 is a diagram illustrating a mathematical model of a low power modulator with a VCO quantizer according to an embodiment of the present disclosure;

(4) FIG. 3 is a diagram showing a performance graph of the low power modulator with the VCO quantizer according to an embodiment of the present disclosure;

(5) FIGS. 4A and 4B are diagrams illustrating a noise simulation model of the low power modulator with the VCO quantizer according to an embodiment of the present disclosure; and

(6) FIGS. 5A and 5B are diagrams showing a noise performance graph of the low power modulator with the VCO quantizer according to an embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

(7) The present disclosure may have various modifications and various embodiments and specific embodiments will be illustrated in the drawings and described in detail.

(8) Various features of the present disclosure disclosed in claims will be better understood in consideration of the drawings and the detailed description. Apparatuses, methods, preparations and various embodiments disclosed herein will be provided for illustrative purposes. The disclosed structural and functional features are intended to specifically implement various embodiments by those skilled in the art, and are not intended to limit the scope of the present disclosure. Disclosed terms and sentences are for ease of description to understand various features of the disclosed invention, and are not intended to limit the scope of the present disclosure.

(9) In describing the present disclosure, if it is determined that a detailed description of related known technologies unnecessarily makes the gist of the present disclosure unclear, the detailed description will be described.

(10) Hereinafter, a low power modulator with a VCO quantizer according to an embodiment of the present disclosure will be described.

(11) FIG. 1 is a diagram illustrating a low power modulator 100 with a VCO quantizer according to an embodiment of the present disclosure.

(12) Referring to FIG. 1, the low power modulator 100 may include an integrator 110, a quantizer 120, a filter unit 130, a pulse width modulation (PWM) 140, a digital-to-analog converter (DAC) 150, and a controller (not illustrated).

(13) The integrator 110 may convert an input current to a voltage.

(14) In an embodiment, the integrator 110 may accumulate the input current in a capacitor included in the integrator 110 when the input current is input to amplify the accumulated input current to the voltage according to a value of the capacitor.

(15) At this time, since the integrator 110 maintains constantly a voltage of an input node according to a negative feedback characteristic of an Op-Amp included in the integrator 110, when connecting a diode, a cathode voltage does not swing, and thus a reverse biased voltage applied to a photodiode is maintained at the same voltage, thereby constantly maintaining an amplification rate of the photodiode itself.

(16) In one embodiment, even when the integrator 110 does not include the Op-Amp, the integrator 110 may constantly maintain the voltage of the input node by preventing the voltage of the input node from greatly swinging by the negative feedback through the filter unit 130, the PWM 140, and the DAC 150.

(17) However, when the Op-AMP of the integrator 110 is used, the effect thereof is further increased, and when there is the Op-Amp, the input voltage swings within 1 mV, but even when there is no Op-Amp, the input voltage swings only in about several mV according to a current value to maintain a diode cathode voltage.

(18) The quantizer 120 may convert the converted voltage to digital information.

(19) In one embodiment, the voltage based on the input current may be input to the quantizer 120 to change the frequency of an oscillator included in the quantizer 120. In one embodiment, the quantizer 120 may include a voltage-controlled oscillator (VCO).

(20) In one embodiment, the VCO serves as a quantizer that converts the voltage to a digital value, and senses a phase change rate of the oscillator by observing a difference in frequency changed for a certain time (sampling period) to quantize the voltage input to the VCO to a digital value.

(21) The filter unit 130 may filter the converted digital information. In one embodiment, the filter unit 130 may filter a low frequency bandwidth of the digital information.

(22) For example, the filter unit 130 may be implemented as a digital IIR filter. In one embodiment, the filter unit 130 may include a digital filter 132, and for example, the digital filter 132 may include a digital low pass filter.

(23) Then, in the digital information (e.g., digital code), digital information of a path through the digital filter 132 by two paths of the filter unit 130 determines a low frequency component input as the input and the digital information through the remaining path may be converted to a feedback current through the DAC 150 by passing through a high frequency component.

(24) That is, a current having a large amplitude of the low frequency input to an input end is removed by the digital information with only the low frequency remaining through the digital filter 132, and the digital information including the remaining high frequency component is a frequency component of a required signal to output a current signal to digital information through the DSM via a path which does not pass through the digital filter 132.

(25) The DAC 150 may convert the filtered digital information into a feedback current.

(26) The controller may calculate the digital information output based on a difference value between the input current and the feedback current for each sampling time.

(27) In one embodiment, the PWM 140 may adjust a bit of the DAC 150 to 1 bit.

(28) In one embodiment, the integrator 110 may output a feedback voltage that accumulates the difference value between the input current and the feedback current for each sampling time.

(29) In one embodiment, the quantizer 120 may output digital information corresponding to the feedback voltage. In one embodiment, a threshold value may be determined based on a voltage readable by the quantizer 120.

(30) In one embodiment, the feedback voltage may be increased or decreased for each sampling time.

(31) In one embodiment, the difference value between the input current and the feedback current may be accumulated in the integrator 110 for each sampling time. In this case, the integrator 110 may output a feedback voltage corresponding to the accumulated feedback current.

(32) In one embodiment, the controller may calculate an average value of the digital information corresponding to the feedback voltage for each sampling time.

(33) In one embodiment, in the input node, the feedback current and the input current of the DAC 150 are offset to each other, and may be accumulated in the first integrator 110 by an original difference between the input current and the feedback current.

(34) When continuously repeating the process, the difference between the input current and the feedback current is continuously accumulated, and when the quantizer 120 can determine the difference, the code of the DAC 150 is further increased by 1 and the feedback current of the DAC 150 is increased, so that the differences accumulated in the integrator 110 may be reduced.

(35) When the determination of the quantizer 120 is performed faster than a change rate of the input current and how many times the accumulated differences are repeated to be removed is calculated through an average by collecting the digital information, it can be seen that the value may be a smaller value than a minimum input value capable of being originally converted by the quantizer 120.

(36) In one embodiment, the controller may include at least one processor or micro processor, or apart of the processor. In addition, the controller may be referred to as a communication processor (CP). The controller may control an operation of the low power modulator 100 according to various embodiments of the present disclosure.

(37) Referring to FIG. 1, the low power modulator 100 may include an integrator 110, a quantizer 120, a filter unit 130, a PWM 140, a DAC 150, and a controller. In various embodiments of the present disclosure, since the components described in FIG. 1 are not required, the low power modulator 100 may be implemented to have more components or fewer components than the components described in FIG. 1.

(38) In one embodiment, the low power modulator 100 according to the present disclosure may include a delta-delta delta-sigma modulator (DSM) system for converting a broadband current signal to a digital value with low power.

(39) FIG. 2 is a diagram illustrating a mathematical model of the low power modulator with the VCO quantizer according to an embodiment of the present disclosure. FIG. 3 is a diagram showing a performance graph of the low power modulator with the VCO quantizer according to an embodiment of the present disclosure.

(40) Referring to FIG. 2, an error source for the low power modulator 100 may include a quantization error and a truncate error. The two errors are all 2nd order noise shaped to reduce the size of an error in a frequency domain of an interested signal.

(41) In one embodiment, a noise transfer function (NTF) for the low power modulator 100 may be represented by the following Equations 1 and 2.

(42) $\begin{array}{cc}NT{F}_Q=\frac{\left(a-z^{-1}\right){\left(1-z^{-1}\right)}^2}{D\left(Z\right)}& \left[\mathrm{Equation}1\right]\end{array}$

(43) Here, NTF.sub.Q represents a quantization error. Here, a and D(Z) may be represented by the following Equation 3.

(44) $\begin{array}{cc}NT{F}_T=\frac{k_a{k}_{VCO}{k_{DAC}\left(1-z^{-1}\right)}^2}{D\left(Z\right)}& \left[\mathrm{Equation}2\right]\end{array}$

(45) Here, NTF.sub.T represents a truncate error, K.sub.a may represent a 1/C.sub.F=10.sup.11, K.sub.VCO represents 10.sup.5, and K.sub.DAC may represent 32×3×10.sup.−8.
D(Z)=(a−z.sup.−1)k.sub.ak.sub.VCOk.sub.DACz.sup.−2+(1−z.sup.−1).sup.2
a=1+k.sub.truc  [Equation 3]

(46) Here, K.sub.a may represent 1/C.sub.F=10.sup.11, K.sub.VCO represents 10.sup.5, K.sub.DAC may represent 32×3×10.sup.−8, and K.sub.truc may represent ¼.

(47) First, the low power modulator 100 according to the present disclosure makes a DC feedback loop of offsetting a large current of a low frequency by external light by the filter unit 130 (that is, the digital filter) and the feedback DAC 150 to make a magnitude of the input current small and is applied to a DSM capable of measuring a wide input current to widen the input current range more than when using only the DSM and reduce a required sampling frequency, thereby reducing power consumption.

(48) Second, since the feedback DAC and the DC feedback of the DSM have the same input and output, the filter unit 130 is corrected as the following Equation 4 to combine two feedback paths to one, thereby reducing the system complexity.

(49) $\begin{array}{cc}\mathrm{Filter}=\frac{a-z^{-1}}{1-z^{-1}}& \left[\mathrm{Equation}4\right]\end{array}$

(50) Third, the DAC 150 is implemented to limit the bit number of the DAC 150 to 1 using the PWM 140 to minimize a noise effect of the DAC 150, thereby improving the performance.

(51) Through the three methods, the required sampling frequency is lowered and the performance of the circuit of the lower power modulator 100 is optimized to implement a system having a function of converting an input current of a broadband (100 dB or more) to a digital value with low power consumption.

(52) Referring to FIG. 3, that is, minimum recognizable signal power may be confirmed through Equations 1 to 3 above.

(53) The lower power modulator 100 according to the present disclosure may convert a smaller value than the signal size, and as a result, it can be confirmed that the lower power modulator 100 may convert all inputs of about 120 dB, that is, 1.sub.pA to 1.sub.uA.

(54) Here, as a result of simulation by adding noise emitted from the circuit of the lower power modulator 100, it can be seen that AC inputs of about 100 dB (10.sub.pA to 1.sub.uA) reduced by about 20 dB can be converted.

(55) FIGS. 4A and 4B are diagrams illustrating a noise simulation model of the low power modulator 100 with the VCO quantizer according to an embodiment of the present disclosure. FIGS. 5A and 5B are diagrams showing a noise performance graph of the low power modulator 100 with the VCO quantizer according to an embodiment of the present disclosure.

(56) Referring to FIGS. 4A and 4B, the low power modulator 100 may include a noise 401 of the DAC 150, a noise 402 of the integrator 110, a noise 403 of the quantizer 120, a quantization error 404, a truncate error 405, and a jitter error.

(57) In this case, referring to FIGS. 5A and 5B, a wide dynamic range (DR) and a high spurious free dynamic range (SFDR) (100 dB>,10.sub.pA to 1.sub.uA) may be confirmed.

(58) Further, a bandwidth (BW) of 1 to 0.5 KHz for a spike signal may be confirmed and low power consumption (to 1 uW) may be confirmed.

(59) According to the present disclosure, as compared to an environment where existing optical microscopes are required, experiments using an IC chip may provide more excellent research convenience to biotechnologists.

(60) The low power modulator 100 according to the present disclosure can be used for a longer time than a conventional IC chip with the same battery to increase the persistence to the activity, thereby providing further improved convenience.

(61) Further, the low power modulator 100 according to the present disclosure may be applied to measure an electrical signal as well as a fluorescent signal using a photodiode to measure all wide input currents and can be used in various fields due to a wide application range up to measurement of power consumption of a low power system and measurement of electrical characteristics of a low power device.

(62) The above description is only to illustratively describe the technical idea of the present disclosure, and those skilled in the art can make various modification and changes in a range without departing from the intrinsic features of the present disclosure.

(63) Therefore, the embodiments of the present disclosure are not intended to limit the technical idea of the present disclosure, but illustrative, and the scope of the present disclosure is not limited to the embodiments.

(64) The protective scope of the present disclosure should be construed based on the appended claims, and all technical ideas in the equivalent scope thereto should be construed as falling within the scope of the present disclosure.