METHOD FOR CHECKING A SEMICONDUCTOR SWITCH FOR A FAULT

Abstract

The invention provides a method for checking a semiconductor switch for a fault, wherein the semiconductor switch is driven with a PWM signal with a variable duty cycle. To the benefit of determining faults on the semiconductor switch reliably and cost-effectively, it is provided that if the semiconductor switch is operated with a duty cycle of 100% or 0%, the current measurement of the overall system is evaluated, while if the semiconductor switch is operated with a duty cycle of between 0% and 100%, the generated voltage pulses across the semiconductor switch are evaluated.

Claims

1. A method for checking a semiconductor switch for a fault, in which the semiconductor switch is driven with a PWM signal with variable duty cycle, wherein when the semiconductor switch is operated with a duty cycle of 100% or 0% the current measurement of the overall system is evaluated, while when the semiconductor switch is operated with a duty cycle between 0% and 100% the voltage pulses generated across the semiconductor switch are evaluated.

2. The method as claimed in claim 1, wherein the voltage pulses generated across the semiconductor switch are counted for the evaluation, and as a result of the evaluation a short circuit or an open circuit of the semiconductor switch is detected if the latter does not generate voltage pulses.

3. The method as claimed in claim 2, wherein at a duty cycle of 100% or 0% the evaluation is aborted and a fault is determined via the current measurement of the overall system.

4. A device for carrying out the method as claimed in claim 1, wherein the voltage pulses generated across the semiconductor switch (S3) are tapped off it via a capacitor (C4) and applied to an A/D converter (Q1, Q2), which applies a digital signal (Timer) to the counter input of a controller for the evaluation.

5. The device as claimed in claim 4, wherein the voltage pulses tapped off by the capacitor are converted by a diode (D4) into positive pulses that are applied to the A/D converter (Q1, Q2).

Description

[0020] In the following the invention is explained in more detail on the basis of the drawings, in which:

[0021] FIG. 1 shows the circuit diagram of a first embodiment of the device according to the invention for carrying out the method according to the invention for checking a semiconductor switch for a fault, and

[0022] FIG. 2 shows a schematic drawing of a modification of the device of FIG. 1 for checking a circuit with two semiconductor switches for a fault.

[0023] The device shown in FIG. 1 is based on a circuit for checking a semiconductor switch for a fault, in which the semiconductor switch is driven with a variable duty-cycle PWM signal. The collector of the semiconductor switch S3 is connected to a positive voltage HV+ via a load resistor HC3 and the other side of the switch is connected to a ground GND_HC. A PWM signal is applied at the input of the semiconductor switch.

[0024] A capacitor C4 filters out the voltage pulses from the collector of the semiconductor switch, which are produced in the PWM-switching case, since only these are required for the diagnosis of the switch. This circuit configuration provides the additional advantage that the rest of the circuit is not permanently connected to the supply potential, but is only loaded by individual pulses. This can significantly reduce the component count, as no continuous losses are generated.

[0025] The capacitor is connected to ground GND_HC via a voltage divider comprising a resistor R10 and a resistor R7. This voltage divider divides the generated voltage pulses down to lower values and reduces the pulse current through C4.

[0026] The pulses transmitted by the capacitor C4 are forwarded via a diode D1 to a subsequent signal conditioning stage as positive pulses. At this point, other diagnostic branches, not shown, can be linked at their cathodes (provided they have a phase offset) to form a disjunction (OR logic gate).

[0027] A Zener diode D9 connected after the OR gate protects the subsequent signal conditioning means against overvoltage. The said means comprises two transistors Q1 and Q2, which are connected to a simple A/D converter via resistors R18, R11 and R6 and R9 respectively, and generates a digital signal “Timer” from the positive pulse at the cathode of diode D9, which is fed to the counter input of a controller, not shown. On the controller, the diagnosis of the semiconductor switch is performed at the software level, wherein the incoming “Timer” pulses are counted. In the event of a fault on the semiconductor switch, no pulses are generated either in the case of a short circuit or an open circuit. This enables the software to detect the fault and to initiate appropriate measures.

[0028] At a duty cycle of 0% and 100%, this diagnosis at the software level is preferably switched off and a fault diagnosis is performed via the total current of the circuit.

[0029] The capacitor C4 generates only momentary current and voltage pulses in the diagnostic circuit. This allows the circuit to be implemented with a small number of low-cost components.

[0030] The functional principle of the circuit of FIG. 1 is shown in FIG. 2 for the case of simultaneous testing of two semiconductor switches for faults.