Abstract
A method for balancing thermal stresses in semiconductor switching devices may include (a) monitoring temperatures of the semiconductor switching devices to provide a temperature difference between two of the switching devices; and (b) based on the temperature difference, providing a zero-sequence component to be used for adjusting conduction times of each of the semiconductor devices.
Claims
1. In a multi-phase voltage source inverter, an apparatus for balancing thermal stresses in semiconductor switching devices, comprising: a monitor for monitoring temperatures of the semiconductor switching devices, the monitor providing a temperature difference between two of the switching devices; and a controller providing, based on the temperature difference, a zero-sequence component to be used for adjusting conduction times of each of the semiconductor devices.
2. The apparatus of claim 1, wherein the temperature difference corresponds to an upper switch and a lower switch in one of the phases of the multi-phase voltage source inverter.
3. The apparatus of claim 1, wherein one of two semiconductor switching devices of the temperature difference has the highest temperature among the semiconductor switching devices.
4. The apparatus of claim 1, wherein the multi-phase voltage source inverter comprises a three-phase voltage source inverter.
5. The apparatus of claim 1, wherein the conduction times are adjusted by increasing or decreasing a duty cycle of each of the semiconductor switching devices.
6. The apparatus of claim 1, wherein each phase of the multi-phase voltage source inverter provides an output phase signal that has a zero or near-zero frequency.
7. The apparatus of claim 6, wherein the output phase signal comprises an output phase current whose magnitude is substantially unaffected by the zero-sequence component.
8. In a multi-phase voltage source inverter, a method for balancing thermal stresses in semiconductor switching devices, comprising: monitoring temperatures of the semiconductor switching devices to provide a temperature difference between two of the switching devices; and based on the temperature difference, providing a zero-sequence component to be used for adjusting conduction times of each of the semiconductor devices.
9. The method of claim 8, wherein the temperature difference corresponds to an upper switch and a lower switch in one of the phases of the multi-phase voltage source inverter.
10. The method of claim 8, wherein one of two semiconductor switching devices of the temperature difference has the highest temperature among the semiconductor switching devices.
11. The method of claim 8, wherein the multi-phase voltage source inverter comprises a three-phase voltage source inverter.
12. The method of claim 8, wherein the conduction times are adjusted by increasing or decreasing a duty cycle of each of the semiconductor switching devices.
13. The method of claim 8, wherein each phase of the multi-phase voltage source inverter provides an output phase signal that has a zero or near-zero frequency.
14. The method of claim 13, wherein the output phase signal comprises an output phase current whose magnitude is substantially unaffected by the zero-sequence component.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIG. 1 is a schematic diagram of three-phase voltage source inverter 100 driving electric motor 106; three-phase voltage source inverter 100 may be used as a traction inverter.
[0012] FIG. 2 illustrates providing a positive output phase current from terminal 104-1 (i.e., phase A) under an SVPWM scheme.
[0013] FIG. 3 shows conductive periods (“duty cycles”) 301, 302 and 303 of switches 103-1, 103-3 and 103-5, respectively, under an SVPWM scheme.
[0014] FIG. 4 is a block diagram of control circuit 400 that enables a method that actively balances thermal stresses in the switches of a multi-phase voltage source inverter, based on a temperature difference between the upper and lower switches in the phase that provides the highest phase current, according to one embodiment of the present invention.
[0015] FIG. 5 illustrate adjusting duty cycles d.sub.A, d.sub.B and d.sub.C (i.e., duty cycle signals 301, 302 and 303 of FIG. 3) by zero-sequence component Δd to provide adjusted duty cycles d.sub.A+Δd, d.sub.B+Δd and d.sub.C+Δd in duty cycle signals 501, 502 and 503, respectively.
[0016] FIGS. 6(a), 6(b) and 6(c) illustrate an electric motor's hill-hold operation in which a 0 Hz torque is enabled by a three-phase voltage source inverter, according to one embodiment of the present invention.
[0017] FIGS. 7(a) and 7(b) illustrate a hold-hill operation at an output frequency of 0.1 Hz, enabled by a three-phase voltage source inverter, according to one embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0018] According to one embodiment of the present invention, in a multi-phase voltage source inverter operating at a near-zero output frequency, a control circuit implements a method (“the present control scheme”) that actively balances thermal stresses in the switches of the multi-phase voltage source inverter, based on a temperature difference between the upper and lower switches in the phase that supplies the highest output phase current. FIG. 4 is a block diagram of control circuit 400 that enables such a method in a three-phase voltage source inverter (e.g., three-phase voltage source inverter 100 of FIG. 1). In the three-phase voltage source inverter, control circuit 400 provides a zero-sequence adjustment to each of the duty cycle signals that drive the switches of the three-phase voltage source inverter. The zero-sequence adjustment is made at adder 404 to each duty cycle signal—i.e., each of duty cycles d.sub.A, d.sub.B and d.sub.C, for phases A, B and C, respectively. In FIG. 4, the pre-adjusted duty cycle signals are provided, for example, by conventional motor control circuit 405.
[0019] As shown in FIG. 4, control circuit 400 receives from temperature sensors temperature signals 407, each indicating a temperature at one of the six switches of the three-phase voltage source inverter. Alternatively, temperature signals 407 may be generated from temperature estimates. Temperature signals 407 are received into temperature monitoring and phase selection circuit 401, which monitors temperature signals 407 and selects therefrom the phase that corresponds to the switch that has the highest temperature. The temperature difference between the upper switch and the lower switch of that phase is provided to controller 403, which may be any suitable proportional (P) or proportional-integral (PI) controller. Controller 403 provides zero-sequence component Δd that is added to each of duty cycles d.sub.A, d.sub.B and d.sub.C, as illustrated in FIG. 5.
[0020] FIG. 5 illustrate adjusting duty cycles d.sub.A, d.sub.B and d.sub.C (i.e., duty cycle signals 301, 302 and 303 of FIG. 3) by zero-sequence component Δd to provide adjusted duty cycles d.sub.A+Δd, d.sub.B+Δd and d.sub.C+Δd in duty cycle signals 501, 502 and 503, respectively. As shown in FIG. 5, zero-sequence component Δd may be positive or negative, corresponding to a resulting increase or decrease of the duty cycle. In this manner, the conduction times of the upper and the lower switches in each phase are adjusted to balance their respective thermal stress. As one of ordinary skill in the art knows, adjusting each phase with a zero-sequence component maintains its output phase current.
[0021] FIGS. 6(a), 6(b) and 6(c) illustrate an electric motor's hill-hold operation in which a 0 Hz torque is enabled by a three-phase voltage source inverter, according to one embodiment of the present invention. FIG. 6(a) shows the duty cycles of the upper switches of phases A, B and C in a three-phase voltage source inverter; waveform 601 represents the duty cycle of the upper switch in phase A and waveform 602 represents both the duty cycles of the upper switches in phases B and C. FIG. 6(b) shows temperatures 611 and 612 of the upper and the lower switches, respectively, over the same time period. FIG. 6(c) shows phase A output current, also over the same time period.
[0022] As shown in FIGS. 6(a), 6(b) and 6(c), initially, at time to, phase A has a 0.55 duty cycle, with a peak phase A output current of 300 A, and phases B and C each have a 0.45 duty cycle. Because of its duty cycle and because phase A's output phase current is positive, more current flows through the upper switch's IGBT, causing greater thermal stress to the phase A upper switch, relative to other switches in the three-phase voltage source inverter. Thus, FIG. 6(b) shows that temperature 611 (i.e., the temperature of phase A's upper switch) is 30° C. higher than temperature 612 (i.e., the temperature of phase A's lower switch). Then, at time t.sub.1, approximately 1.2 seconds from time to, the present control scheme decreases the duty cycles of the upper switches in all three phases by an equal amount. With a lesser current through the IGBT of phase A's upper switch, the temperatures between phase A's upper switch and phase A's lower switch converge. At time t.sub.2, the present control scheme is disabled, such that the temperature difference between phase A's upper and lower switches widens, becoming 30° C. again over time. The present control scheme becomes active again at time t.sub.3. During the timer period that the present control scheme is enabled (i.e., between times t.sub.1 and t.sub.2), phase A's output phase current does not change, as expected and desired.
[0023] FIGS. 7(a) and 7(b) illustrate a hold-hill operation at an output frequency of 0.1 Hz, enabled by a three-phase voltage source inverter, according to one embodiment of the present invention. In this example, as shown in FIG. 7(b), phase A's peak output phase current is also at 300 A, just as in the example of FIGS. 6(a), 6(b) and 6(c). Because the output phase current has a period of 10 seconds, which is longer than the thermal time constant of the power module, FIG. 7(a) shows that the temperatures of all six switches of the three-phase voltage source inverter reach their respective peak values in regular succession. For each phase, as the temperature of the upper switch reaches its peak, the temperature of the lower switch reaches its peak value, which is about 30° C. lower than the temperature of its corresponding upper switch. As shown in FIG. 7(a), at time t.sub.1, the present control scheme is enabled, resulting in a narrowing of the difference in peak temperatures between the upper and the lower switches. The stresses on the upper and the lower switches thus become more balanced. As shown in FIG. 7(b), during the active period of the present control scheme, phase A's output phase current does not change.
[0024] As compared to conventional SVPWM and DPWM schemes, the present control scheme actively balances the thermal stresses among the upper and lower devices of the different phases. The resulting reduced device thermal stress extends the lifetimes of the switches in a multi-phase voltage source inverter. The present control scheme provides an increase output torque in hill-hold operations.
[0025] The above detailed description is provided to illustrate specific embodiments of the present invention and is not intended to be limiting. Numerous modifications and variations within the scope of the present invention are possible. The present invention is set forth in the accompanying claims.
