CONTROL METHOD FOR SWITCHES BASED ON DUAL PHASE MATERIALS

Abstract

The present disclosure relates to a switch system that provides a control method for switches based on dual-phase materials. The disclosed switch system includes a heat resistor, a power management (PM) unit configured to provide a control voltage at a voltage port coupled to the heat resistor, and a phase-change-based switch. Herein, the heat resistor is underneath the phase-change-based switch, and configured to generate heat energy from the control voltage and provide the heat energy to the phase-change-based switch. The phase-change-based switch is capable of being switched on and off by switching between a crystalline phase and an amorphous phase based on the heat energy provided by the heat resistor. The control voltage provided by the PM unit contains waveform information of target heat energy required for switching on and off the phase-change-based switch.

Claims

1. An apparatus comprising: at least one heat resistor; a power management (PM) unit configured to provide a control voltage at a voltage port, which is coupled to the at least one heat resistor; and at least one phase-change-based switch, wherein: the at least one heat resistor is underneath the at least one phase-change-based switch, and configured to generate heat energy from the control voltage and provide the heat energy to the at least one phase-change-based switch, wherein the at least one heat resistor is not electrically connected to the at least one phase-change-based switch; the at least one phase-change-based switch is capable of being switched on and off by switching between a crystalline phase and an amorphous phase based on the heat energy provided by the at least one heat resistor; and the control voltage provided by the PM unit contains waveform information of target heat energy required for switching on and off the at least one phase-change-based switch.

2. The apparatus of claim 1 further comprising a multiplexer (MUX), which is configured to select either a first ramp waveform or a second ramp waveform as a target voltage, wherein: the target voltage is provided to the PM unit, and the control voltage is provided based on the target voltage; the first ramp waveform corresponds to switching on the phase-change-based switch, and contains the waveform information of the target heat energy required for switching on the phase-change-based switch; and the second ramp waveform corresponds to switching off the phase-change-based switch, and contains the waveform information of the target heat energy required for switching off the phase-change-based switch.

3. The apparatus of claim 2 wherein the PM unit includes a tracking amplifier, a control unit, a multi-level voltage converter, and a power inductor, wherein: the tracking amplifier is configured to receive the target voltage, and configured to generate a tracked voltage based on the target voltage, wherein the control voltage is related to the tracked voltage; the multi-level voltage converter includes a multi-level charge pump (CP) configured to receive a battery voltage and generate a boosted voltage higher than the battery voltage, and a CP switch structure coupled between the multi-level CP and the power inductor; the control unit is configured to control a value of the boosted voltage generated by the multi-level CP, and configured to control the CP switch structure to provide the boosted voltage from the multi-level CP, the battery voltage, or zero voltage to the power inductor; and the power inductor is coupled between the CP switch structure of the multi-level voltage converter and the voltage port.

4. The apparatus of claim 3 wherein the control unit is one of a group consisting of a microprocessor, a microcontroller, a digital signal processor (DSP), and a field programmable gate array (FPGA).

5. The apparatus of claim 3 wherein: the PM unit further comprises an offset capacitor, which is coupled between the tracking amplifier and the voltage port; and the control voltage at the voltage port is equal to a summation of the tracked voltage generated by the tracking amplifier and an offset voltage across the offset capacitor.

6. The apparatus of claim 5, wherein: the control unit is configured to control the multi-level CP by comparing the tracked voltage from the tracking amplifier and the control voltage at the voltage port.

7. The apparatus of claim 5 wherein: the boosted voltage is equal to up to three times the battery voltage; and the offset voltage is equal to up to two times the battery voltage.

8. The apparatus of claim 7 wherein: the tracking amplifier is powered by the boosted voltage; and the control voltage is capable of having a maximum value up to five times the battery voltage.

9. The apparatus of claim 1 wherein the at least one phase-change-based switch is formed from a chalcogenide material.

10. The apparatus of claim 9 wherein the at least one phase-change-based switch is formed from germanium-antimony-tellurium, germanium-tellurium, or antimony-tellurium.

11. The apparatus of claim 1 wherein the at least one phase-change-based switch at the crystalline phase has a first impedance, and the at least one phase-change-based switch at the amorphous phase has a second impedance; and the second impedance is at least 20,000,000 times larger than the first impedance.

12. The apparatus of claim 1 wherein: the at least one heat resistor is formed of tungsten; and the at least one heat resistor has a width between 1 μm and 5 μm and a length between 2 μm and 10 μm.

13. The apparatus of claim 1 further comprising a plurality of field-effect transistor (FET) based switches, wherein: the at least one heat resistor includes a plurality of heat resistors; the at least one phase-change-based switch includes a plurality of phase-change-based switches, wherein each of the plurality of heat resistors is underneath a corresponding one of the plurality of phase-change-based switches, and configured to generate heat energy from the control voltage and provide the heat energy to the corresponding one of the plurality of phase-change-based switches; and the plurality of FET based switches is configured to selectively provide the control voltage to certain ones of the plurality of heat resistors.

14. The apparatus of claim 13 wherein each of the plurality of FET based switches is coupled in series with a corresponding one of the plurality of heat resistors.

15. The apparatus of claim 14 wherein: each of the plurality of FET based switches is a P-channel FET (PFET) based switch; and each of the plurality of FET based switches is coupled between the voltage port and a corresponding heat resistor.

16. The apparatus of claim 14 wherein: each of the plurality of FET based switches is a N-channel FET (NFET) based switch; and each of the plurality of FET based switches is coupled between a corresponding heat resistor and ground.

17. The apparatus of claim 13 further comprising a serial bus (SuBUS), which is configured to program when to close or open certain ones of the plurality of FET based switches.

18. The apparatus of claim 1 wherein each waveform of the target heat energy required for switching on or off the at least one phase-change-based switch has a duration of 0.5 μs to 2 μs.

19. An apparatus comprising: at least one heat resistor; a non-variable power management (PM) unit configured to provide a control voltage at a voltage port that is coupled to the at least one heat resistor, wherein the control voltage is fixed over time; at least one phase-change-based switch, wherein: the at least one heat resistor is underneath the at least one phase-change-based switch, and configured to generate heat energy from the control voltage and provide the heat energy to the at least one phase-change-based switch; and the at least one phase-change-based switch is capable of being switched on and off by switching between a crystalline phase and an amorphous phase based on the heat energy provided by the at least one heat resistor; and at least one N-channel field-effect transistor (NFET) based switch coupled between the at least one heat resister and ground, wherein a gate of the at least one NFET based switch is controlled by a gate control voltage, which contains waveform information of target heat energy required for switching on and off the at least one phase-change-based switch.

20. The apparatus of claim 19 further comprising at least one multiplexer (MUX), which is configured to select either a first ramp waveform or a second ramp waveform as the gate control voltage, wherein: the first ramp waveform corresponds to switching on the phase-change-based switch, and contains the waveform information of the target heat energy required for switching on the phase-change-based switch; and the second ramp waveform corresponds to switching off the phase-change-based switch, and contains the waveform information of the target heat energy required for switching off the phase-change-based switch.

21-35. (canceled)

Description

BRIEF DESCRIPTION OF THE DRAWING FIGURES

[0043] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0044] FIG. 1 illustrates a dual phase material at an amorphous phase and a crystalline phase.

[0045] FIG. 2 illustrates an exemplary switch system with a switch controller, which controls a switch based on a dual phase material, according to an embodiment of the present disclosure.

[0046] FIG. 3 illustrates a power management (PM) unit in the switch controller shown in FIG. 2.

[0047] FIG. 4 illustrates an exemplary switch system with a switch controller, which controls a number of switches, each based on a dual phase material, according to an embodiment of the present disclosure.

[0048] FIG. 5 illustrates an alternative switch system with a switch controller, which controls a number of switches, each based on a dual phase material, according to an embodiment of the present disclosure.

[0049] FIG. 6 illustrates another alternative switch system with a switch controller, which controls a number of switches, each based on a dual phase material, according to an embodiment of the present disclosure.

[0050] It will be understood that for clear illustrations, FIGS. 1-6 may not be drawn to scale.

DETAILED DESCRIPTION

[0051] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0052] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

[0053] It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

[0054] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0055] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0056] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0057] The present disclosure relates to a switch system that performs a control method for one or more switches based on dual phase materials. FIG. 2 illustrates an exemplary switch system 10 including a phase-change-based switch 12, a switch controller 14, and a heat resistor 16 with a resistance R.sub.HEAT according to an embodiment of the present disclosure. Herein, the phase-change-based switch 12 is a two-terminal (e.g., a first terminal T1_1 and a second terminal T2_1) switch, and may be formed from a chalcogenide material (e.g., germanium-antimony-tellurium, germanium-tellurium, or antimony-tellurium). The phase-change-based switch 12 is capable of achieving a radio frequency (RF) switching speed with a low insertion loss by utilizing heat energy with proper waveforms. At an “ON” state (i.e., at the crystalline phase), the phase-change-based switch 12 has a superior low impedance between the first terminal T1_1 and the second terminal T2_1, while at an “OFF” state (i.e., at the amorphous phase), the phase-change-based switch 12 has a superior high impedance between the first terminal T1_1 and the second terminal T2_1. In an unlimited example, the high impedance at the amorphous phase is at least 20,000,000 times greater than the low impedance at the crystalline phase. The phase-change-based switch 12 is connected to external circuitry (not shown) via the first terminal T1_1 and the second terminal T2_1.

[0058] The switch controller 14 is configured to provide electrical energy (i.e., a control voltage V.sub.CTRL) to the heat resistor 16, so as to close or open the phase- change-based switch 12. In detail, the switch controller 14 includes a power management (PM) unit 18 and a multiplexer (MUX) 20. The PM unit 18 is configured to provide the control voltage V.sub.CTRL to the heat resistor 16 based on two ramp waveforms (i.e., a first ramp waveform V.sub.RAMP1 and a second ramp waveform V.sub.RAMP2). Herein, the first ramp waveform V.sub.RAMP1 corresponds to switching from the “OFF” state to the “ON” state (i.e., from the amorphous state to the crystalline phase) of the phase-change-based switch 12, and the second ramp waveform V.sub.RAMP2 corresponds to switching from the “ON” state to the “OFF” state (i.e., from the crystalline phase to the amorphous phase) of the phase-change-based switch 12. The MUX 20 is configured to select either the first ramp waveform V.sub.RAMP1 or the second ramp waveform V.sub.RAMP2 for the PM unit 18 depending on switching on or switching off the phase-change-based switch 12, respectively.

[0059] The heat resistor 16 is placed underneath the phase-change-based switch 12, particularly underneath the chalcogenide portion of the phase-change-based switch 12. The heat resistor 16 may be formed of tungsten and may have a width between 1 μm and 5 μm and a length between 2 μm and 10 μm. The heat resistor 16 is configured to transfer the electrical energy to heat energy and configured to provide the heat energy to the phase-change-based switch 12. The heat energy provided by the heat resistor 16 is about equal to V.sub.CTRL.sup.2/R.sub.HEAT. As such, waveform requirements of target heat energy for switching on and switching off the phase-change-based switch 12 can be achieved by adjusting waveforms of the control voltage V.sub.CTRL. Typically, a waveform of target heat energy required for switching on the phase-change-based switch 12 and a waveform of target heat energy required for switching off the phase-change-based switch 12 may have different amplitudes and/or different durations. Each waveform required for switching on or off the phase-change-based switch 12 may have a duration of 0.5 μs to 2 μs.

[0060] The first ramp waveform V.sub.RAMP1 contains waveform information of the target heat energy required for switching on the phase-change-based switch 12, and the second ramp waveform V.sub.RAMP2 contains waveform information of the target heat energy required for switching off the phase-change-based switch 12. Since the waveforms of the target heat energy required for switching on and switching off the phase-change-based switch 12 might be different in amplitudes and/or durations, the first ramp waveform V.sub.RAMP1 and the second ramp waveform V.sub.RAMP2 may also be different in amplitudes and/or durations.

[0061] In some applications, the switch controller 14 may further include a serial bus (SuBUS) 22, which is configured to provide programmability to the switch controller 14 via a serial interface. The SuBUS 22 might be a single-wire bus.

[0062] FIG. 3 illustrates details of the PM unit 18 in the switch controller 14 shown in FIG. 2. The PM unit 18 includes a tracking amplifier 24, a control unit 26, a multi-level voltage converter 28, and a power inductor 30. In detail, the tracking amplifier 24 is configured to receive a target voltage V.sub.TAR, which is selected by the MUX 20 from the first ramp waveform V.sub.RAMP1 and the second ramp waveform V.sub.RAMP2. In addition, the tracking amplifier 24 receives a supply voltage V.sub.SUP as a power supply, and is configured to provide a tracked voltage V.sub.TRACK by tracking the target voltage V.sub.TAR. The supply voltage V.sub.SUP is no smaller than the target voltage V.sub.TAR over time to ensure proper operation of the tracking amplifier 24. As such, the supply voltage V.sub.SUP is no smaller than the tracked voltage V.sub.TRACK, which tracks the target voltage V.sub.TAR. In a non-limiting example, the tracking amplifier 24 is coupled to a voltage port P via an offset capacitor 32, where the voltage port P is electrically connected to the heat resistor 16 and the control voltage V.sub.CTRL is provided at the voltage port P. The offset capacitor 32 is configured to provide an offset voltage V.sub.OFFSET. The offset voltage V.sub.OFFSET, which may be precharged, may help raise the tracked voltage V.sub.TRACK to the control voltage V.sub.CTRL (V.sub.CTRL=V.sub.TRACK+V.sub.OFFSET) at the voltage port P, thus helping to lower the supply voltage V.sub.SUP required by the tracking amplifier 24 to improve power efficiency in the PM unit 18.

[0063] If the tracking amplifier 24 is coupled directly to the voltage port P without the offset capacitor 32, then the control voltage V.sub.CTRL will be the same as the tracked voltage V.sub.TRACK. In this regard, if a maximum value of the control voltage V.sub.CTRL at the voltage port P is required to be 5 V for example, the tracked voltage V.sub.TRACK produced by the tracking amplifier 24 will also be 5 V. Accordingly, the supply voltage V.sub.SUP needs to be at least 5 V. In contrast, if the tracking amplifier 24 is coupled to the voltage port P via the offset capacitor 32 that provides the 2 V offset voltage V.sub.OFFSET, then the tracking amplifier 24 would only need to produce the tracked voltage V.sub.TRACK at 3 V. As a result, the supply voltage V.sub.SUP may be reduced to 3 V as well, thus helping improve power efficiency in the PM unit 18.

[0064] In addition, the tracking amplifier 24 sources a tracked current I.sub.TRACK to the voltage port P through the offset capacitor 32. Since the offset capacitor 32 may block direct current (DC) and/or low-frequency alternate current (AC), the tracked current I.sub.TRACK from the tracking amplifier 24 to the voltage port P may include middle and/or high frequency AC portions. As such, the tracking amplifier 24 may provide middle and/or high frequency energy to the voltage port P.

[0065] Notice that the control voltage V.sub.CTRL is based on the target voltage V.sub.TAR (i.e., one of the first ramp waveform V.sub.RAMP1 and the second ramp waveform V.sub.RAMP2), which contains the waveform information of the target heat energy required for switching on/off the phase-change-based switch 12. Therefore, the control voltage V.sub.CTRL also contains the waveform information of the target heat energy for switching on/off the phase-change-based switch 12. By adjusting the target voltage V.sub.TAR, and consequently adjusting the control voltage V.sub.CTRL, the waveform requirements for switching on/off the phase-change-based switch 12 can be achieved, and thus the phase-change-based switch 12 is capable of operating properly.

[0066] The control unit 26 may be a microprocessor, a microcontroller, a digital signal processor (DSP), or a field programmable gate array (FPGA), for example. The multi-level voltage converter 28 includes a multi-level charge pump (CP) 34 and a CP switch structure 36. Herein, the multi-level CP 34 is configured to provide a boosted voltage V.sub.BOOST based on a battery voltage V.sub.BAT, and the CP switch structure 36 is configured to selectively output the boosted voltage V.sub.BOOST from the multi-level CP 34, the battery voltage V.sub.BAT, or zero voltage to the power inductor 30.

[0067] Comparing the tracked voltage V.sub.TRACK from the tracking amplifier 24 and the control voltage V.sub.CTRL at the voltage port P (representing that the offset capacitor 32 needs to be charged or discharged), the control unit 26 may be configured to control duty cycles of the multi-level CP 34 to change the value of the boosted voltage V.sub.BOOST. Typically, the boosted voltage V.sub.BOOST is higher than the battery voltage V.sub.BAT. In a non-limiting example, the boosted voltage V.sub.BOOST may be equal to two times or three times of the battery voltage V.sub.BAT (V.sub.BOOST=2V.sub.BAT/3V.sub.BAT)

[0068] The CP switch structure 36 is coupled between the multi-level CP 34 and the power inductor 30. In a non-limiting example, the CP switch structure 36 includes a single-pole three-throw (SP3T) switch, which is controlled by the control unit 26 to selectively connect to the multi-level CP 34, the battery voltage V.sub.BAT, or ground. As such, the CP switch structure 36 selectively outputs the boosted voltage V.sub.BOOST from the multi-level CP 34, the battery voltage V.sub.BAT, or zero voltage from ground to the power inductor 30. Notably, the CP switch structure 34 may be implemented by any number, type, and layout of switches without affecting functionalities of the CP switch structure 36.

[0069] The power inductor 30 is coupled between the CP switch structure 36 of the multi-level voltage converter 28 and the voltage port P. The voltage outputted by the CP switch structure 36 causes the power inductor 30 to induce an output current I.sub.L toward the voltage port P. As such, the control unit 26 is configured to control (e.g., increase/decrease) the output current I.sub.L to the voltage port P. Herein, since the power inductor 30 may block middle and/or high frequency AC, the output current I.sub.L from the power inductor 30 may include DC and/or low frequency AC portions. Therefore, the multi-level voltage converter 28 and the power inductor 30 may provide low frequency energy to the voltage port P.

[0070] In one embodiment, the boosted voltage V.sub.BOOST generated from the multi-level CP 34 is applied as the supply voltage V.sub.SUP of the tracking amplifier 24. Therefore, the maximum value of the target voltage V.sub.TAR and consequently, the tracked voltage V.sub.TRACK is the boosted voltage V.sub.BOOST. Furthermore, the maximum value of the control voltage V.sub.CTRL is V.sub.BOOST+V.sub.OFFSET. If the V.sub.BOOST can achieve up to 3*V.sub.BAT, and the V.sub.OFFSET can be charged up to 2*V.sub.BAT, the control voltage V.sub.CTRL can reach as high as 5*V.sub.BAT. As such, even with a low battery voltage V.sub.BAT (e.g., 2.5V), a large transient peak power (e.g., 12-20 Watts) can still be delivered to the phase-change-based switch 12 during a short pulse period (e.g., 0.5 μs to 2 μs).

[0071] In some applications, a switch system may provide a control method for multiple phase-change-based switches. FIG. 4 illustrates an exemplary switch system 40 including a number of phase-change-based switches 42 (e.g., a first phase-change-based switch 42_1, . . . , and a M.sup.th phase-change-based switch 42_M), a switch controller 44, and a number of heat resistors 46 (e.g., a first heat resistor 46_1, . . . , and a M.sup.th heat resistor 46_M) according to an embodiment of the present disclosure. Herein, each phase-change-based switch 42 is a two-terminal (e.g., a corresponding first terminal T1_# and a corresponding second terminal T2_#) switch, and is formed from a chalcogenide material (e.g., germanium-antimony-tellurium, germanium-tellurium, or antimony-tellurium). Each phase-change-based switch 42 is capable of achieving a RF switching speed with a low insertion loss by utilizing heat energy with proper waveforms. At an “ON” state (i.e., at the crystalline phase), each phase-change-based switch 42 has a superior low impedance between the first terminal T1_# and the second terminal T2_#, while at an “OFF” state (i.e., at the amorphous phase), each phase-change-based switch 42 has a superior high impedance between the first terminal T1_# and the second terminal T2_#. Each phase-change-based switch 42 is connected to external circuitry (not shown) via the first terminal T1_# and the second terminal T2_#.

[0072] Each heat resistor 46 is placed underneath a corresponding phase-change-based switch 42. Each heat resistor 46 is configured to transfer electrical energy (i.e., the control voltage V.sub.CTRL) to heat energy and provide the heat energy to the corresponding phase-change-based switch 42. Each heat resistor 46 may be formed of tungsten and may have a width between 1 μm and 5 μm and a length between 2 μm and 10 μm.

[0073] The switch controller 44 is configured to provide electrical energy (i.e., the control voltage V.sub.CTRL) to the heat resistors 46, so as to close or open the phase-change-based switch 42. Similar as the switch controller 14, the switch controller 44 also includes the PM unit 18 and the MUX 20. Besides, the switch controller 44 further includes a number of P-channel field-effect transistor (PFET) based switches 48 (e.g., a first PFET based switch 48_1, . . . , and a M.sup.th PFET based switch 48_M), each of which is coupled between the PM unit 18 and a corresponding heat resistor 46. The PFET based switches 48 are configured to selectively provide the control voltage V.sub.CTRL to the heat resistors 46. As such, each heat resistor 46 can be heated simultaneously or alone by the control voltage V.sub.CTRL, and consequently, the corresponding phase-change-based switch 42 can switch on/off simultaneously or alone.

[0074] FIG. 5 illustrates an alternative switch system 40A with an alternative switch controller 44A. Compared to the switch controller 44, the alternative switch controller 44A utilizes a number of N-channel FET (NFET) based switches 52 (e.g., a first NFET based switch 52_1, . . . , and a M.sup.th NFET based switch 52_M) instead of PFET based switches 48 to selectively provide the control voltage V.sub.CTRL to the heat resistors 46. In the alternative switch controller 44A, each heat resistor 46 is directly connected to the PM unit 18, and each NFET based switch 52 is coupled between a corresponding heat resistor 46 and ground. As such, each heat resistor 46 can be heated simultaneously or alone by the control voltage V.sub.CTRL, and consequently, the corresponding phase-change-based switch 42 can switch on/off simultaneously or alone.

[0075] As illustrated in FIGS. 4 and 5, the PFET based switches 48/the NFET based switches 52 are included in the switch controller 44/44A, and can be programmed by the SuBUS 22 (e.g., programming when to close certain PFET based switch(es)/certain NFET based switch(es)). In some applications, the PFET based switches 48/the NFET based switches 52 may not be included in the switch controller 44/44A and not controlled by the SuBUS 22 (e.g., fabricating the PFET based switches 48/the NFET based switches 52 simultaneously with the phase-change-based switch 42).

[0076] As described above, the control voltage V.sub.CTRL generated by the PM unit 18 will vary over time to achieve waveform requirements of the target heat energy for switching on and switching off the phase-change-based switches 42, and will be identical for each phase-change-based switch 42. FIG. 6, on the other hand, illustrates another switch system 60, which utilizes variable resistance instead of variable voltage to achieve waveform requirements for switching on and switching off the phase-change-based switches. The switch system 60 includes a number of phase-change-based switches 62 (e.g., a first phase-change-based switch 62_1, . . . , and a M.sup.th phase-change-based switch 62_M), a switch controller 64, and a number of heat resistors 66 (e.g., a first heat resistor 66_1, . . . , and a M.sup.th heat resistor 66_M).

[0077] Each phase-change-based switch 62 is a two-terminal (e.g., a corresponding first terminal T1_# and a corresponding second terminal T2_#) switch, and is formed from a chalcogenide material (e.g., germanium-antimony-tellurium, germanium-tellurium, or antimony-tellurium). Each phase-change-based switch 62 is capable of achieving a RF switching speed with a low insertion loss. At an “ON” state (i.e., at the crystalline phase), each phase-change-based switch 62 has a superior low impedance between the first terminal T1_# and the second terminal T2_#, while at an “OFF” state (i.e., at the amorphous phase), each phase-change-based switch 62 has a superior high impedance between the first terminal T1_# and the second terminal T2_#. Each phase-change-based switch 62 is connected to external circuitry (not shown) via the first terminal T1_# and the second terminal T2_#.

[0078] Each heat resistor 66 is placed underneath a corresponding phase-change-based switch 62 and configured to transfer electrical energy to heat energy and provide the heat energy to the corresponding phase-change-based switch 62. Each heat resistor 66 may be formed of tungsten and may have a width between 1 μm and 5 μm and a length between 2 μm and 10 μm.

[0079] The switch controller 64 is configured to provide electrical energy to the heat resistors 66, so as to close or open the phase-change-based switch 62. In detail, the switch controller 64 includes a non-variable PM unit 68, a number of MUXs 70 (e.g., a first MUX 70_1, . . . , and a M.sup.th MUX_M), a number of NFET based switches 72 (e.g., a first NPET based switch 72_1, . . . , and a M.sup.th NFET based switch 72_M), and a SuBUS 73.

[0080] Different from the PM unit 18, which provides the control voltage V.sub.CTRL varying over time, the non-variable PM unit 68 is configured to provide a fixed control voltage V.sub.CTRL_FIX. Herein, the fixed control voltage V.sub.CTRL_FIX does not change over time. The non-variable PM unit 68 includes a multi-level voltage converter 74, a control unit 76, a power inductor 78, and an offset capacitor 80. The multi-level voltage converter 74 has a same configuration as the multi-level voltage converter 28 described above. The multi-level voltage converter 74 includes a multi-level CP 82 and a CP switch structure 84. Herein, the multi-level CP 82 is configured to provide a boosted voltage V.sub.BOOST based on a battery voltage V.sub.BAT, and the CP switch structure 82 is configured to selectively output the boosted voltage V.sub.BOOST from the multi-level CP 34, the battery voltage V.sub.BAT, or zero voltage to the power inductor 78. In a non-limiting example, the boosted voltage V.sub.BOOST may be equal to two times or three times the battery voltage V.sub.BAT (V.sub.BOOST=2V.sub.BAT/3V.sub.BAT).

[0081] The control unit 76 is configured to control duty cycles of the multi-level CP 82 to change the value of the boosted voltage V.sub.BOOST, and configured to control the CP switch structure 84 to select a desired voltage level. The control unit 76 controls the multi-level CP 82 depending on the fixed control voltage V.sub.CTRL_FIX at the voltage port. The control unit 76 may be a microprocessor, a microcontroller, a DSP, a FPGA, or a pulse-width modulation (PWM) analog circuit controller, for example. The power inductor 78 is coupled between the CP switch structure 74 of the multi-level voltage converter 74 and a voltage port P, at which the fixed control voltage V.sub.CTRL_FIX is provided. The maximum value of the fixed control voltage V.sub.CTRL_FIX can reach as high as 3*V.sub.BAT (i.e., maximum of V.sub.BOOST). The offset capacitor 80 is coupled between the voltage port P and ground and can be charged up to V.sub.BOOST (i.e., maximum 3*Vbat) or discharged to ground.

[0082] Notice that the fixed control voltage V.sub.CTRL_FIX does not track any waveform information of the target heat energy required for switching on/off the phase-change-based switches 62. Instead, once the control unit 76 determines a boosting value of the multi-level CP 82 (e.g., 2V.sub.BAT or 3V.sub.BAT) and a voltage choice of the CP switch structure 84 (e.g., V.sub.BOOST, V.sub.BAT, or ground), the fixed control voltage V.sub.CTRL_FIX is fixed over time.

[0083] Each NFET based switch 72 and a corresponding heat resistor 66 are coupled in series between ground and the voltage port P. Each MUX 70 is electrically coupled to a gate of a corresponding NFET based switch 72 and configured to provide a gate control voltage V.sub.CTRL_G (e.g., a first gate control voltage V.sub.CTRL_G1, . . . , or a M.sup.th gate control voltage V.sub.CTRL_GM) to control the corresponding NFET based switch 72. Each NFET based switch 72 is capable of being fully closed (i.e., a very low resistance), partially closed (i.e., a medium resistance), or fully opened (i.e., a very high resistance) depending on the amplitude of the corresponding gate control voltage V.sub.CTRL_G. As such, each gate control voltage V.sub.CTRL_G can change a resistance value between the voltage port P and ground. Since the fixed control voltage V.sub.CTRL_FIX has a fixed value over time, current flowing through each heat resistor 66, and consequently heat generated by each heat resistor 66, can change according on the variation of the corresponding control voltage V.sub.CTRL_G. Therefore, each phase-change-based switch 62 is capable of switching on and switching off by the variation of the corresponding control voltage V.sub.CTRL_G.

[0084] Herein, each gate control voltage V.sub.CTRL_G is selected from a corresponding ramp waveform pair V.sub.RAMP1 and V.sub.RAMP2 (e.g., a first ramp waveform pair V.sub.RAMP1_1 and V.sub.RAMP2_1, . . . , or a M.sup.th ramp waveform pair V.sub.RAMP1_M and V.sub.RAMP2_M). Each ramp waveform pair contains waveform information of the target heat energy required for switching on and switching off the corresponding phase-change-based switch 62. Therefore, each gate control voltage V.sub.CTRL_G also contains the waveform information of the target heat energy required for switching on or switching off the corresponding phase-change-based switch 62. By adjusting each ramp waveform pair V.sub.RAMP1 and V.sub.RAMP2, and consequently adjusting each gate control voltage V.sub.CTRL_G, the waveform requirements for switching on/off the corresponding phase-change-based switch 62 can be achieved.

[0085] Each ramp waveform pair may be the same or different depending on the corresponding phase-change-based switch 62. In addition, by utilizing multiple MUXs 70, different phase-change-based switches 62 may perform different switching operations at a same time. For instance, the first MUX 70_1 selects V.sub.RAMP1_1 for the first phase-change-based switch 62_1, and the first phase-change-based switch 62_1 turns from “ON” to “OFF”. Simultaneously, the M.sup.th MUX 70_M selects V.sub.RAMP2_M for the M.sup.th phase-change-based switch 62_M, and the M.sup.th phase-change-based switch 62_M turns from “OFF” to “ON”.

[0086] The SuBUS 73 is configured to provide programmability to the switch controller 64 via a serial interface. The SuBUS 73 might be a single-wire bus. In one embodiment, each MUX 70 can be programmed by the SuBUS 73 (e.g., programming each MUX 70 to select a certain ramp waveform as a gate control voltage at a certain time).

[0087] In some applications, there might be only one phase-change-based switch 62 (instead of multiple phase-change-based switches 62) in the switch system 60. Accordingly, there will be only one heat resistor 66 (instead of multiple heat resistors 66), and one MUX 70 (instead of multiple MUXs 70) and one NFET based switch 72 (instead of multiple NFET based switches 72) in the switch controller 64 (not shown).

[0088] Note that in all embodiments, the offset capacitor 32/80 and capacitors in the multi-level CP 34/82 can be precharged before the switch controller 14/44/44A/62 provides electrical energy to the heat resistor(s) 16/46/66, so as to reduce switching delays for the phase-change-based switch 12/42/62.

[0089] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.