AUTOMATIC TUNING OF A PROPORTIONAL-INTEGRAL-DERIVATIVE CONTROLLER FOR DC-DC BUCK SWITCHING POWER CONVERTER

Abstract

A method of automatically tuning a proportional-integral-derivative (PID) controller (102) controlling a DC-DC converter (100) includes substituting the PID controller (102) with a modified relay feedback test (MRFT) (104) controller having a threshold parameter (β) and a magnitude parameter (h), iteratively determining a current error signal (e [k]) by measuring an output voltage (Vo[k]) of the DC-DC converter (100) and comparing it to a desired reference output voltage (Vo-ref), input the error signal (e[k]) to the MRFT (104), determining an output value (u[k]) of the MRFT, update the duty cycle (D) based on the output value (u[k]), operating the DC-DC converter (100) using the updated duty cycle (D), exciting oscillations in the loop containing the MRFT (104) and the DC-DC converter (100), measuring a frequency (Ω0) and amplitude (α0) of the output voltage (Vo[k]), updating PID controller parameters based on the frequency (Ω0) and amplitude (α0), and substituting the MRFT (104) with the PID controller (102).

Claims

1. A method of automatically tuning a proportional-integral-derivative (PID) controller controlling a DC-DC buck switching power converter, comprising: a) substituting the PID controller with a modified relay feedback test (MRFT) block having an MRFT magnitude (h) and a threshold parameter (β); b) determining a current error signal (e[k])by measuring an output voltage (V.sub.o[k]) of the DC-DC buck switching power converter and comparing the output voltage (v.sub.o) to a desired reference output voltage (V.sub.o-ref); c) inputting the error signal (e[k]) to the MRFT block; d) producing a MRFT block output signal u[k] in accordance with the MRFT block equations, which can only be D+h or D−h; e) operating the DC-DC buck switching power converter using the updated nominal duty cycle (D); f) repeating steps from b) through e), which results in generation of self-excited oscillations due to the switching of the MRFT block output between the values D+h and D−h, until a predefined number of cycles (N.sub.cycles) is observed; g) measuring a frequency (Ω.sub.0) and amplitude (a.sub.0) of oscillations of the output voltage (V.sub.o[k]) of the DC-DC buck switching power converter; h) updating PID controller parameters based on the frequency (Ω.sub.0) and amplitude (a.sub.0) of the oscillations of the voltage output (V.sub.o[k]) of the DC-DC buck switching power converter; and i) substituting the MRFT block with the PID controller.

2. The method according to claim 1, further comprising: j) comparing the error signal (e[k]) against previous maximum and minimum values of the error signal (e.sub.max, e.sub.min); k) determining a new maximum value (e.sub.max) if the current error signal value (e[k]) is greater than the previous maximum value; l) determining a new minimum value (e.sub.min) if the current error signal value (e[k]) is less than the previous minimum value; and m) determining the current value of the MRFT block output signal (u[k]) based on the new maximum or minimum value (e.sub.max, e.sub.min), the previous value of the MRFT block output signal (u[k−1]), the current error signal value (e[k]), and the MRFT block threshold parameter (β) and magnitude (h) in such a way that the current value of the MRFT block output signal (u[k]) is set to be D+h if (e[k]≥−β×e.sub.min and u[k−1]=D−h) or if (e[k]≥−β×e.sub.max and u[k−1]=D+h); and the current value of the MRFT block output signal (u[k]) is set to be D−h if (e[k]≤−β×e.sub.max and u[k−1]=D+h) or if (e[k]≤−β×e.sub.min and u[k−1]=D−h)

3. The method according to claim 2, wherein an initial number of cycles (N.sub.discard) are disregarded when measuring the frequency (Ω.sub.0) and amplitude (a.sub.0) of the oscillations of the output voltage (V.sub.o[k]) of the DC-DC buck switching power converter (step g).

4. The method according to claim 3, wherein the PID controller parameters are updated based on a number of recorded cycles (N.sub.MRFT) which equals a total number of cycles (N.sub.cycles) minus the initial number of cycles (N.sub.discard), an elapsed time period (T.sub.MRFT) of the number of recorded cycles (N.sub.MRFT), and the frequency (Ω.sub.0), where ${\Omega }_0=\frac{2\pi }{\frac{T_{\mathrm{MRFT}}}{N_{\mathrm{MRFT}}}}.$

5. The method according to claim 4, wherein the PID controller parameters are updated based on the amplitude (a.sub.0) where $a_0=\frac{.Math.N_{\mathrm{MRFT}}{e}_{\max }+.Math.N_{\mathrm{MRFT}}.Math.e_{\min }.Math.}{2N_{\mathrm{MRFT}}}.$

6. The method according to claim 5, further comprising the step of: n) calculating a proportional gain (K.sub.c), an integral time (T.sub.i), and a derivative time (T.sub.d) for the PID controller, where: $K_c=c_1\frac{4h}{\pi a_0},T_i=c_2\frac{2\pi }{{\Omega }_0},T_d=c_3\frac{2\pi }{{\Omega }_0}.$

7. The method according to claim 6, where c.sub.1=0.69±5%, c.sub.2=1.14±5%, and c.sub.3=0.19±5%.

8. The method according to claim 6, in which the coefficients c.sub.1, c.sub.2, and c.sub.3 are selected to satisfy the equations: c.sub.1√{square root over (1+ζ.sup.2)}=1 and β=sin(ϕ.sub.m−tan.sup.−1ζ), where $\xi =2\pi c_3-\frac{1}{2\pi c_2}$ and (ϕ.sub.m) is a desired phase margin;

9. The method according to claim 1, where a threshold parameter β=−0.2±5%.

10. A non-transitory computer readable storage medium having data stored therein representing software executable by a computer, the software including instructions to: switch a controller circuit of a DC-DC buck switching power converter from a proportional-integral-derivative (PID) controller enforcing a nominal duty cycle (D) of the converter to a modified relay feedback test (MRFT) block having an MRFT magnitude (h) and a threshold parameter (β); determine a current error signal (e[k]) by measuring an output voltage (V.sub.o[k]) of the DC-DC buck switching power converter and comparing the output voltage (V.sub.o[k]) to a desired reference output voltage (V.sub.o-ref); input the error signal (e[k]) to the MRFT block; determine a controller output signal (u[k]) of the MRFT block; update the nominal duty cycle (D) to the value given by the controller output signal (u[k]); operate the DC-DC buck switching power converter using the updated nominal duty cycle (D); observe appearance of self-excited oscillations and repeat the preceding instructions for a predetermined number of cycles (N.sub.cycles) of these oscillations; measure a frequency (Ω.sub.0) and amplitude (a.sub.0) of oscillations of the output voltage (V.sub.o[k]) of the DC-DC buck switching power converter; update PID controller parameters based on the frequency (Ω.sub.0) and amplitude (a.sub.o) of the oscillations of the voltage output (V.sub.o[k]) of the DC-DC buck switching power converter; and switch the controller circuit of the DC-DC buck switching power converter from a MRFT block to the PID controller.

11. The non-transitory computer readable storage medium according to claim 10, wherein the software further includes instructions to: compare the error signal (e[k]) against previous maximum and minimum values of the error signal (e.sub.max, e.sub.min); store a new maximum value (e.sub.max) in transitory memory if the current error signal value (e[k]) is greater than the previous maximum value; store a new minimum value (e.sub.min) in transitory memory if the current error signal value (e[k]) is less than the previous minimum value; and calculate current value of the MRFT block output signal (u[k]) based on the new maximum or minimum value (e.sub.max, e.sub.min), the previous value of the MRFT block output signal (u[k−1]), the current error signal value (e[k]), and the MRFT block threshold parameter (β) and magnitude (h) in such a way that the current value of the MRFT block output signal (u[k]) is set to be D+h if (e[k]≥−β×e.sub.min and u[k−1]=D−h) or if (e[k]≥−β×e.sub.maxu[k−1]=D+h); and the current value of the MRFT block output signal (u[k]) is set to be D−h if (e[k]≤−β×e.sub.max and u[k−1]=D−h) or if (e[k]≤−β×e.sub.min and u[k−1]=D−h), and store it in transitory memory.

12. The non-transitory computer readable storage medium according to claim 10, wherein the software further includes instructions to discard the frequency (Ω.sub.0) and amplitude (a.sub.0) of the oscillations of the output voltage (V.sub.o[k]) of the DC-DC buck switching power converter data collected during an initial number of cycles (N.sub.discard).

13. The non-transitory computer readable storage medium according to claim 12, wherein the software further includes instructions to update the PID controller parameters based on a number of recorded cycles (N.sub.MRFT) which equals a total number of cycles (N.sub.cycles) minus the initial number of cycles (N.sub.discard), an elapsed time period (T.sub.MRFT) of the number of recorded cycles (N.sub.MRFT), and the frequency (Ω.sub.0), where ${\Omega }_0=\frac{2\pi }{\frac{T_{\mathrm{MRFT}}}{N_{\mathrm{MRFT}}}},$

14. The non-transitory computer readable storage medium according to claim 13, wherein the software further includes instructions to update the PID controller parameters based on the amplitude (a.sub.0) where $a_0=\frac{.Math.N_{\mathrm{MRFT}}{e}_{\max }+.Math.N_{\mathrm{MRFT}}.Math.e_{\min }.Math.}{2N_{\mathrm{MRFT}}}.$

15. The non-transitory computer readable storage medium according to claim 14, wherein the software further includes instructions to calculate a proportional gain (K.sub.c), T.sub.i an integral time (T.sub.i), and a derivative time (T.sub.d) for the PID controller, where: $K_c=c_1\frac{4h}{\pi a_0},T_i=c_2\frac{2\pi }{{\Omega }_0},T_d=c_3\frac{2\pi }{{\Omega }_0}.$

16. The non-transitory computer readable storage medium according to claim 15 having data stored therein representing a value of c.sub.1 as 0.69±5%, a value of c.sub.2 as 1.14±5%, and a value of c.sub.3 is 0.19±5%.

17. The non-transitory computer readable storage medium according to claim 15, wherein the software further includes instructions to calculate the coefficients c.sub.1, c.sub.2, and c.sub.3, which are selected to satisfy the equations: c.sub.1√{square root over (1+ζ.sup.2)}=1 and β=sin(ϕ.sub.m−tan.sup.−1ζ), where $\xi =2\pi c_3-\frac{1}{2\pi c_2},$ and (ϕ.sub.m) is a desired phase margin;

18. The non-transitory computer readable storage medium according to claim 11 having data stored therein representing a value of threshold parameter β as −0.2±5%.

Description

DESCRIPTION OF THE DRAWINGS

[0027] The present invention will now be described, by way of example with reference to the accompanying drawings, in which:

[0028] FIG. 1a shows a schematic block diagram of the MRFT (which represents the test stage of the MRFT autotuning method) according to the prior art;

[0029] FIG. 1b shows illustrative waveforms of the operation of the MRFT according to the prior art;

[0030] FIG. 2 shows a flowchart for an implementation of the MRFT test stage on a DC-DC switching buck converter according to some embodiments;

[0031] FIG. 3 shows a schematic block diagram of the MRFT block with the DC-DC switching buck converter according to some embodiments;

[0032] FIG. 4 shows a graph of oscillations resulting from the application of the MRFT to a DC-DC switching buck converter, using scales of 20 mV/division for the vertical axis and 200 μs/division for the horizontal axis, according to some embodiments;

[0033] FIG. 5 shows a graph of oscillations resulting from the application of the MRFT to a DC-DC switching buck converter overlaid on the relay status according to some embodiments;

[0034] FIG. 6a shows the transient response of the output voltage of a DC-DC switching buck converter due to a step in the commanded set-point voltage from 2V to 2.2V, where the converter has an inductance value of 10 μH and a capacitance value of 660 μF, and where the PID controller of the converter is tuned with the MRFT autotuning method, according to some embodiments;

[0035] FIG. 6b shows a transient response of the output voltage of a DC-DC switching buck having the same inductance and capacitance values as in FIG. 6a and for the same step in set-point like in FIG. 6a, but where the PID controller of the converter, unlike FIG. 6a, is tuned using an optimal but non-autotuning method;

[0036] FIG. 7a shows the transient response of the output voltage of a DC-DC switching buck converter due to a step in the commanded set-point voltage from 2V to 2.2V, where the converter has an inductance value of 10 μH and a capacitance value of 440 μF, and where the PID controller of the converter is tuned with the MRFT autotuning method, according to some embodiments;

[0037] FIG. 7b shows a transient response of the output voltage of a DC-DC switching buck having the same inductance and capacitance values as in FIG. 7a and for the same step in set-point like in FIG. 7a, but where the PID controller of the converter, unlike FIG. 7a, is tuned using an optimal but non-autotuning method;

[0038] FIG. 8a shows the transient response of the output voltage of a DC-DC switching buck converter due to a step in the commanded set-point voltage from 2V to 2.2V, where the converter has an inductance value of 4.8 μH and a capacitance value of 660 μF, and where the PID controller of the converter is tuned with the MRFT autotuning method, according to some embodiments;

[0039] FIG. 8b shows a transient response of the output voltage of a DC-DC switching buck having the same inductance and capacitance values as in FIG. 8a and for the same step in set-point like in FIG. 8a, but where the PID controller of the converter, unlike FIG. 8a, is tuned using an optimal but non-autotuning method;

[0040] FIG. 9a shows the transient response of the output voltage of a DC-DC switching buck converter due to a step in the commanded set-point voltage from 2V to 2.2V, where the converter has an inductance value of 4.8 μH and a capacitance value of 440 μF, and where the PID controller of the converter is tuned with the MRFT autotuning method, according to some embodiments;

[0041] FIG. 9b shows a transient response of the output voltage of a DC-DC switching buck having the same inductance and capacitance values as in FIG. 9a and for the same step in set-point like in FIG. 9a, but where the PID controller of the converter, unlike FIG. 9a, is tuned using an optimal but non-autotuning method;

[0042] FIG. 10a shows the transient response of the output voltage of a DC-DC switching buck converter due to a step in the load current from 0.27 A to 1.27 A, where the converter has an inductance value of 10 μH and a capacitance value of 660 μF, and where the PID controller of the converter is tuned with the MRFT autotuning method, according to some embodiments;

[0043] FIG. 10b shows a transient response of the output voltage of a DC-DC switching buck having the same inductance and capacitance values as in FIG. 10a and for the same step in load current like in FIG. 10a, but where the PID controller of the converter, unlike FIG. 10a, is tuned using an optimal but non-autotuning method;

[0044] FIG. 11a shows the transient response of the output voltage of a DC-DC switching buck converter due to a step in the load current from 0.27 A to 1.27 A, where the converter has an inductance value of 10 μH and a capacitance value of 440 μF, and where the PID controller of the converter is tuned with the MRFT autotuning method, according to some embodiments;

[0045] FIG. 11b shows a transient response of the output voltage of a DC-DC switching buck having the same inductance and capacitance values as in FIG. 11a and for the same step in load current like in FIG. 11a, but where the PID controller of the converter, unlike FIG. 11a, is tuned using an optimal but non-autotuning method;

[0046] FIG. 12a shows the transient response of the output voltage of a DC-DC switching buck converter due to a step in the load current from 0.27 A to 1.27 A, where the converter has an inductance value of 4.8 μH and a capacitance value of 660 μF, and where the PID controller of the converter is tuned with the MRFT autotuning method, according to some embodiments;

[0047] FIG. 12b shows a transient response of the output voltage of a DC-DC switching buck having the same inductance and capacitance values as in FIG. 12a and for the same step in load current like in FIG. 12a, but where the PID controller of the converter, unlike FIG. 12a, is tuned using an optimal but non-autotuning method;

[0048] FIG. 13a shows the transient response of the output voltage of a DC-DC switching buck converter due to a step in the load current from 0.27 A to 1.27 A, where the converter has an inductance value of 4.8 μH and a capacitance value of 440 μF, and where the PID controller of the converter is tuned with the MRFT autotuning method, according to some embodiments; and

[0049] FIG. 13b shows a transient response of the output voltage of a DC-DC switching buck having the same inductance and capacitance values as in FIG. 13a and for the same step in load current like in FIG. 13a, but where the PID controller of the converter, unlike FIG. 13a, is tuned using an optimal but non-autotuning method.

DETAILED DESCRIPTION

[0050] A method of autotuning a PID controller 102 of a DC-DC switching buck converter 100 using the modified relay feedback test (MRFT) is provided. The method is comprised of two components, which are: [0051] a procedure for implementing the test stage of the MRFT autotuning method on a digitally-controlled DC-DC pulse-width modulated buck converter; and [0052] PID controller tuning rules that provide near-optimal performance for virtually any DC-DC buck converter. The tuning rules also provide a desired phase margin.

[0053] In the context of the DC-DC converter, a direct implementation of the original MRFT autotuning method would be to disable the DPWM and let the MRFT directly control the converter switches, so that when the MRFT block output is +h, the main switch is turned ON, and when the relay is −h, the main switch is turned OFF. But since the MRFT frequency is typically much lower than the DPWM frequency, switching at the MRFT frequency will result in an increased ripple in both the inductor current and the output voltage. The present invention adopts a more appropriate approach of double-modulation, where the DPWM is still maintained during the test stage, and the MRFT modulation is superposed on top of it. This is done by setting the MRFT block output, u(t), to either D+h or D−h instead of +h or −h, where D is the nominal duty-cycle, i.e., the modulation index that is normally provided by the PID controller to the DPWM to produce an output voltage equal to the set point (V.sub.o-ref). In such approach, the MRFT oscillations appear superposed on top of the nominal output voltage. In terms of gate pulses, the MRFT manifests as a series of slightly wider PWM pulses corresponding to the D+h duty-cycle and lasting for T.sub.u/2, followed by a series of slightly narrower PWM pulses corresponding to the D−h duty-cycle and also lasting for T.sub.u/2, where T.sub.u is the time period of the MRFT oscillations. The advantage of the adopted approach is that the converter maintains the switching frequency it was designed for even during the test stage, thus maintaining an acceptable level of ripple. This minimizes the impact of the MRFT auto-tuning on the converter, making it possible to take place even during normal operation (in most applications).

[0054] The algorithm of the MRFT block in such approach is expressed as below:

[00010]$u\left(t\right)=\{\begin{array}{cc}& \left\{e\left(t\right)\ge -\beta e_{\min }\&u\left(t-\right)=D-h\right\}\\ D+h,\mathrm{if}& \mathrm{or}\\ & \left\{e\left(t\right)\ge -\beta e_{\max }\&u\left(t-\right)=D+h\right\}\\ & \\ & \left\{e\left(t\right)\le -{\mathrm{\beta e}}_{\max }\&u\left(t-\right)=D+h\right\}\\ D-h,\mathrm{if}& \mathrm{or}\\ & \left\{e\left(t\right)\le -{\mathrm{\beta e}}_{\min }\&u\left(t-\right)=D-h\right\}\\ & \end{array}$

[0055] The MRFT tuning method can be initiated upon user prompt or programmed by the user in accordance with a certain schedule or event. The MRFT tuning method only lasts for a short duration (typically less than 1 millisecond). The inputs required by the MRFT tuning method routine are: [0056] β is a threshold parameter that determines the amount of hysteresis in the modified relay; [0057] h is the desired magnitude of the relay (to be added to steady-state duty-cycle); [0058] N.sub.discard is the number of initial MRFT oscillation cycles to be neglected in calculating amplitude and frequency of oscillations; [0059] N.sub.MRFT is the number of MRFT oscillation cycles to be run after the first N.sub.discard cycles; and [0060] N.sub.cycles is the total number of MRFT oscillation cycles per single run of the test. Thus, N.sub.cycles=N.sub.discard+N.sub.MRFT.

[0061] Next, the MRFT tuning method data that needs to be recorded for post-processing is as follows: [0062] All minimums and maximums of an error signal for duration of the test stage of the

[0063] MRFT autotuning method; and [0064] T.sub.MRFT is the time duration for the last N.sub.MRFT cycles only, i.e., not including the time duration of the initial N.sub.discard cycles. [0065] The complete error signal waveform for duration of the MRFT tuning method is optionally recorded. [0066] The complete relay signal waveform for duration of the MRFT tuning method is optionally recorded.

[0067] The MRFT tuning method is then executed per the algorithm in the flowchart shown in FIG. 2. After the MRFT tuning method is completed, the following post-processing calculations are carried out:

[00011]$T_u=\frac{T_{MRFT}}{N_{MRFT}}$ [0068] is calculated. This is the time period of the MRFT oscillations (referred to as the ultimate time period). It is calculated as the average time period over the last N.sub.MRFT cycles (i.e., not including the first N.sub.discard cycles).

[00012]$a=\frac{{.Math.}_{N_{\mathrm{MRFT}}}{e}_{\max }+{.Math.}_{N_{\mathrm{MRFT}}}\left|e_{\min }\right|}{2N_{\mathrm{MRFT}}}.fwdarw.$ [0069] is calculated. This is the average amplitude of the MRFT oscillations, calculated using the (absolute value of) all minimums and maximums over the last N.sub.MRFT cycles. [0070] A validity check on the error waveform may optionally be conducted to check if it contains many noise spikes or highly irregular oscillations. The test may be repeated if deemed necessary.

[0071] The above procedure represents the test stage, which is first of two steps of the MRFT tuning method. The second and final step is the tuning stage, which is to update the PID controller parameters using the test results. A PID controller of the following form is used, where K.sub.c is the proportional gain, T.sub.i the integral time, and T.sub.d the derivative time.

[00013]$\begin{array}{cc}{W}_c\left(s\right)=K_c\left(1+\frac{1}{T_{i}s}+T_{d}s\right)& \mathrm{Eq}.\left(3\right)\end{array}$

[0072] Tuning rules of the following form are used, where coefficients c.sub.1, c.sub.2, and c.sub.3, are positive constants.

[00014]$\begin{array}{cc}{K}_c=c_1{K}_u=c_1\frac{4h}{\pi a_0},T_i=c_2{T}_u=c_2\frac{2\pi }{{\Omega }_0},T_d=c_3{T}_u=c_3\frac{2\pi }{{\Omega }_0}& \mathrm{Eq}.\left(4\right)\end{array}$

[0073] According to the MRFT autotuning method, selecting c.sub.1, c.sub.2, and c.sub.3, and the threshold parameter β of the MRFT in coordination with each other as per the following constraints would provide a user-specified phase margin, ϕ.sub.m, for any arbitrary system.

[00015]$\begin{array}{cc}{c}_1\sqrt{1+{\xi }^2}=1& \mathrm{Eq}.\left(5\right)\end{array}$$\beta =\sin \left({\varphi }_m-{\tan }^{-1}\xi \right),\mathrm{where}\xi =2\pi c_3-\frac{1}{2\pi c_2}$

[0074] Further to this, using a two-stage optimization technique, the set (β, c.sub.1, c.sub.2, c.sub.3) is chosen so that it provides near-optimal transient performance for a wide range of DC-DC buck converters. Details of the optimization procedure used to obtain the optimized tuning rules is provided later. The optimized set (β*, c.sub.1*, c.sub.2*, c.sub.3*), is given below.

β*=−0.2±5%, c.sub.1*=0.69±5%, c.sub.2*=1.14±5%, c.sub.3*=0.19±5%  Eq. (6)

[0075] Referring to the example application shown in FIG. 3, a digitally controlled synchronous DC-DC buck converter 100, operating in voltage-control mode, is used for the implementation of the MRFT tuning method. A full schematic of the system is illustrated in FIG. 3. The output voltage (v.sub.o) goes through a sensing circuit 106 that includes a voltage step-down circuit and an anti-aliasing filter.

[0076] A digital microcontroller, e.g., Texas Instruments TMS320F28335, is used for sampling and control. The microcontroller includes non-transitory memory containing software instructions to perform the steps of the method described herein. The microcontroller also includes transitory memory containing data generated by the method described herein.

[0077] The switching frequency (f.sub.s=1/T.sub.s) of the digital pulse width modulator (DPWM) 108 is set to 200 kHz. The sampling rate is also set to 200 kHz and is synchronized with the PWM. The resistive load (R.sub.o) 110 can be electronically switched between two values to provide load transients for controller testing. The resistor R.sub.s 112 is used to sense the inductor current (I.sub.L) through the inductor L 114 for protection purposes. The output filter capacitance consists of a parallel combination of two larger aluminum polymer low equivalent series resistance (ESR) capacitors (together forming capacitance C.sub.1) 115 and three smaller ceramic capacitors (together forming capacitance C.sub.2) 116. R.sub.L, R.sub.C1, and R.sub.C2 are the parasitic resistances of L, C.sub.1, and C.sub.2, respectively. Nominal input supply voltage (V.sub.s) is 9 V while the set-point output voltage (V.sub.o-ref) is 2 V.

[0078] For the first test setup, L=4.8 μH and C.sub.1=440 μF are used (where C.sub.1 is formed using two parallel 220 μF capacitors for lower ESR). The MRFT tuning method is performed using the optimized β in Eq. (6). The experimentally measured oscillations in v.sub.o are shown in FIG. 4. The digital controller is programmed to discard the first few cycles when taking measurements of T.sub.u and a.sub.0, since as seen from FIG. 4 the oscillations stabilize after a short transient of one or two cycles. It is also noted that the amplitude of oscillations is relatively low (only ±0.04 V around the 2 V steady state, i.e., 2%). Such small magnitude of the oscillations, as well the need for only a few oscillation cycles, makes the MRFT method's effect on a converter's operation minimal The same oscillations of FIG. 4 but recorded in the microcontroller memory as contiguous digital conversion samples taken by the Analog to Digital Converter (ADC) 118 (see FIG. 3), are shown in FIG. 5. Also shown superposed in FIG. 5 is a plot of the relay's output, where +1 (relay ON) indicates that h is added to the steady-state controller output, while −1 (relay OFF) indicates that h is subtracted from the steady-state controller output. It is noted that the sampled ADC signal shown in FIG. 5, upon which the control action is based, is much cleaner than that shown in the graph of FIG. 4. This is achieved by sampling between switch transitions to avoid switching noise spikes and is also partially due to the filtering provided by the anti-aliasing low pass filter (LPF) 106.

[0079] Immediately following the first stage of the MRFT method, the new PID controller coefficients are calculated. K.sub.u is obtained from Eq. (2) using the measured amplitude a.sub.0, and it is used along with the frequency Ω.sub.0=2π/T.sub.u to calculate the PID controller coefficients using Eq. (4) and (c.sub.1, c.sub.2, c.sub.3) from Eq. (6). T.sub.u for this example application (using a DC-DC buck converter with L=4.8 μH and C.sub.1=440 μF) was 138 μs, while the K.sub.u based on the measured a.sub.0 was 11.4 V.sup.−1.

[0080] This same test stage of the MRFT autotuning method was repeated using the same example converter referred above but with different values of L and C.sub.1. For each design, two tests are conducted to test the MRFT auto-tuned controller's performance In the first test, a step in V.sub.o-ref from 2 V to 2.2 V is applied, while in the second test a step in the output current (I.sub.o) from 0.27 A to 1.27 A is applied.

TABLE-US-00001 TABLE 1 Controller Parameters for MRFT Auto- Tuned and Optimized Controllers Controller Ti T.sub.d Design # Type K.sub.c (μs) (μs) 1 L = 10 μH MRFT 10.5 150 25 C.sub.1 = 660 μF (Adaptive) Optimized 7.3 193 36 (Non-adaptive) 2 L = 10 μH MRFT 7.9 157 26 C.sub.1 = 440 μF (Adaptive) Optimized 5.6 145 35 (Non-adaptive) 3 L = 4.8 μH MRFT 4.6 100 17 C.sub.1 = 660 μF (Adaptive) Optimized 4.8 132 16 (Non-adaptive) 4 L = 4.8 μH MRFT 3.7 96 16 C.sub.1 = 440 μF (Adaptive) Optimized 4.3 105 16 (Non-adaptive)

[0081] For comparison, another PID controller that is tuned optimally for each of the specific converter designs is used. This optimized controller is obtained using the following procedure. Experimentally measured frequency response data of the buck converter system is obtained with the aid of a software frequency response analyzer (SFRA) tool, such as that produced by Texas Instruments Incorporated, and a high order transfer function (TF) is fitted to the measured frequency response data. Using this fitted model, a controller that gives the lowest integral of time-weighted absolute error (ITAE) (in simulation) for a step in V.sub.o-ref for this TF is obtained through optimization using a processes of finding a minimum of an unconstrained multivariable function using derivative-free method, e.g., the fminsearch function in MATLAB® available from MathWorks, Inc. Note that this optimized controller differs from the MRFT block in that it 1) is optimized only for a given converter design and cannot be re-tuned to any other converter, and 2) does not guarantee a specific gain or phase margin.

[0082] Table 1 above lists the PID controller parameters for the MRFT blocks and the optimized controllers of each of the four tested designs. FIGS. 6a-9b show the experimental voltage output waveforms for the V.sub.o-ref step tests, while FIGS. 10a-13b show the experimental voltage output waveforms for a step change in the load. The overall performance of the MRFT block is quite close to that of the optimized controller. Furthermore, in many of the cases where the overshoot/undershoot of the optimized controller is (expectedly) less than that of the MRFT-autotuned controller, the settling time of the latter is the same or even better, as seen in FIG. 8. Finally, the cases of high overshoot/undershoot (such as FIGS. 8a, 9a, 12a, and 13a) are associated with low damping due to the choice of a smaller inductor L.

[0083] In the remainder of this section, the optimization framework used to arrive at the optimal set of (β, c.sub.1, c.sub.2, c.sub.3) is described. The model below describes a general buck converter. The term e.sup.−τs represents the total delay due to sampling/control and the PWM operation, given by τ=1.5T.sub.s.

[00016]$G_{buck}\left(s\right)=\frac{e^{-\tau s}}{L{C}_o{s}^2+\frac{L}{R_o}s+1}$

[0084] Let T.sub.1=√{square root over (LC.sub.o)} and

[00017]$T_2=\frac{L}{R_o}.$

G.sub.buck is said to have three following situational parameters, namely T.sub.1, T.sub.2, and τ. The situational parameters may be reduced to two through use of the scaled Laplace variable s′=T.sub.1s, which results in the TF below having only

[00018]$\frac{\tau }{T_1}\mathrm{and}\frac{T_2}{T_1}$

as situational parameters.

[00019]$G_{buck}\left(s\right)=\frac{e^{\frac{\tau }{T_1}{s}^{\prime }}}{s^{\prime 2}+\frac{T_2}{T_1}{s}^{\prime }+1}$

[0085] In order to obtain a realistic range of TFs covering practical buck converter designs, basic component-sizing equations are utilized. The following equation may be used to determine the inductive value L in a DC-DC buck converter:

[00020]$L=\frac{V_o\left(1-D\right)}{K_L{I}_o{f}_s}$

where V.sub.o and I.sub.o are the nominal output voltage and nominal output current, respectively. K.sub.L is a coefficient related to the inductor current ripple and is typically set between 0.2 and 0.3 for a buck converter. K.sub.L=0.3 is chosen to provide the minimum L, since L will be scaled up later. The nominal duty-cycle (D) is taken as 0.5. Noting that the ratio of V.sub.o to I.sub.o is equal to the load resistance (R.sub.o), minimum inductance (L.sub.min) is given by

[00021]$L_{\min }=\frac{0.5R_o}{0.3f_s}=\frac{5}{3}\frac{R_o}{f_s}.$

[0086] The design criteria for C.sub.o, in the case of a low ESR, is given below where K.sub.c is the desired maximum percent ripple in the capacitor voltage.

[00022]$C_o=\frac{1}{8f_s}\frac{K_L{I}_o}{K_C{V}_o}$

[0087] Choosing K.sub.C as 1%, the following expression is obtained for the minimum inductance, C.sub.o-min:

[00023]$C_{o-\min }=\frac{1}{8f_s}\frac{0.3I_o}{0.01V_o}=\frac{15}{4}\frac{1}{f_s{R}_o}=\frac{3.75}{f_s{R}_o}$

[0088] Defining scaling factors a.sub.L for L and a.sub.C for C.sub.o, the situational parameters and thus the expression for G.sub.buck may be rewritten as follows:

[00024]$T_1=\sqrt{L{C}_o}=\sqrt{{\alpha }_L{L}_{\min }{\alpha }_C{C}_{o-\min }}=\frac{5}{2}\frac{\sqrt{{\alpha }_L{\alpha }_C}}{f_s}$$T_2=\frac{L}{R_o}=\frac{{\alpha }_L{L}_{\min }}{R_o}=\frac{5}{3}\frac{{\alpha }_L}{f_s}$$.fwdarw.\frac{\tau }{T_1}=\frac{0.6}{\sqrt{{\alpha }_L{\alpha }_C}}\mathrm{and}\frac{T_2}{T_1}=\frac{2}{3}\sqrt{\frac{{\alpha }_L}{{\alpha }_C}}$$G_{buck}\left(s\right)=\frac{e^{-\left(\frac{0.6}{{\alpha }_L{\alpha }_C}\right)s^{\prime }}}{s^{\mathrm{\prime 2}}+\left(\frac{2}{3}\sqrt{\frac{{\alpha }_L}{{\alpha }_C}}\right)s^{\prime }+1}$

[0089] Comparing the characteristic polynomial in the denominator to the standard second order system format of (s.sup.2+2ζω.sub.n+ω.sub.n.sup.2), the damping factor ζ is found to be

[00025]$\frac{1}{3}\sqrt{\frac{{\alpha }_L}{{\alpha }_C}},$

while the natural frequency ω.sub.n is 1. By considering all combinations of a.sub.L and a.sub.C from 1 to 10, a whole range of converters are represented. An illustration of this in grid format is provided in Table 2.

TABLE-US-00002 TABLE 2 Grid of TFs representing the range of buck converter designs α.sub.C .fwdarw. α.sub.L ↓ 1 2 3 4 5 6 7 8 9 10 1 1 2 2 3 3 4 5 6 4 7 8 9 10 5 11 12 13 14 15 6 16 17 18 19 20 21 7 22 23 24 25 26 27 28 8 29 30 31 32 33 34 35 36 9 37 38 39 40 41 42 43 44 45 10 46 47 48 49 50 51 52 53 54 55

[0090] Finally, to justify the approximation of neglecting the zero that appears in the transfer function when the output capacitor has a non-negligible ESR, the ESR effect is represented to some extent by increasing the damping (ζ). This is done by making sure a.sub.L≥a.sub.C, which results in ζ being ≥⅓. A total of 55 TFs (shown as shaded boxes in the figure below) are obtained after applying the criterion a.sub.L≥a.sub.C. The TFs are numbered serially from 1 to 55, with the TF number appearing in the respective box in Table 2.

[0091] The optimization framework consists of two stages. In the first stage, the optimized value (β, c.sub.1, c.sub.2, c.sub.3) for every TF of the grid in Table 2 is obtained through optimization of the transient response in simulation, using the derived model G.sub.buck. The transient performance is evaluated using the “integral of time weighted absolute error” (ITAE), calculated using the following equation, where X is the vector [β, c.sub.1, c.sub.2, c.sub.3]. t.sub.init is the time instant at which the transient occurs, and t.sub.s is the settling time.

[00026]$\mathrm{ITAE}\left(X\right)={\int }_{t_{\mathrm{init}}}^{t_s}\left(t-t_{\mathrm{init}}\right).Math.e\left(t-t_{\mathrm{init}},X\right).Math.\mathrm{dt}$

[0092] A combination of computer-based simulation programs, such as MATLAB® and SIMULINK®, also available from MathWorks, Inc., may be used for this purpose. A processes of finding a minimum of an unconstrained multivariable function using derivative-free method, e.g., the fminsearch function in MATLAB® which is based on the Nelder-Mead simplex direct search algorithm, is used for the optimization. Each iteration of the optimization consists of the following 3 steps. [0093] 1. The MRFT block described by the diagram of FIG. 1a, with the modified relay as described in Eq. (2) and with W(s)=G.sub.buck(s), is simulated by the computer-based simulation programs using the initial/current value of β. Measurements of T.sub.u and a.sub.0 from the simulation are obtained. [0094] 2. PID controller coefficients are calculated from (4) using T.sub.u and a.sub.0 from step 1 and the initial/current (c.sub.1, c.sub.2, c.sub.3). [0095] 3. Using the PID controller coefficients from step 2 and the current G.sub.buck, a closed-loop simulation of a step in V.sub.o-ref is performed and the ITAE is calculated.

[0096] After every iteration (of steps 1-3), the set (β, c.sub.1, c.sub.2, c.sub.3) is updated by the fminsearch function to result in a lower ITAE—while still ensuring that the updated (β, c.sub.1, c.sub.2, c.sub.3) still satisfy the constraints in Eq. (5). The iterations (of steps 1-3) are repeated until the improvement in ITAE is below the specified tolerance. Let the 55 TFs in the grid of FIG. 4 be referred to as G.sub.buck-n for n=1 to 55. The final output of the first stage of optimization is therefore a group of locally optimized sets (β.sup.n, c.sub.1.sup.n, c.sub.2.sup.n, c.sub.3.sup.n) for n=1 to 55, where each (β.sup.n, c.sub.1.sup.n, c.sub.2.sup.n, c.sub.3.sup.n) results in the lowest ITAE for the corresponding G.sub.buck-n.

[0097] The second stage of the optimization applies the principle of “least performance degradation” to obtain a globally optimized set of (β, c.sub.1, c.sub.2, c.sub.3). This is done as follows: [0098] 1. Using β.sup.1 (the optimized β found for G.sub.buck-1), MRFT is simulated for G.sub.buck-1 to G.sub.buck-55. Respective MRFT measurements, T.sub.u1.sup.n and a.sub.01.sup.n (for n=1 to 55), are recorded. [0099] 2. Now using c.sub.1.sup.1, c.sub.2.sup.1, and c.sub.3.sup.1 (which are locally optimized for G.sub.buck-1), along with T.sub.u1.sup.n and a.sub.01.sup.n (for n=1 to 55) from the previous step, a PID controller C.sub.1.sup.n(s) is designed for each of G.sub.buck-1 to G.sub.buck-55 using (10). Thus, C.sub.1.sup.n(s) is based on G.sub.buck-n and the set (β.sup.1, c.sub.1.sup.1, c.sub.2.sup.1, c.sub.3.sup.1) that is locally optimized to G.sub.buck-1. [0100] 3. Next, each G.sub.buck-n is simulated in closed-loop using its corresponding PID controller from the previous step, C.sub.1.sup.n(s). For example: G.sub.buck-1 with C.sub.1.sup.1(s), G.sub.buck-2 with C.sub.1.sup.2(s), and so on. Each time the corresponding ITAE, denoted ITAE.sub.1.sup.n(for n=1 to 55) is recorded. The single maximum (worst-case) ITAE

[00027]$\underset{n=1,2,.Math.55}{\max }{\mathrm{ITAE}}_1^n,$

is then found. [0101] 4. Steps 1, 2, and 3 are repeated using (β.sup.2, c.sub.1.sup.2, c.sub.2.sup.2, c.sub.3.sup.2) to obtain ITAE.sub.2.sup.n for n=1 to 55, and

[00028]$\underset{n=1,2,.Math.55}{\max }{\mathrm{ITAE}}_2^n$

is recorded. This is repeated until all worst-case ITAEs,

[00029]$\underset{n=1,2,.Math.55}{\max }{\mathrm{ITAE}}_k^n\left(\mathrm{for}k=1\mathrm{to}55\right),$

are recorded.

[0102] The globally optimized set, (β*, c.sub.1*, c.sub.2*, c.sub.3*), is the set with the lowest

[00030]$\underset{n=1,2,.Math.55}{\max }{\mathrm{ITAE}}_k^n\mathrm{for}k=1\mathrm{to}55.$

In other words, it is the set that results in the least performance degradation when applied to all converters in the considered range. This completes the second stage of the optimization. Constraints used in the optimization process include restricting ϕ.sub.m in Eq. (5) to [20°, 60°], c.sub.2 to [0.1, 100] to limit the integral action, and restricting c.sub.1 and c.sub.3 to being positive. A final constraint was to set the minimum β to −0.2, since large negative values of β may be difficult to apply in practice due to the oscillations associated with having a smaller amplitude thus making their accurate measurement a challenging task. Performing the optimization process above for the system represented by G.sub.buck and for the range of parameters defined by the grid of Table 2, the globally optimized set was found to be (β.sup.3, c.sub.1.sup.3, c.sub.2.sup.3, c.sub.3.sup.3), which resulted in ϕ.sub.m=35°. The numerical values of the parameters in this set were:

β*=−0.2, c.sub.1*=0.69, c.sub.2*=1.14, c.sub.3*=0.19

[0103] In other words, using (β*, c.sub.1*, c.sub.2*, c.sub.3*)=(β.sup.3, c.sub.1.sup.3, c.sub.2.sup.3, c.sub.3.sup.3) to tune a controller for every other G.sub.buck-n model in the considered range resulted in the least performance degradation from the locally optimized performance, ITAE.sub.3.sup.3. This worst-case degradation,

[00031]$\underset{n=1,2,.Math.55}{\max }{\mathrm{ITAE}}_3^n,$

only 13% more than the locally optimized case ITAE.sub.3.sup.3. It is noted that the (β*, c.sub.1*, c.sub.2*, c.sub.3*) provided earlier in the manuscript included a ±5% tolerance for each parameter in the set. This is because as long as the four parameters satisfy the constraints in Eq. (5), the specified phase margin is guaranteed, and further if they are in the vicinity of the original values of (β.sup.3, c.sub.1.sup.3, c.sub.2.sup.3, c.sub.3.sup.3) , then very similar dynamic performance is obtained.

[0104] While the invention has been described with reference to an exemplary embodiment(s), it will be understood by those skilled in the art that various changes may be made, and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention is not limited to the disclosed embodiment(s), but that the invention will include all embodiments falling within the scope of the appended claims.