CMOS RGB-IR SENSOR WITH QUADRUPLE-WELL STACK STRUCTURE

Abstract

A CMOS image sensor includes: a substrate containing a potential well stack including: a first p-well, a first n-well disposed below the first p-well, a second p-well disposed below the first n-well, a second n-well disposed below the second p-well, and a third p-well disposed below the second n-well, wherein a first photodiode is formed at the junction between the first p-well and first n-well, a second photodiode is formed at the junction between the first n-well and second p-well, a third photodiode is formed at the junction between the second p-well and the second n-well, and a fourth photodiode is formed at the junction between the second n-well and the third p-well, and each photodiode is disposed at a different respective depth within the substrate; and a plurality of active pixel sensors for converting light received by the photodiodes into electrical charge.

Claims

1. A CMOS image sensor, comprising: a plurality of micro lenses, for receiving incident light; a substrate, disposed below the plurality of micro lenses, the substrate containing a potential well stack comprising: a first p-well disposed below the micro lenses, a first n-well disposed below the first p-well, a second p-well disposed below the first n-well, a second n-well disposed below the second p-well, and a third p-well disposed below the second n-well, wherein a first photodiode is formed at the junction between the first p-well and first n-well, a second photodiode is formed at the junction between the first n-well and second p-well, a third photodiode is formed at the junction between the second p-well and the second n-well, and a fourth photodiode is formed at the junction between the second n-well and the third p-well, and each photodiode is disposed at a different respective depth within the substrate; and a plurality of active pixel sensors for converting light received by the photodiodes into electrical charge.

2. The CMOS image sensor of claim 1, wherein the first photodiode is for receiving blue light, the second photodiode is for receiving green light, the third photodiode is for receiving red light and the fourth photodiode is for receiving infrared light.

3. The CMOS image sensor of claim 1, wherein the CMOS image sensor is a front light illuminated (FSI) sensor.

4. The CMOS image sensor of claim 1, wherein the CMOS image sensor is a back light illuminated (BSI) sensor.

5. The CMOS image sensor of claim 4, further comprising a reflector for enhancing the received infrared light.

6. The CMOS image sensor of claim 2, wherein the first photodiode is disposed in the substrate at a depth of 0.2˜0.5 micrometers, the second photodiode is disposed in the substrate at a depth of 0.5˜1.5 micrometers, the third photodiode is disposed in the substrate at a depth of 1.5˜3 micrometers and the fourth photodiode is disposed in the substrate at a depth of 3 micrometers and below.

7. An active pixel sensor control circuit for converting incident light received by a CMOS image sensor into electrical charge, the CMOS image sensor having a potential well stack structure comprising a first p-well, a first n-well disposed below the first p-well, a second p-well disposed below the first n-well, a second n-well disposed below the second p-well , and a third p-well disposed below the second n-well, wherein a first photodiode is formed at the junction between the first p-well and the first n-well, a second photodiode is formed at the junction between the first n-well and the second p-well, a third photodiode is formed at the junction between the second p-well and the second n-well, and a fourth photodiode is formed at the junction between the second n-well and the third p-well, the active pixel sensor control circuit comprising: a first control circuit for controlling the first photodiode, a second control circuit for controlling the second photodiode, a third control circuit for controlling the third photodiode and a fourth control circuit for controlling the fourth photodiode, wherein the first control circuit and the third control circuit are a second type control circuit, the second control circuit and the fourth control circuit are a first type control circuit, the first type control circuit comprises: a four transistor (4T) active pixel sensor comprising a transfer transistor, a reset transistor, a source follower and a select transistor, wherein the reset transistor and the source follower are coupled to a first power supply signal; the second type control circuit comprises: a 4T active pixel sensor comprising a transfer transistor, a reset transistor, a source follower and a select transistor, wherein the source follower is coupled to the first power supply signal, the reset transistor is coupled to a second power supply signal, and the second power supply signal is less than the first power supply signal; wherein when a transfer signal is applied to the gates of the transfer transistors and a reset signal is applied to the gates of the reset transistors, the second photodiode and the fourth photodiode are charged to the first power supply level, and the first photodiode and the third photodiode are discharged to the second power supply level.

8. The active pixel sensor control circuit of claim 7, wherein each of the select transistors is coupled to a same column bus, so that signals from the first photodiode, the second photodiode, the third photodiode and the fourth photodiode are read out sequentially when a select signal is applied to the gates of the select transistors.

9. The active pixel sensor control circuit of claim 7, wherein each of the select transistors is coupled to a different respective column bus, and the four column buses are coupled to the first power supply, so that the signals from the first photodiode, the second photodiode, the third photodiode and the fourth photodiode are read out at a same time when a select signal is applied to the gates of the select transistors.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] FIG. 1 is a diagram of a CMOS image sensor according to the conventional art.

[0017] FIG. 2 is a diagram of the filter operation of the CMOS image sensor shown in FIG. 1.

[0018] FIG. 3A is a cross-section diagram of a CMOS image sensor having a quadruple-well stack structure according to an exemplary embodiment of the present invention.

[0019] FIG. 3B is a top-view diagram of the CMOS image sensor shown in FIG. 3A.

[0020] FIG. 4 is an active pixel sensor control circuit diagram of the CMOS image sensor shown in FIG. 3 according to a first embodiment of the present invention.

[0021] FIG. 5 is an active pixel sensor control circuit diagram of the CMOS image sensor shown in FIG. 3 according to a second embodiment of the present invention.

DETAILED DESCRIPTION

[0022] The present invention provides a CMOS image sensor which does not require an SNIR filter or an IR pass filter. As light has a different absorption ratio depending on its wavelength, the CMOS image sensor of the present invention uses a quadruple-well stack structure to form the photodiodes for each colour pixel (RGB-IR). The individual photodiodes are formed at the junction between each potential well. By distributing each photodiode at a different depth within the silicon substrate, wherein the depth is determined according to the individual absorption ratios of different wavelengths of light, only a specific wavelength of light will be absorbed by an individual photodiode while other wavelengths will be passed. Hence, the photodiodes act as their own filter.

[0023] Refer to FIG. 3A and FIG. 3B, which respectively illustrate a cross-section and a top view of the proposed quadruple well stack structure 300. As shown in FIG. 3A, a first p-well is distributed directly below the surface of the substrate, an n-well is distributed below the p-well, another p-well is distributed below the n-well etc. such that four photo-diodes at respective depths d.sub.a, d.sub.b, d.sub.c and d.sub.d are formed within the substrate 300, wherein d.sub.a is at a depth of 0.2˜0.5 micrometers, d.sub.b is at a depth of 0.5˜1.5 micrometers, d.sub.c is at a depth of 1.5˜3 micrometers and d.sub.d is at a depth of 3 micrometers and below.

[0024] FIG. 3B illustrates the four photodiodes/PN junctions D.sub.0, D.sub.1, D.sub.2 and D.sub.3 which are formed by the quadruple wells. As light enters the substrate, it will be absorbed by each photodiode, with blue light being absorbed by the first photodiode D.sub.0, then green light being absorbed by the second photodiode D.sub.1, red light being absorbed by the third photodiode D.sub.2 and finally IR light is absorbed by the deepest photodiode D.sub.3.

[0025] The above design can be used in a standard BSI CMOS image sensor, a BSI CMOS image sensor with a reflective layer/IR enhancer layer, and also in a front side illuminated (FSI) CMOS sensor.

[0026] In order to effectively convert the charges collected by each photodiode into photocurrent, an active pixel sensor control circuit 400 for the quadruple well stack structure 300 is provided. This is illustrated in FIG. 4. In a conventional four transistor (4T) active pixel sensor, a transfer/sense transistor must be reverse biased in order to collect electrical charge during an integration period. This is achieved by inputting at least a reset signal to a coupled reset transistor. After the integration period is completed, a select signal will be activated to pass the collected electrical charge to a source follower and then a select transistor for outputting the photocurrent on a column bus.

[0027] Due to the quadruple-well stack structure 300 shown in FIG. 3A and FIG. 3B, the direction of the photodiodes D.sub.0 and D.sub.2 are different from the direction of the photodiodes D.sub.1 and D.sub.3. The circuit 400 therefore provides two different control mechanisms for reverse biasing the photodiodes. For simplicity of explanation, the following description will only refer to photodiodes D.sub.2 and D.sub.3. One skilled in the art will be able to apply the following description to photodiodes D.sub.0 and D.sub.1. As shown in FIG. 4, D.sub.2 is coupled to a sense transistor M.sub.5 which receives a transfer signal TX at its gate. D.sub.3 is coupled to a sense transistor M.sub.3 which also receives the transfer signal TX at its gate. M.sub.5 is coupled to reset transistor M.sub.6 which receives a reset signal RX at its gate and is coupled to power supply NVDD. M.sub.3 is similarly coupled to reset transistor M.sub.2 which receives the reset signal RX at its gate, but M.sub.2 is coupled to power supply PVDD rather than NVDD. M.sub.6 is coupled to source follower M.sub.7, which is coupled to PVDD. M.sub.2 is similarly coupled to source follower M.sub.1 which is coupled to PVDD. M.sub.7 is coupled to select transistor M.sub.8, which receives a signal SX at its gate and outputs a signal on a column bus. M.sub.1 is coupled to select transistor M.sub.4, which receives the signal SX at its gate and outputs a signal on the column bus.

[0028] The dashed lines represent a pixel control circuit for each photodiode. The control circuit for photodiode D.sub.2 is annotated I.sub.2, and the control circuit for photodiode D.sub.3 is annotated I.sub.1. The photodiodes are reverse biased by applying signals TX and RX. For photodiode D.sub.3, applying signals TX and RX to the gates of M.sub.3 and M.sub.2, respectively, charges node a to the PVDD level. As D.sub.3 is also coupled to ground, this will increase the potential difference such that current cannot flow and charge can be collected when incident light is absorbed. For photodiode D.sub.2, due to the different configuration of the control circuit I.sub.2, applying the TX and RX signals to the gates of M.sub.5 and M.sub.6, respectively, node b will be discharged to the NVDD level. As node a is at PVDD, and NVDD is lower than PVDD, the potential difference therein is enough to reset photodiode D.sub.2.

[0029] Note that the above circuit structure 400 is used for sequential readout of the pixel signals. The 4T active pixel sensor structure for each photodiode enables correlated double sampling (CDS) to be performed, wherein two samples of the pixel signal are taken, and one is subtracted from the other. The double sampling is usually first performed immediately after reset of the photodiode, and then after charge accumulation at the photodiode. This method will be well-known to those skilled in the art. Pixel readout can be performed in the conventional manner for a 4T active pixel sensor circuit.

[0030] An additional circuit is provided which enables readout of all pixels at the same time. Refer to FIG. 5, which is a circuit diagram 500. Comparing the circuit 500 with the circuit 400 shown in FIG. 4, it can be seen that the difference therein is that there are four column buses respectively coupled to the select transistors, rather than all select transistors being coupled to a same column bus. Furthermore, the four column buses are also coupled to the power supply PVDD.

[0031] By using the fact that different wavelengths of light have absorption rates, the present invention has provided a CMOS image sensor which does not require extra filters. By placing each photodiode at a particular depth within a substrate corresponding to a specific absorption ratio of light, each photodiode can act as its own filter.

[0032] The present invention is therefore able to implement a CMOS image sensor which can effectively filter RGB-IR wavelengths of light without requiring additional filters or complicated circuitry.

[0033] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.