ELECTRONIC DEVICE INCLUDING AN ELECTRONIC MODULE AND A COMPENSATION CIRCUIT

Abstract

According to one aspect, an electronic device includes a power supply terminal, a voltage regulator connected to the power supply terminal, an electronic module connected to the voltage regulator, and a compensation circuit configured to receive an auxiliary current generated by the voltage regulator and being equal to a first fraction of the electronic module current. The compensation circuit includes a current source configured to supply a source current to a cold point, and a compensation stage connected to the power supply terminal and being traversed by an intermediate current equal to a difference between the source current and the auxiliary current and by a complementary current equal to the intermediate current multiplied by an inverse multiplication factor of the first fraction.

Claims

1. An electronic device comprising: a power supply terminal configured to be connected to a power supply; at least one voltage regulator connected to the power supply terminal; at least one electronic module connected to the at least one voltage regulator and configured to consume an electronic module current coming from the power supply; and a compensation circuit connected to the at least one voltage regulator and configured to receive an auxiliary current generated by the at least one voltage regulator and being equal to a first fraction of the electronic module current consumed by the at least one electronic module, the compensation circuit including: a current source connected to the at least one voltage regulator so as to receive the auxiliary current and being configured to supply to a cold point a source current greater than a maximum value of the electronic module current consumed by the at least one electronic module; and a compensation stage including: a first resistor and a second resistor each having a first terminal connected to the power supply terminal, the first resistor having a first resistive value equal to a second resistive value of the second resistor multiplied by an inverse of a multiplication factor of the first fraction, the first resistor having a second terminal connected to the current source so as to be traversed by an intermediate current equal to a difference between the source current and the auxiliary current; a first transistor having a drain connected to a second terminal of the second resistor and a source connected to the cold point; and a first operational amplifier configured to control the first transistor and having an inverting input connected to the second terminal of the first resistor and a non-inverting input connected to the second terminal of the second resistor, so that the second resistor is traversed by a complementary current equal to the intermediate current multiplied by the multiplication factor.

2. The device according to claim 1, wherein the current source and the compensation stage are connected to the at least one voltage regulator via a second transistor controlled by a second operational amplifier having an inverting input connected to a source of the second transistor and a non-inverting input configured to receive a voltage delivered by the at least one voltage regulator to the at least one electronic module.

3. The device according to claim 1, wherein the compensation stage includes: a third transistor having a drain connected to the second terminal of the first resistor and a source connected to the current source so that the second terminal of the first resistor is connected to the current source via the third transistor; and a fourth transistor having a drain connected to the second terminal of the second resistor and a source connected to the drain of the first transistor so that the second terminal of the second resistor is connected to the drain of the first transistor via the fourth transistor; the third transistor and the fourth transistor each having a gate configured to receive a fixed voltage allowing the third transistor and the fourth transistor to operate as cascodes.

4. The device according to claim 1, wherein the current source comprises at least one current mirror configured to generate the source current from a reference current.

5. The device according to claim 4, wherein the current source includes: a reference branch comprising: a reference transistor of the at least one current mirror; a first cascode transistor having a drain configured to receive the reference current and connected to a gate of the reference transistor, a source connected to a drain of the reference transistor, and a gate configured to receive a fixed voltage; and a first selection transistor having a drain connected to a source of the reference transistor, a source connected to the cold point, and a gate configured to receive a voltage delivered by the at least one voltage regulator to the at least one electronic module; an auxiliary current generation branch for each current mirror including: a copy transistor of the current mirror having a gate connected to a gate of the reference transistor and being configured to at least partly generate the source current; a second cascode transistor having a drain connected to a second output of the at least one voltage regulator, and a source connected to a drain of the copy transistor; and a second selection transistor having a drain connected to a source of the copy transistor, and a source connected to the cold point.

6. The device according to claim 5, wherein the second selection transistor of the auxiliary current generation branch of each current mirror has a gate configured to be controlled by the selection signal.

7. The device according to claim 5, wherein the second cascode transistor is common to each generation branch, the current source further including a third operational amplifier having a non-inverting input connected to the drain of the reference transistor, an inverting input connected to the source of the common second cascode transistor, and an output connected to the gate of the second cascode transistor.

8. An electronic device comprising: a power supply terminal configured to be connected to a power supply; at least one voltage regulator connected to the power supply terminal; at least one electronic module connected to the at least one voltage regulator and configured to consume an electronic module current coming from the power supply; and a compensation circuit connected to the at least one voltage regulator and configured to receive an auxiliary current generated by the at least one voltage regulator and being equal to a first fraction of the electronic module current consumed by the at least one electronic module, the compensation circuit including: a current source connected to the at least one voltage regulator so as to receive the auxiliary current and being configured to supply to a cold point a source current greater than a maximum value of the electronic module current consumed by the at least one electronic module, wherein the current source comprises: at least one current mirror configured to generate the source current from a reference current; a reference branch; and an auxiliary current generation branch for each current mirror; and a compensation stage including: a first resistor and a second resistor each having a first terminal connected to the power supply terminal, the first resistor having a first resistive value equal to a second resistive value of the second resistor multiplied by an inverse of a multiplication factor of the first fraction, the first resistor having a second terminal connected to the current source so as to be traversed by an intermediate current equal to a difference between the source current and the auxiliary current; a first transistor having a drain connected to a second terminal of the second resistor and a source connected to the cold point; and a first operational amplifier configured to control the first transistor and having an inverting input connected to the second terminal of the first resistor and a non-inverting input connected to the second terminal of the second resistor, so that the second resistor is traversed by a complementary current equal to the intermediate current multiplied by the multiplication factor.

9. The device according to claim 8, wherein the current source and the compensation stage are connected to the at least one voltage regulator via a second transistor controlled by a second operational amplifier having an inverting input connected to a source of the second transistor and a non-inverting input configured to receive a voltage delivered by the at least one voltage regulator to the at least one electronic module.

10. The device according to claim 9, wherein the compensation stage includes: a third transistor having a drain connected to the second terminal of the first resistor and a source connected to the current source so that the second terminal of the first resistor is connected to the current source via the third transistor; and a fourth transistor having a drain connected to the second terminal of the second resistor and a source connected to the drain of the first transistor so that the second terminal of the second resistor is connected to the drain of the first transistor via the fourth transistor; the third transistor and the fourth transistor each having a gate configured to receive a fixed voltage allowing the third transistor and the fourth transistor to operate as cascodes.

11. The device according to claim 8, wherein the compensation stage includes: a third transistor having a drain connected to the second terminal of the first resistor and a source connected to the current source so that the second terminal of the first resistor is connected to the current source via the third transistor; and a fourth transistor having a drain connected to the second terminal of the second resistor and a source connected to the drain of the first transistor so that the second terminal of the second resistor is connected to the drain of the first transistor via the fourth transistor; the third transistor and the fourth transistor each having a gate configured to receive a fixed voltage allowing the third transistor and the fourth transistor to operate as cascodes.

12. The device according to claim 8, wherein the reference branch comprises: a reference transistor of the at least one current mirror; a first cascode transistor having a drain configured to receive the reference current and connected to a gate of the reference transistor, a source connected to a drain of the reference transistor, and a gate configured to receive a fixed voltage; and a first selection transistor having a drain connected to a source of the reference transistor, a source connected to the cold point, and a gate configured to receive a voltage delivered by the at least one voltage regulator to the at least one electronic module.

13. The device according to claim 12, wherein each auxiliary current generation branch comprises: a copy transistor of the current mirror having a gate connected to the reference branch and being configured to at least partly generate the source current; a second cascode transistor having a drain connected to a second output of the at least one voltage regulator, and a source connected to a drain of the copy transistor; and a second selection transistor having a drain connected to a source of the copy transistor, a source connected to the cold point, and a gate configured to be controlled by a selection signal.

14. The device according to claim 13, wherein the second cascode transistor is common to each generation branch, the current source further including a third operational amplifier having a non-inverting input connected to the drain of the reference transistor, an inverting input connected to the source of the common second cascode transistor, and an output connected to the gate of the second cascode transistor.

15. An electronic device comprising: a power supply terminal configured to be connected to a power supply; at least one voltage regulator connected to the power supply terminal; at least one electronic module connected to the at least one voltage regulator; and a compensation circuit connected to the at least one voltage regulator, the compensation circuit including: a current source connected to the at least one voltage regulator; and a compensation stage including: a first resistor and a second resistor each having a first terminal connected to the power supply terminal, wherein the first resistor has a second terminal connected to the current source; a first transistor having a drain connected to a second terminal of the second resistor and a source connected to a cold point; a first operational amplifier having an inverting input connected to the second terminal of the first resistor, a non-inverting input connected to the second terminal of the second resistor, and an output connected to a gate of the first transistor; a second transistor connecting the current source and the compensation stage to the at least one voltage regulator; and a second operational amplifier having an output coupled to a gate of the second transistor, an inverting input connected to a source of the second transistor, and a non-inverting input configured to receive a voltage delivered by the at least one voltage regulator to the at least one electronic module.

16. The device according to claim 15, wherein the compensation stage includes: a third transistor having a drain connected to the second terminal of the first resistor and a source connected to the current source so that the second terminal of the first resistor is connected to the current source via the third transistor; and a fourth transistor having a drain connected to the second terminal of the second resistor and a source connected to the drain of the first transistor so that the second terminal of the second resistor is connected to the drain of the first transistor via the fourth transistor.

17. The device according to claim 15, wherein the current source comprises at least one current mirror configured to generate the source current from a reference current.

18. The device according to claim 17, wherein the current source includes: a reference branch comprising: a reference transistor of the at least one current mirror; a first cascode transistor having a drain configured to receive the reference current and connected to a gate of the reference transistor, a source connected to a drain of the reference transistor, and a gate configured to receive a fixed voltage; and a first selection transistor having a drain connected to a source of the reference transistor, a source connected to the cold point, and a gate configured to receive the voltage delivered by the at least one voltage regulator to the at least one electronic module; an auxiliary current generation branch for each current mirror including: a copy transistor of the current mirror having a gate connected to a gate of the reference transistor and being configured to at least partly generate the source current; a second cascode transistor having a drain connected to a second output of the at least one voltage regulator, and a source connected to a drain of the copy transistor; and a second selection transistor having a drain connected to a source of the copy transistor, and a source connected to the cold point.

19. The device according to claim 18, wherein the second selection transistor of the auxiliary current generation branch of each current mirror has a gate configured to be controlled by the selection signal.

20. The device according to claim 18, wherein the second cascode transistor is common to each generation branch, the current source further including a third operational amplifier having a non-inverting input connected to the drain of the reference transistor, an inverting input connected to the source of the common second cascode transistor, and an output connected to the gate of the second cascode transistor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Other advantages and features of the invention will appear upon examining the detailed description of non-limiting embodiments and the appended drawings wherein:

[0047] FIG. 1 illustrates an electronic device including an electronic module and a voltage regulator;

[0048] FIG. 2 illustrates an electronic device with a current source including a reference branch and at least one branch for generating current; and

[0049] FIG. 3 illustrates an electronic device including a single common transistor for each current generation branch, which transistor is controlled by an operational amplifier.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0050] FIG. 1 illustrates an electronic device DIS, in particular a system on chip, including an electronic module, in particular a microprocessor CPU, and an LDO voltage regulator. The LDO regulator is configured to adapt a voltage VCC provided by an electrical power supply source ALIM to a desired voltage to power supply the microprocessor CPU. For example, the LDO regulator can be adapted to provide a voltage of 1.2V to the microprocessor CPU from a voltage of 3V generated by the power supply source ALIM. The LDO voltage regulator can be of the low-dropout type (also known by the expression “low-dropout regulator” or “LDO regulator”).

[0051] The LDO voltage regulator has an input I1 connected to a power supply terminal BA of the electronic device DIS. The power supply terminal BA is configured to be able to be connected to the power supply source ALIM. The LDO regulator also has a first output O1 connected to a power supply terminal of the microprocessor CPU. In this way, the LDO voltage regulator is configured to draw a current I.sub.vdd delivered by the power supply source ALIM and to transmit this current to the microprocessor CPU. The value of current I.sub.vdd may vary depending on the operations that can be performed by the microprocessor.

[0052] The electronic device DIS also includes a compensation circuit JSCR configured to be able to draw a current I.sub.JSCR delivered by the power supply source ALIM, so that the total current I.sub.VCC drawn from the power supply source is constant regardless of the value of the current I.sub.vdd required by microprocessor CPU.

[0053] In particular, the compensation circuit JSCR includes a first input IN1 connected to a second output O2 of the LDO voltage regulator, and a second input IN2 connected to the power supply terminal BA of the electronic device DIS so as to be able to be connected to the power supply source ALIM.

[0054] The second output O2 of the voltage regulator is configured to deliver to the compensation circuit JSCR an auxiliary current I.sub.aux equal to I.sub.vdd/100, that is to say one hundredth of the current I.sub.vdd. For this purpose, the LDO voltage regulator may comprise a current mirror. The current mirror can then include a first branch having a first transistor having given dimensions, and a second branch having a second transistor with dimensions one hundred times smaller than those of the first transistor. The current mirror may also include on its first branch a number of identical transistors connected in parallel one hundred times greater than a number of identical transistors connected in parallel provided on its second branch.

[0055] The LDO regulator is therefore configured to draw a total current I.sub.VDD equal to the sum of the current I.sub.vdd required by the microprocessor and the current I.sub.aux equal to I.sub.vdd/100 delivered to the compensation circuit.

[0056] The compensation circuit JSCR may comprise a first amplifier AMP_LDO configured to control a gate of a first PMOS-type transistor PCASLDO. The amplifier AMP_LDO includes an inverting input connected to the second output O2 of the LDO regulator via the first input IN1 of the compensation circuit and to the source of the transistor PCASLDO. The amplifier AMP_LDO also includes a non-inverting input connected to the first output O1 of the LDO regulator so as to receive a voltage vdd! at the input of the microprocessor CPU. Thus, the first amplifier AMP_LDO and the transistor PCASLDO allow to obtain a potential at the second output O2 of the LDO regulator identical to the potential at the first output O1 of the LDO regulator so as to ensure a current I.sub.vdd/100 conforming to the current I.sub.vdd supplying the microprocessor CPU.

[0057] The compensation circuit JSCR further comprises a current source SC having a first terminal connected to the drain of the transistor PCASLDO and a second terminal connected to a cold point, in particular to a ground GND. The current source SC is of the NMOS-type and is thus configured to generate a current I.sub.src equal to I.sub.set/100 towards the cold point GND. The value of the current I.sub.set is chosen to be greater than a maximum of the current I.sub.vdd. The ratio between the current I.sub.src and the current I.sub.set is chosen to be identical to the ratio between the current I.sub.aux and I.sub.vdd. Embodiments of such a current source are described below in relation to FIGS. 2 and 3.

[0058] The compensation circuit JSCR further comprises a compensation stage. The compensation stage comprises an NMOS-type transistor CASMINUS. The transistor CASMINUS has a gate connected to the first output of the LDO regulator so as to receive a fixed voltage allowing the transistor CASMINUS to operate as a cascode. This fixed voltage may be the voltage vdd!. The transistor CASMINUS further includes a source connected to the first terminal of the current source and to the drain of the transistor PCASLDO.

[0059] The compensation stage CSTG includes a resistor R.sub.0 having a first terminal connected to the second input IN2 of the compensation circuit JSCR so as to be able to be connected to the power supply source ALIM and a second terminal connected to a drain of the transistor CASMINUS. The compensation stage also includes a resistor R.sub.1 having a first terminal connected to the first terminal of the resistor R.sub.0 and to the second input IN2 of the compensation circuit JSCR so as to be able to be connected to the power supply source ALIM. The value of the resistor R.sub.1 is chosen so that the ratio between the resistor R.sub.1 and the resistor R.sub.0 is the same as the ratio between the current I.sub.aux and I.sub.vdd, and the same as the ratio between the current I.sub.src and the current I.sub.set. For example, the resistor R.sub.1 has a value equal to R.sub.0/100. The transistor CASMINUS allows the potential at the second terminal of the resistor R.sub.0 to vary freely according to the current passing through this resistor R.sub.0.

[0060] The compensation stage CSTG also includes an NMOS-type transistor CASPLUS. The transistor CASPLUS has a gate connected to the first output of the LDO regulator so as to receive a fixed voltage allowing the transistor CASPLUS to operate as a cascode. This fixed voltage may be the voltage vdd!. The transistor CASPLUS also has a drain connected to a second terminal of the resistor R.sub.1.

[0061] The compensation stage CSTG also includes an NMOS-type transistor LV. The transistor LV has a drain connected to the source of the transistor CASPLUS and a source connected to the cold point, in particular to the ground. The transistor CASPLUS allows protection of the transistor LV from high voltages, and allows the potential at the second terminal of the resistor R.sub.1to vary freely according to the current passing through this resistor R.sub.1.

[0062] The compensation stage CSTG further comprises an operational amplifier AMP3 having an inverting input connected to the second terminal of the resistor R.sub.0 and a non-inverting input connected to the second terminal of the resistor R.sub.1. The operational amplifier AMP3 also has an output connected to the gate of the transistor LV so as to be able to control the transistor LV. Thus, the amplifier AMP3 allows obtaining of a potential at the second terminal of the resistor R.sub.1 identical to the potential at the second terminal of the resistor R.sub.0.

[0063] In this way, the resistor R.sub.0 is traversed by a current I.sub.int equal to (Iset-Ivdd)/100, and the resistor R.sub.1 is traversed by a current I.sub.SMT equal to Iset-Ivdd.

[0064] Thus, the current I.sub.VCC delivered by the power supply source ALIM is equal to the sum of the current I.sub.vdd required by the microprocessor CPU, the current I.sub.vdd/100 delivered at the second output O2 of the LDO regulator and the current I.sub.JSCR corresponding to the sum of the current I.sub.int passing through the resistor R.sub.0 and I.sub.SMT passing through the resistor R.sub.1. Thus, the current I.sub.VCC is expressed according to the following formula:

[00001]$I_{\mathrm{VCC}}=I_{\mathrm{VDD}}+I_{\mathrm{JSCR}}=I_{\mathrm{vdd}}+\left(I_{\mathrm{set}}-I_{\mathrm{vdd}}\right)=1.01*I_{\mathrm{set}}$

[0065] The current I.sub.VCC having the value 1.01*I.sub.set no longer depends on the current I.sub.vdd required by the microprocessor CPU, and is therefore constant.

[0066] Such a compensation circuit JSCR has the advantage of being relatively simple while allowing smoothing of the current drawn from the power supply source and being reactive to variations in the current I.sub.vdd required by the microprocessor CPU.

[0067] FIG. 2 illustrates an electronic device DIS as described previously whose current source SC allowing generating of the current I.sub.src is represented according to a first embodiment.

[0068] In this embodiment, the current source SC includes a reference branch BREF and at least one branch BGEN for generating current I.sub.src.

[0069] The reference branch includes an NMOS-type cascode transistor MCREF and each current generation branch BGEN includes an NMOS-type cascode transistor MCDAC. The transistors MCREF and MCDAC each have a gate configured to receive a fixed voltage vcas5u. The drain MCREF is configured to receive a reference current I.sub.ref, of 5 μA for example.

[0070] The current source SC further includes a current mirror MIR for each current generation branch BGEN. Each current mirror MIR allows multiplying of the reference current I.sub.ref in order to obtain the current I.sub.src equal to I.sub.set/100 at the output of the current source. In particular, the generation branch includes an NMOS-type transistor MMREF. This transistor MMREF has a drain connected to a source of the transistor MCREF, a gate connected to a drain of the transistor MCREF and a source connected to a drain of a transistor MSREF of the reference branch. This transistor MSREF also includes a source connected to the cold point, in particular to the ground, and a gate configured to receive the voltage vdd!.

[0071] Each current generation branch includes an NMOS-type transistor MMDAC<n:0> and an NMOS-type transistor MSDAC<n:0>. The transistor MMDAC<n:0> of each current generation branch has a gate connected to the gate of the transistor MMREF, a drain connected to a source of the transistor MCDAC<n:0> of this same current generation branch, and a source connected to a drain of the transistor MSDAC<n:0> of this same current generation branch. Thus, each current mirror comprises the transistor MMREF of the reference branch and a transistor MMDAC<n:0>of a current generation branch.

[0072] Each transistor MSDAC<n:0>has a gate allowing receiving of a selection signal SEL<n:0>, and a source connected to the cold point, in particular to the ground. The selection signals allow to activate or not the various current mirrors MIR.

[0073] The total current consumed by the compensation circuit is then equal to the sum of the current I.sub.src equal to I.sub.set/100 generated by the current source SC, a current consumed by the operational amplifier AMP_LDO and a current consumed by the operational amplifier AMP3. The total current consumed is therefore relatively low, and therefore has an advantage, especially for products requiring high power consumption.

[0074] Furthermore, it is also possible to increase the bias current of the amplifier AMP3 to improve the performance of the compensation circuit JSCR.

[0075] FIG. 3 illustrates an electronic device DIS as described previously whose current source SC allowing generating of the current I.sub.src equal to I.sub.set/100 is shown according to a second embodiment.

[0076] This second embodiment differs from the first embodiment in that it comprises a single common transistor MCDAC for each current generation branch. This transistor MCDAC is controlled by an operational amplifier AMP_CAS and not by the signal vcas5u.

[0077] In particular, the operational amplifier AMP_CAS has a non-inverting input connected to the drain of the transistor MMREF, and an inverting input connected to the drain of the transistor MMDAC.

[0078] In this way, the drain voltage of the transistor MMDAC is identical to the voltage at the drain of the transistor MCREF. It is thus possible to use a smaller transistor MCDAC allowing reducing of parasitic capacitances so that the compensation circuit is more reactive to current variations I.sub.vdd. The bandwidth of the amplifier does not impact the compensation circuit because the current I.sub.ref is constant.

[0079] The total current consumed by the compensation circuit is then equal to the sum of the current I.sub.set/100 generated by the current source, the current supplying the operational amplifier AMP_LDO, the current consumed by the operational amplifier AMP3 and the current Iamp_cas supplying the amplifier AMP_CAS. Such a total current is also relatively low compared to known compensation circuits.

[0080] Of course, the present invention is amenable to various variants and modifications which will occur to the person skilled in the art. For example, it is also possible to provide an electronic device including several LDO voltage regulators and several electronic modules connected to the various voltage regulators. The compensation circuit then has several inputs IN1 for the various voltage regulators so as to receive the auxiliary currents generated by the various regulators. The current source SC and the compensation stage CSTG are then connected to the various LDO regulators via several parallel branches connected to the inputs IN1, each branch including a transistor PCAS_LDO controlled by an operational amplifier AMP_LDO as described above.