Systems and Methods for Synthesis of Modulated RF Signals

Abstract

Systems and methods for synthesis of a modulated RF signal using a variety of modulation schemes are described. An embodiment includes a direct frequency synthesizer with frequency modulated continuous wave (FMCW) modulation that includes: a high speed BAW resonator that generates a frequency signal; a BAW oscillator that receives the frequency signal and generates an output BAW clock signal (BAW CLK); a frequency and phase estimation circuit that receives a reference clock signal from a reference clock (REF CLK) and the BAW CLK and generates a frequency error and a phase error; a frequency chirp generator that receives chirp parameters, a chirp sync signal and generates a nominal frequency control word (FCW); and a high speed digital to analog converter (HS DAC) that receives the BAW CLK and the codeword and outputs an analog signal.

Claims

1. A direct frequency synthesizer comprising: a high speed BAW resonator configured to generate a frequency signal; a BAW oscillator capable of receiving the frequency signal and configured to generate an output BAW clock signal (BAW CLK); a frequency and phase estimation circuit capable of receiving a reference clock signal from a reference clock (REF CLK) and the BAW CLK, where the frequency and phase estimation circuit is configured to generate a frequency error signal and a phase error signal; a frequency chirp generator capable of receiving chirp parameters, and a chirp sync signal, where the direct digital frequency synthesizer is configured to generate a sequence of nominal frequency control word (FCW); a frequency control word (FCW) generator that is capable of receiving an input FCW from the frequency chirp generator, and the phase error signal and the frequency error signal from the frequency and phase estimation circuit, where the FCW generator is configured to generate a corrected FCW based upon the input FCW, the phase error signal and the frequency error signal; a direct digital frequency synthesizer capable of receiving the BAW CLK and the corrected FCW, where the direct digital frequency synthesizer is configured to generate a codeword based upon the BAW CLK and the corrected FCW; and a high speed digital to analog converter (HS DAC) capable of receiving the BAW CLK and the codeword, where the HS DAC is configured to synthesize an analog signal.

2. The direct frequency synthesizer of claim 1, wherein the analog signal transmitted is a continuous wave that varies up and down in frequency over a fixed period by a modulated signal.

3. The direct frequency synthesizer of claim 1, wherein the FCW is generated according to chirp parameters specified by a user.

4. The direct frequency synthesizer of claim 1, wherein the frequency errors and phase errors are added to compensate for frequency and phase differences between the REF CLK and the BAW oscillator.

5. The direct frequency synthesizer of claim 1, wherein the analog signal is be specified in the following equation: $x\left(t\right)=\sin \left(2\pi \left(f_0+\frac{\alpha }{2}t\right)+{\theta }_0\right)$ wherein: f.sub.0: initial frequency of the chirp signal α: frequency ramp rate of the chirp signal θ.sub.0: initial phase of the chirp signal wherein a chirp signal is generated digitally and converted to the analog signal with the high-speed DAC, wherein a digital codeword x.sub.n can be specified in the following equation: $x_n=x\left(t={\mathrm{nT}}_s\right)=\sin \left({\theta }_n\right){\theta }_n=\{\begin{array}{c}{\theta }_0,n=0\\ {\theta }_{n-1}+2\pi f_{n-1}+\pi \alpha T_s^2,n>0\end{array}{f}_n=\{\begin{array}{c}{f}_0{T}_s,n=0\\ f_{n-1}+\alpha T_s^2,n>0\end{array}$ wherein: T.sub.s: sample period of the DAC clock f.sub.n: frequency at time t=nT.sub.s wherein, for non-stationary sample clock, digital codeword x.sub.n can be adjusted as follows: $x_n^{\prime }=x\left(t={\mathrm{nT}}_s^{\prime }\right)=\sin \left({\theta }_n^{\prime }\right){\theta }_n^{\prime }=\{\begin{array}{c}{\theta }_0,n=0\\ {\theta }_{n-1}^{\prime }+2\pi f_{n-1}^{\prime }+\pi {\alpha \left(T_s+\Delta T_s\right)}^2,n>0\end{array}{f}_n^{\prime }=\{\begin{array}{c}{f}_0\left(T_s+\Delta T_s\right),n=0\\ f_{n-1}^{\prime }+{\alpha \left(T_s+\Delta T_s\right)}^2,n>0\end{array}$ wherein: T.sub.s′: non-stationary sample period of the DAC clock (T.sub.s′=T.sub.s+ΔT.sub.s).

6. A direct frequency synthesizer comprising: a high speed BAW resonator configured to generate a frequency signal; a BAW oscillator capable of receiving the frequency signal and configured to generate an output BAW clock signal (BAW CLK); a frequency and phase estimation circuit capable of receiving a reference clock signal from a reference clock (REF CLK) and the BAW CLK, where the frequency and phase estimation circuit is configured to generate a frequency error signal and a phase error signal; a frequency hop frequency control word generator capable of receiving frequency hopping parameters, a sync signal, where the frequency hop frequency control word generator is configured to generate a sequence of nominal frequency control word (FCW); a frequency control word (FCW) generator that is capable of receiving an input FCW from the frequency hop frequency control word generator, and the frequency error signal and the phase error signal from the frequency and phase estimation circuit, wherein the frequency control word generator is configured to generate a corrected FCW based upon the input FCW, the frequency error signal, and the phase error signal; a direct digital frequency synthesizer capable of receiving the BAW CLK and the corrected FCW, where the direct digital frequency synthesizer is configured to generate a codeword based upon the BAW CLK and the corrected FCW; and a high speed digital to analog converter (HS DAC) capable of receiving the BAW CLK and the codeword, wherein the HS DAC is configured to output an analog signal.

7. The direct frequency synthesizer of claim 6, wherein an output frequency is changed from one frequency to another one controlled by a pseudo-random (PN) sequence.

8. The direct frequency synthesizer of claim 6, wherein a signal is expressed by the following equation:
x(t)=sin(2πf(t)t+θ.sub.0)
f(t)=f.sub.rand(n),t.sub.n-1≤t<t.sub.n,nϵ[1, . . . ,N] wherein: f.sub.1, . . . , f.sub.N: list of frequencies used in the frequency hopping system t.sub.1, . . . , t.sub.N: frequency hopping time rand(n): random frequency mapping in the frequency hopping system θ.sub.0: initial phase of the sine wave wherein: the frequency hopping signal is synthesized digitally and digital codeword x.sub.n is converted to the analog signal through the high-speed digital-to-analog converter (DAC); wherein: the relationship between x(t) and x.sub.n is given by the following equation:
x.sub.n=x(t=nT.sub.s)=sin(2πf(t)nT.sub.s+θ.sub.0)=sin(2πf.sub.c(t)n+θ.sub.0)
f.sub.c(t)=f.sub.rand(n)T.sub.s,t.sub.n-1≤t<t.sub.n,nϵ[1, . . . ,N] wherein: T.sub.s: sample period of the DAC clock wherein, if the sample clock is non-stationary, the digital codeword x.sub.n is adjusted so the output frequency stays at the desired frequency by the following equation:
x.sub.n′=x(t=nT.sub.s′)=sin(2πf(t)nT.sub.s′+θ.sub.0)=sin(2π(f.sub.c(t)+Δf.sub.c(t))n+θ.sub.0) wherein: T.sub.s: non-stationary sample period of the DAC clock (T.sub.s′=T.sub.s+ΔT.sub.s) Δf.sub.c(t): frequency control word error (Δf.sub.c(t)=f.sub.c(t)*ΔT.sub.s/T.sub.s).

9. A direct frequency synthesizer comprising: a high speed BAW resonator configured to generate a frequency signal; a BAW oscillator capable of receiving the frequency signal, where the BAW oscillator is configured to generate an output BAW clock signal (BAW CLK); a frequency and phase estimation circuit capable of receiving a reference clock signal from a reference clock (REF CLK) and the BAW CLK, where the frequency and phase estimation circuit is configured to generate a frequency error signal and a phase error signal; a code-modulated continuous wave (CMCW) generator capable of receiving CM parameters and a sync signal, where the CMCW generator is configured to generate a codeword; a variable interpolator/decimator (VID) capable of receiving the codeword from the CMCW generator, the phase error signal and the frequency error signal from the frequency and phase estimation circuit and the BAW CLK signal from the BAW oscillator, where the VID is configured to generate a corrected codeword; and a high speed digital to analog converter (HS DAC) capable of receiving the BAW CLK and the corrected codeword, where the HS DAC is configured to output an analog signal.

10. The direct frequency synthesizer of claim 9, wherein the CMCW modulates a high frequency continuous wave with a wide-band code sequence.

11. The direct frequency synthesizer of claim 9, wherein the codeword is a digital codeword x.sub.n; wherein x.sub.n is converted to the analog signal through the high-speed digital-to-analog converter (HS DAC); wherein x.sub.n corresponds to a desired analog signal at t=nT.sub.s where T.sub.s is the period of the sample clock; wherein, for a non-stationary sample clock where the sample time happens at t′=nT.sub.s′ or (nT.sub.s+ΔT.sub.s), the digital codeword is adjusted and the corrected codeword x.sub.n′ is calculated by the variable-interpolator-decimator (VID) by the following equation: $x_n^{\prime }=x\left(t={\mathrm{nT}}_s^{\prime }\right)=x\left(t={\mathrm{nT}}_s+\Delta T_s\right)=\{\begin{array}{cc}{x}_n\frac{1-\Delta T_s}{T_s}+x_{n+1}\frac{\Delta T_s}{T_s},& \Delta T_s\ge 0\\ x_n\frac{1+\Delta T_s}{T_s}-x_{n-1}\frac{\Delta T_s}{T_s},& \Delta T_s<0\end{array}$ wherein for all VID filters, codeword x.sub.n′ can be calculated as follows: $x_n^{\prime }=x\left(t={\mathrm{nT}}_s^{\prime }\right)=x\left(t={\mathrm{nT}}_s+\Delta T_s\right)=\underset{i=-L}{\overset{L}{.Math.}}h\left(i\right)*x_{n+i}$ wherein h(i): VID filter coefficients.

12. A direct frequency synthesizer comprising: a high speed BAW resonator configured to generate a frequency signal; a BAW oscillator capable of receiving the frequency signal, where the BAW oscillator is configured to generate an output BAW clock signal (BAW CLK); a frequency and phase estimation circuit capable of receiving a reference clock signal from a reference clock (REF CLK) and the BAW CLK from the BAW oscillator, where the frequency and phase estimation circuit is configured to generate a frequency error signal and a phase error signal; an orthogonal frequency-division multiplexing (OFDM) generator that is capable of receiving OFDM modulation parameters and a sync signal, where the OFDM generator is configured to generate a codeword; a variable interpolator/decimator (VID) that is capable of receiving the codeword from the OFDM generator, the phase error signal and the frequency error signal from the frequency and phase estimation circuit, and the BAW CLK from the BAW oscillator, where the VID is configured to generate a corrected codeword; and a high speed digital to analog converter (HS DAC) that is capable of receiving the BAW CLK from the BAW oscillator and the corrected codework from the VID, where the HS DAC is configured to output an analog signal.

13. The direct frequency synthesizer of claim 12, wherein an OFDM signal includes coded signals transmitted on multiple carriers continuously and in parallel.

14. The direct frequency synthesizer of claim 12, wherein the codeword is a digital codeword x.sub.n; wherein x.sub.n is converted to the analog signal through the high-speed digital-to-analog converter (HS DAC); wherein x.sub.n corresponds to a desired analog signal at t=nT.sub.s where T.sub.s is the period of the sample clock; wherein, for a non-stationary sample clock where the sample time happens at t′=nT.sub.s′ or (nT.sub.s+ΔT.sub.s), the digital codeword is adjusted and the corrected codeword x.sub.n′ is calculated by the variable-interpolator-decimator (VID) by the following equation: $x_n^{\prime }=x\left(t={\mathrm{nT}}_s^{\prime }\right)=x\left(t={\mathrm{nT}}_s+\Delta T_s\right)=\{\begin{array}{cc}{x}_n\frac{1-\Delta T_s}{T_s}+x_{n+1}\frac{\Delta T_s}{T_s},& \Delta T_s\ge 0\\ x_n\frac{1+\Delta T_s}{T_s}-x_{n-1}\frac{\Delta T_s}{T_s},& \Delta T_s<0\end{array}$ wherein For all VID filters, codeword x.sub.n′ can be calculated as follows: $x_n^{\prime }=x\left(t={\mathrm{nT}}_s^{\prime }\right)=x\left(t={\mathrm{nT}}_s+\Delta T_s\right)=\underset{i=-L}{\overset{L}{.Math.}}h\left(i\right)*x_{n+i}$ wherein h(i): VID filter coefficients.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0047] FIG. 1A conceptually illustrates a direct RF-transmitter in accordance with an embodiment of the invention.

[0048] FIG. 1B illustrates a circuit diagram of a single tone generator in accordance with an embodiment of the invention.

[0049] FIG. 2 illustrates a process for single tone generation in accordance with an embodiment of the invention.

[0050] FIG. 3 illustrates a circuit diagram of a frequency modulated continuous wave (FMCW) generator in accordance with an embodiment of the invention.

[0051] FIG. 4 illustrates a process for FMCW generation in accordance with an embodiment of the invention.

[0052] FIG. 5 illustrates a circuit diagram of a frequency hopping generator in accordance with an embodiment of the invention.

[0053] FIG. 6 illustrates a process for frequency hopping generation in accordance with an embodiment of the invention.

[0054] FIG. 7 illustrates a circuit diagram of a code-modulated continuous wave (CMCW) generator in accordance with an embodiment of the invention.

[0055] FIG. 8 illustrates a process for code-modulated continuous wave generation in accordance with an embodiment of the invention.

[0056] FIG. 9 illustrates a circuit diagram of an orthogonal frequency-division multiplexing (OFDM) generator in accordance with an embodiment of the invention.

[0057] FIG. 10 illustrates a process for OFDM generation in accordance with an embodiment of the invention.

DETAILED DESCRIPTION OF THE DRAWINGS

[0058] Turning now to the drawings, systems and methods in accordance with many embodiments of the invention synthesize a modulated RF signal using one of a variety of different modulation schemes including, but not limited to, amplitude shift keying, phase shift keying, quadrature phase shift keying, quadrature amplitude modulation, and/or amplitude phase shift keying.

[0059] In several embodiments, a sequence frequency control world for a direct digital frequency synthesizer is selected to synthesize a signal in which a symbol is modulated onto a controlled carrier frequency. The specific manner in which the frequency control words are selected depends upon the stability of a reference signal and/or the particular modulation scheme utilized for data transmission.

[0060] In the various architectures specified by U.S. patent application Ser. No. 15/470,616 issued as U.S. Pat. No. 10,530,372, entitled “Systems and Methods for Digital Synthesis of Output Signals Using Resonators” to Yu et al., the relevant disclosure from which including the disclosure related to architectures and device implementations is herein incorporated by reference, the sample clock for a DAC can be taken from a free running oscillator for improved phase noise performance. An example of a direct RF-transmitter using a direct frequency synthesizer in accordance with an embodiment of the invention is illustrated in FIG. 1. As illustrated, a direct-RF transmitter 100 receives a plurality of input signals 105 that are input to ‘n’ serializers/deserializers (SerDes RX) 110. Each serializer/deserializer 110 converts data between serial data and parallel interfaces in each direction. The outputs of the SerDes RXs 110 are provided to a data multiplexer select (Data Mux Sel) 120, whose outputs are provided to ‘n’ upconverters 130. The outputs of the upconverters 130 are provided to a channel multiplexer select (Chan Mux Sel) 140. The outputs of the Chan Mux Sel 140 is provided to an IFFT Upconverter 150. The output of the IFFT Upconverter 150 is provided to a 12G digital to analog converter 160.

[0061] BAW resonator 180 provides a resonant frequency to oscillator 1785, and this is provided as an input to the 12G DAC 160 and the SerDes RX 110. Furthermore, I2C and uController 195 provide outputs to the IFFT Upconverter 150. Although FIG. 1 illustrates an example circuit implementation for a direct RF-transmitter, any of a variety of different architectures may be utilized as appropriate to the requirements of specific applications in accordance with embodiments of the invention.

[0062] Described below are further details on implementations of the following modulation schemes that can be utilized by a direct RF-transmitter, including: Frequency Modulated Continuous Wave (FMCW), Frequency Diversity with Hopping, Code-modulated Continuous Wave (CMCW), Orthogonal Frequency-Division Multiplexing (OFDM), among others in accordance with many embodiments of the invention.

[0063] An analog sine wave can be specified in the following equation:

x(t)=sin(2πft+θ.sub.0)

[0064] f: frequency of the sine wave.

[0065] θ.sub.0: initial phase of the sine wave.

[0066] In a digital frequency synthesis architecture in accordance with many embodiments, digital codeword x.sub.n can be generated digitally and converted to an analog signal through a high-speed digital-to-analog converter (HS DAC). The relationship between x(t) and x.sub.n can be given by the following equation

x.sub.n=x(t=nT.sub.s)=sin(2πfnT.sub.s+θ.sub.0)=sin(2πf.sub.cn+θ.sub.0)

[0067] T.sub.s: sample period of the DAC clock.

[0068] f.sub.c: digital frequency control word (f.sub.c=fT.sub.s).

[0069] As noted above, in certain architectures specified by U.S. patent application Ser. No. 15/470,616 issued as U.S. Pat. No. 10,530,372, entitled “Systems and Methods for Digital Synthesis of Output Signals Using Resonators” to Yu et al., the sample clock for a DAC can be taken from a free running oscillator for improved phase noise performance. In many embodiments, the sample clock may not be stationary and can change in frequency over time. Accordingly, in many embodiments, the digital codeword x.sub.n may need to be adjusted so the output frequency stays constant. This adjustment can be illustrated by the following equation:

x.sub.n′=x(t=nT.sub.s′)=sin(2πfnT.sub.s′+θ.sub.0)=sin(2π(f.sub.c+Δf.sub.c)n+θ.sub.0)

[0070] Where:

[0071] T.sub.s′: non-stationary sample period of the DAC clock (T.sub.s′=T.sub.s+ΔT.sub.s)

[0072] Δf.sub.c: frequency control word error (Δf.sub.c=f*ΔT.sub.s).

[0073] A circuit architecture for a single tone generator in accordance with an embodiment of the invention is shown in FIG. 1B. As illustrated, the system includes a frequency/phase estimation circuit, a BAW oscillator that generates a BAW CLK, a BAW resonator, a direct digital frequency synthesizer (DDFS), and a high speed digital to analog convertor (HS DAC).

[0074] The frequency/phase estimation circuit can receive a reference clock (REF CLK) and the BAW CLK and generate a frequency error that is added to a nominal frequency control word (FCW) to generate a corrected FCW that is then provided to the DDFS. The DDFS can receive also the BAW clock and output a codeword to the HS DAC. Although FIG. 1B illustrates a particular circuit architecture of a single tone generator, any of a variety of architectures can be specified as appropriate to the requirements of a particular application in accordance with various embodiments of the invention.

[0075] A process for signal synthesis in accordance with an embodiment of the invention is illustrated in FIG. 2. As illustrated, a frequency/phase estimation circuit can receive a reference clock (REF CLK) and a BAW CLK and generate a frequency error that is provided to a frequency control word (FCW) generation circuit. The FCW generation circuit can also obtain a nominal FCW in order to generate a corrected FCW that is provided to a DDFS processing circuit to generate a codeword that is provided to a DAC. Although a specific process is illustrated in FIG. 2, any of a variety of processes can be utilized to generate a frequency tone as appropriate to the requirements of a specific application in accordance with an embodiment of the invention.

[0076] Furthermore, although FIG. 1B illustrates a single frequency tone generation architecture, this architecture can be extended beyond single frequency tone generation. Described below are several signal generation architectures for frequency tone generation in accordance with various embodiments of the invention.

FMCW Generation

[0077] In a frequency modulated continuous wave (FMCW) system in accordance with many embodiments, a transmitted signal can be a continuous wave that varies up and down in frequency over a fixed period by a modulated signal. FMCW may also be known as frequency chirp. FMCW systems in accordance with many embodiments can be used in radar applications among various other applications and can measure a distance and relative velocity simultaneously.

[0078] An FMCW signal can be specified in the following equation:

[00008]$x\left(t\right)=\sin \left(2\pi \left(f_0+\frac{\alpha }{2}t\right)t+{\theta }_0\right)$

[0079] Where:

[0080] f.sub.0: initial frequency of the chirp signal

[0081] α: frequency ramp rate of the chirp signal

[0082] θ.sub.0: initial phase of the chirp signal.

[0083] Similarly, a chirp signal can be generated digitally and converted to an analog signal with a high-speed DAC. Digital codeword x.sub.n can be specified in the following equation:

[00009]$x_n=x\left(t={\mathrm{nT}}_s\right)=\sin \left({\theta }_n\right){\theta }_n=\{\begin{array}{c}{\theta }_0,n=0\\ {\theta }_{n-1}+2\pi f_{n-1}+\pi \alpha T_s^2,n>0\end{array}{f}_n=\{\begin{array}{c}{f}_0{T}_s,n=0\\ f_{n-1}+\alpha T_s^2,n>0\end{array}$

[0084] T.sub.s: sample period of the DAC clock.

[0085] f.sub.n: frequency at time t=nT.sub.s.

[0086] For a non-stationary sample clock, digital codeword x.sub.n can be adjusted as follows:

[00010]$x_n^{\prime }=x\left(t={\mathrm{nT}}_s^{\prime }\right)=\sin \left({\theta }_n^{\prime }\right){\theta }_n^{\prime }=\{\begin{array}{c}{\theta }_0,n=0\\ {\theta }_{n-1}^{\prime }+2\pi f_{n-1}^{\prime }+\pi {\alpha \left(T_s+\Delta T_s\right)}^2,n>0\end{array}{f}_n^{\prime }=\{\begin{array}{c}{f}_0\left(T_s+\Delta T_s\right),n=0\\ f_{n-1}^{\prime }+{\alpha \left(T_s+\Delta T_s\right)}^2,n>0\end{array}$

[0087] T.sub.s′: non-stationary sample period of the DAC clock (T.sub.s′=T.sub.s+ΔT.sub.s).

[0088] An FMCW generation architecture for digital synthesis using a resonator in accordance with an embodiment of the invention is illustrated in FIG. 3. As illustrated in FIG. 3, the architecture can include a frequency chirp generator circuit, a frequency/phase estimation circuit, a DDFS, an HS DAC, a BAW resonator, and a BAW oscillator. The frequency/phase estimation circuit can receive a REF CLK and a BAW CLK and generate a phase error and frequency error. The frequency chirp generator can receive chirp parameters, a chirp sync signal and generate a nominal FCW that is provided to an adder that receives the phase error and frequency error and generates a corrected FCW that is provided to the DDFS. The DDFS can receive the BAW CLK and the corrected FCW and generate a codeword that is provided to the HS DAC. The HS DAC can generate a chirp output. Although FIG. 3 illustrates a particular FMCW generator circuit architectures, any of a variety of FMCW circuit architectures can be utilized as appropriate to the requirements of a specific application in accordance with an embodiment of the invention.

[0089] A process for FMCW generation in accordance with an embodiment of the invention is illustrated in FIG. 4. In many embodiments, a frequency control word (FCW) can be generated according to the chirp parameters specified by a user. Frequency and phase errors can be added to compensate for frequency and phase differences between a REF CLK and a BAW CLK from a BAW oscillator. As illustrated in FIG. 4, the frequency/phase estimation circuit can obtain a REF CLK and a BAW CLK and generate a phase error and a frequency error that is provided to an FCW generation circuit. The FCW generation circuit can obtain a nominal FCW from a chirp FCW generation circuit that uses a chirp sync signal and chirp parameters to generate the nominal FCW signal. The FCW generation circuit can generate a corrected FCW that is provided to a DDFS processing circuit. The DDFS processing circuit can generate a codeword that is provided to a HS DAC. Although a specific process is illustrated in FIG. 4, any of a variety of processes can be utilized for FMCW generation as appropriate to the requirements of a specific application in accordance with an embodiment of the invention.

[0090] In many embodiments, an FMCW architecture can offer several advantages over analog PLL implementations including perfectly linear frequency modulation (digital implementation), ultra-low phase noise (set by the quality of resonator), and very fast frequency modulation rate.

Frequency Diversity with Hopping Generation

[0091] In many embodiments of the system, frequency diversity can be used for interference mitigation in different applications, including radar applications. Frequency hopping is an implementation of frequency diversity. In a frequency hopping system in accordance with many embodiments of the system, the output frequency can be changed from one frequency to another one controlled by a pseudo-random (PN) sequence.

[0092] A frequency hopping signal can be expressed by the following equation:

x(t)=sin(2πf(t)t+θ.sub.0)

f(t)=f.sub.rand(n),t.sub.n-1≤t<t.sub.n,nϵ[1, . . . ,N]

[0093] Where:

[0094] f.sub.1, . . . , f.sub.N: list of frequencies used in the frequency hopping system

[0095] t.sub.1, . . . , t.sub.N: frequency hopping time

[0096] rand(n): random frequency mapping in the frequency hopping system

[0097] θ.sub.0: initial phase of the sine wave.

[0098] In many embodiments, a frequency hopping signal can be synthesized digitally and a digital codeword x.sub.n can be converted to an analog signal through a high-speed digital-to-analog converter (HS DAC).

[0099] The relationship between x(t) and x.sub.n is given by the following equation:

x.sub.n=x(t=nT.sub.s)=sin(2πf(t)nT.sub.s+θ.sub.0)=sin(2πf.sub.c(t)n+θ.sub.0)

f.sub.c(t)=f.sub.rand(n)T.sub.s,t.sub.n-1≤t<t.sub.n,nϵ[1, . . . ,N]

[0100] T.sub.s: sample period of the DAC clock.

[0101] If the sample clock is non-stationary, the digital codeword x.sub.n, may need to be adjusted so the output frequency stays at the desired frequency. This adjustment can be illustrated by the following equation:

x.sub.n′=x(t=nT.sub.s′)=sin(2πf(t)nT.sub.s′+θ.sub.0)=sin(2π(f.sub.c(t)+Δf.sub.c(t))n+θ.sub.0)

[0102] T.sub.s′: non-stationary sample period of the DAC clock (T.sub.s′=T.sub.s+ΔT.sub.s).

[0103] Δf.sub.c(t): frequency control word error (Δf.sub.c(t)=f.sub.c(t)*ΔT.sub.s/T.sub.s).

[0104] A frequency hopping generator circuit in accordance with an embodiment of the invention is shown in FIG. 5. The frequency hopping generator circuit can include a frequency/phase estimation circuit that receives a REF CLK, a BAW CLK from a BAW oscillator and generates a phase error and a frequency error, a frequency hop generator that receives frequency hopping parameters an a sync signal and generates a nominal frequency control word (FCW), an adder that combines the nominal FCW with the frequency error and the phase error to generate a corrected FCW and provides it to a DDFS, the DDFS can output a codeword to an HS DAC. Although FIG. 5 illustrates a particular circuit architecture for a frequency hopping generator, any of a variety of circuit architectures can be utilized as appropriate to the requirements of a specific application in accordance with an embodiment of the invention. A process for frequency hopping generation in accordance with an embodiment of the invention is illustrated in FIG. 6.

[0105] In many embodiments, FCW generation can be controlled by a PN sequence. As illustrated in FIG. 6, the frequency/phase estimation circuit can receive a REF CLK and a BAW CLK and generate a phase error and a frequency error that is provided to an FCW generation circuit. An F/H FCW generation circuit can receive a sync signal and a frequency hopping parameters and generate a nominal FCW signal that is provided to the FCW generation circuit. The FCW generation circuit can generate a corrected FCW that is provided to a DDFS processing circuit. The DDFS processing circuit can receive the corrected FCW and the BAW CLK and can output a codeword to a HS DAC. Although a specific process is illustrated in FIG. 6, any of a variety of processes can be utilized for frequency hopping generation as appropriate to the requirements of a specific application in accordance with an embodiment of the invention. The digital synthesis architecture in accordance with many embodiments of the invention can offers several advantages over analog implementations, including instantaneous frequency change without the unknown frequency settling in PLL, and ultra-low phase noise (set by the quality of resonator).

Code-modulated Continuous Wave Generation (CMCW)

[0106] In many embodiments, code-modulated continuous wave (CMCW) generation systems can modulate a high frequency continuous wave with a wide-band code sequence.

[0107] In many embodiments, a digital CMCW generator can be used to generate digital codeword x.sub.n. x.sub.n can be converted to an analog signal through a high-speed digital-to-analog converter (HS DAC). x.sub.n corresponds to the desired analog signal at t=nT.sub.s where T.sub.s is the period of the sample clock. For a non-stationary sample clock where the sample time happens at t′=nT.sub.s′ or (nT.sub.s+ΔT.sub.s), the digital codeword may need to be adjusted and the new codeword x.sub.n′ can be calculated by a variable-interpolator-decimator (VID). An example of linear VID can be shown by the following equation:

[00011]$x_n^{\prime }=x\left(t={\mathrm{nT}}_s^{\prime }\right)=x\left(t={\mathrm{nT}}_s+\Delta T_s\right)=\{\begin{array}{cc}{x}_n\frac{1-\Delta T_s}{T_s}+x_{n+1}\frac{\Delta T_s}{T_s},& \Delta T_s\ge 0\\ x_n\frac{1+\Delta T_s}{T_s}-x_{n-1}\frac{\Delta T_s}{T_s},& \Delta T_s<0\end{array}$

[0108] For all VID filters, codeword x.sub.n′ can be calculated as follows:

[00012]$x_n^{\prime }=x\left(t={\mathrm{nT}}_s^{\prime }\right)=x\left(t={\mathrm{nT}}_s+\Delta T_s\right)=\underset{i=-L}{\overset{L}{.Math.}}h\left(i\right)*x_{n+i}$ [0109] h(i): VID filter coefficients.

[0110] A circuit architecture of a CMCW generator in accordance with an embodiment of the invention is illustrated in FIG. 7. The CMCW circuit can include a frequency/phase estimation circuit that can receive a REF CLK signal and generate the phase error and the frequency error. A CMCW generator can receive CM parameters, a sync signal, and the REF CLK signal and provide a codeword to a variable interpolator/decimator (VID). The VID can receive the phase error, frequency error from a frequency/phase estimation circuit, the codeword from the CMCW generator, and a BAW CLK signal from a BAW oscillator and generated a corrected codeword to the HS DAS. The HS DAC can generate a modulator output. Although FIG. 7 illustrates a particular circuit architecture for a code-modulated CW generator, any of a variety of circuit architectures can be utilized as appropriate to the requirements of a specific application in accordance with various embodiments of the invention.

[0111] A process for code-modulated CW generation in accordance with an embodiment of the invention is illustrated in FIG. 8. In many embodiments, the modulated signal can be first generated in the REF CLK domain and re-sampled into the BAW CLK domain through a variable interpolator-decimator (VID). As illustrated in FIG. 8, the frequency/phase estimation circuit can receive a REF CLK and a BAW CLK and generate a phase error and a frequency error that is provided to a VID processing circuit. A code-modulated CW generator can receive a sync signal and CM parameters and generate a codeword that is provided to the VID processing circuit. The VID processing circuit can generate a corrected codeword that is provided to a DAC. Although a specific process is illustrated in FIG. 8, any of a variety of processes can be utilized for code-modulated CW generation as appropriate to the requirements of a specific application in accordance with various embodiments of the invention.

[0112] The code-modulated CW digital synthesis architecture can offer an advantage over analog implementations including providing ultra-low phase noise (set by the quality of resonator).

OFDM Generation

[0113] In many embodiments, an OFDM signal can include coded signals transmitted on multiple carrier frequencies (called subcarriers), continuously and in parallel. A digital OFDM modulator in accordance with several embodiments of the invention can be used to generate digital codeword x.sub.n, which can be converted to an analog signal through a high-speed digital-to-analog converter (DAC). x.sub.n corresponds to the desired analog signal at t=nT.sub.s where T.sub.s is the period of the sample clock. For a non-stationary sample clock where the sample time happens at t′=nT.sub.s′ or (nT.sub.s+ΔT.sub.s), the digital codeword may need to be adjusted and the new codeword x.sub.n′ can be calculated by a variable-interpolator-decimator (VID) in accordance with many embodiments of the invention. An example of a linear VID in accordance with several embodiments of the invention can be shown by the following equation:

[00013]$x_n^{\prime }=x\left(t={\mathrm{nT}}_s^{\prime }\right)=x\left(t={\mathrm{nT}}_s+\Delta T_s\right)=\{\begin{array}{cc}{x}_n\frac{1-\Delta T_s}{T_s}+x_{n+1}\frac{\Delta T_s}{T_s},& \Delta T_s\ge 0\\ x_n\frac{1+\Delta T_s}{T_s}-x_{n-1}\frac{\Delta T_s}{T_s},& \Delta T_s<0\end{array}$

For all VID filters, codeword x.sub.n′ can be calculated as follows:

[00014]$x_n^{\prime }=x\left(t={\mathrm{nT}}_s^{\prime }\right)=x\left(t={\mathrm{nT}}_s+\Delta T_s\right)=\underset{i=-L}{\overset{L}{.Math.}}h\left(i\right)*x_{n+i}$ [0114] h(i): VID filter coefficients.

[0115] An OFDM generator circuit architecture in accordance with an embodiment of the invention is illustrated in FIG. 9. The OFDM can include a frequency/phase estimation circuit that can receive a symbol CLK and generate the phase error and frequency error. The OFDM generator circuit architecture can include an OFDM modulator that receives OFDM parameters and a sync signal and generates a codeword that is provided to a variable interpolator/decimator (VID). THE VID can also receive signals representing the phase error and the frequency error from a frequency/phase estimation circuit, and a BAW CLK signal from a BAW oscillator. The VID can output a corrected codeword to an HS DAC. The HS DAC can also receive a BAW CLK from the BAW oscillator. THE HS DAC can generate a modulator output. Although FIG. 9 illustrates a particular circuit architecture for an OFDM generator, any of a variety of circuit architectures can be utilized as appropriate to the requirements of a specific application in accordance with various embodiments of the invention.

[0116] A process for OFDM generation in accordance with an embodiment of the invention is illustrated in FIG. 10. In many embodiments, the modulated signal can be first generated in the OFDM symbol clock domain and re-sampled into the BAW clock domain through a variable interpolator-decimator (VID). As illustrated in FIG. 10, the frequency/phase estimation circuit can receive a REF CLK and a BAW CLK and generate a phase error and a frequency error that is provided to a VID processing circuit. An OFDM modulator can receive a sync signal and OFDM parameters and generate a codeword that is provided to the VID processing circuit. The VID processing circuit can generate a corrected codeword that is provided to a DAC. Although a specific process is illustrated in FIG. 10, any of a variety of processes can be utilized for OFDM generation as appropriate to the requirements of a specific application in accordance with various embodiments of the invention.

[0117] The OFDM digital synthesis architecture in accordance with many embodiments of the invention can offer advantages over the analog implementations including providing for ultra-low phase noise (set by the quality of resonator).

[0118] Although the present invention has been described in certain specific aspects, many additional modifications and variations would be apparent to those skilled in the art. It is therefore to be understood that the present invention may be practiced otherwise than specifically described, including various changes in the implementation. Thus, embodiments of the present invention should be considered in all respects as illustrative and not restrictive.