Voltage Regulator with Supply Noise Cancellation

Abstract

Power supply noise reduction methods and low drop out (LDO) voltage regulators with capacitively coupled supply noise-reducing components are disclosed. One illustrative voltage regulator includes: a pass transistor having an n-type conduction channel that couples a supply voltage to an output node; an operational amplifier that derives a control signal for the pass transistor from a difference between a reference voltage and a scaled or unscaled voltage of the output node, the control signal being supplied to a gate or base of the pass transistor; a buffer that derives a ripple cancellation signal from the supply voltage; and a coupling capacitor that couples the buffer to the base or gate of the pass transistor to impose the ripple cancellation signal on the control signal.

Claims

1. A low drop-out (LDO) voltage regulation circuit that comprises: a pass transistor having an n-type conduction channel that couples a supply voltage to an output node; an operational amplifier that derives a control signal for the pass transistor from a difference between a reference voltage and a scaled or unscaled voltage of the output node, the control signal being supplied to a gate or base of the pass transistor; a buffer that derives a ripple cancellation signal from the supply voltage; and a coupling capacitor connected between the buffer and the base or gate of the pass transistor to impose the ripple cancellation signal on the control signal.

2. The circuit of claim 1, further comprising a feedforward capacitor coupling the supply voltage to an input of the buffer.

3. The circuit of claim 2, wherein a bias voltage is supplied to the input of the buffer via a feedforward resistor, and wherein the feedforward resistor and feedforward capacitor jointly act as a high pass filter.

4. The circuit of claim 1, wherein the pass transistor is an n-type metal oxide semiconductor (NMOS) transistor.

5. The circuit of claim 4, wherein the buffer is an inverting buffer comprising a first NMOS transistor in series with a second NMOS transistor, the first NMOS transistor having a fixed bias and the second NMOS transistor having a gate capacitively coupled to the supply voltage to generate the ripple cancellation signal on an intermediate node between the first and second NMOS transistors.

6. The circuit of claim 4, wherein the pass transistor has a gate capacitance, wherein the buffer has a gain of about minus one, and wherein a ratio of the gate capacitance to the coupling capacitor determines a scaling factor for the ripple cancellation signal.

7. The circuit of claim 1, further comprising a resistive voltage divider that provides the scaled voltage of the output node to an inverting node of the operational amplifier.

8. A low drop-out (LDO) voltage regulation method that comprises: coupling a supply voltage to an output node using a pass transistor having an n-type conduction channel; using an operational amplifier to derive a control signal for the pass transistor from a difference between a reference voltage and a scaled or unscaled voltage of the output node; deriving a ripple cancellation signal from the supply voltage with a buffer; supplying the control signal to a gate or base of the pass transistor; and imposing the ripple cancellation signal on the control signal via a coupling capacitor that directly connects the buffer to the base or gate of the pass transistor.

9. The method of claim 8, further comprising: capacitively coupling the supply voltage to an input of the buffer with a feedforward capacitor.

10. The method of claim 9, further comprising: supplying a bias voltage to the input of the buffer via a feedforward resistor, wherein the feedforward resistor and feedforward capacitor jointly act as a high pass filter.

11. The method of claim 8, wherein the pass transistor is an n-type metal oxide semiconductor (NMOS) transistor.

12. The method of claim 11, wherein the buffer is an inverting buffer comprising a first NMOS transistor in series with a second NMOS transistor, the first NMOS transistor having a fixed bias and the second NMOS transistor having a gate capacitively coupled to the supply voltage to generate the ripple cancellation signal on an intermediate node between the first and second NMOS transistors.

13. The method of claim 11, wherein the pass transistor has a gate capacitance, wherein the buffer has a gain of about minus one, and wherein a ratio of the gate capacitance to the coupling capacitor determines a scaling factor for the ripple cancellation signal.

14. The method of claim 8, further comprising using a resistive voltage divider to provide the scaled voltage of the output node to an inverting node of the operational amplifier.

15. A computer-readable information storage medium that stores a hardware description language design of a low drop-out (LDO) voltage regulation circuit, the design specifying: a pass transistor having an n-type conduction channel that couples a supply voltage to an output node; an operational amplifier that derives a control signal for the pass transistor from a difference between a reference voltage and a scaled or unscaled voltage of the output node, the control signal being supplied to a gate or base of the pass transistor; a buffer that derives a ripple cancellation signal from the supply voltage; and a coupling capacitor that directly connects the buffer to the base or gate of the pass transistor to impose the ripple cancellation signal on the control signal.

16. The medium of claim 15, wherein the design further specifies a feedforward capacitor coupling the supply voltage to an input of the buffer.

17. The medium of claim 16, wherein the design further specifies a feedforward resistor to supply a bias voltage the input of the buffer via a feedforward resistor, and wherein the feedforward resistor and feedforward capacitor jointly act as a high pass filter.

18. The medium of claim 15, wherein the pass transistor is an n-type metal oxide semiconductor (NMOS) transistor.

19. The medium of claim 18, wherein the buffer is an inverting buffer comprising a first NMOS transistor in series with a second NMOS transistor, the first NMOS transistor having a fixed bias and the second NMOS transistor having a gate capacitively coupled to the supply voltage to generate the ripple cancellation signal on an intermediate node between the first and second NMOS transistors.

20. The medium of claim 18, wherein the pass transistor has a gate capacitance, wherein the buffer has a gain of about minus one, and wherein a ratio of the gate capacitance to the coupling capacitor determines a scaling factor for the ripple cancellation signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG. 1 is a schematic of an illustrative low drop out (LDO) voltage regulator circuit.

[0009] FIG. 2 is a schematic of a relatively complex voltage regulator circuit.

[0010] FIG. 3 is a schematic of an illustrative voltage regulator circuit having capacitively coupled supply noise cancellation.

DETAILED DESCRIPTION

[0011] Note that the specific embodiments given in the drawings and following description do not limit the disclosure. On the contrary, they provide the foundation for one of ordinary skill to discern the alternative forms, equivalents, and modifications that are encompassed in the claim scope.

[0012] FIG. 1 shows a voltage regulator circuit 100, which may be a circuit block specified in the form of an HDL design and implemented as an integrated circuit on a semiconducting substrate. The voltage regulator circuit 100 is a low dropout (LDO) voltage regulator, and as such, it includes a pass transistor M0 coupling a power supply voltage V.sub.IN to a regulated voltage node V.sub.OUT for powering a load circuit 102. The load circuit is represented here as an output capacitance C.sub.OUT and a variable current sink I.sub.OUT that consumes power from the regulated voltage node V.sub.OUT. For SerDes modules, it is desired to maintain the regulated voltage V.sub.OUT at a constant value even as the current draw varies from nearly zero to hundreds of milliamps.

[0013] Pass transistor M0 is an n-channel metal oxide semiconductor (NMOS) transistor, having a gate that receives a control signal V.sub.C from operational amplifier 104. The operational amplifier 104 receives a reference voltage V.sub.REF at its non-inverting input V.sub.+ and an unscaled or scaled version of the regulated voltage V.sub.OUT at its inverting input V.sub.−, amplifying the difference between the two to drive the gate of the pass transistor M0. There are many suitable ways to generate the reference voltage V.sub.REF available in the academic literature, though a bandgap voltage reference may be preferred due to stability and ease of implementation.

[0014] As such reference voltages are typically a fraction of the desired regulated voltage V.sub.OUT, a resistive voltage divider 106 may be used for scaling. Voltage divider 106 supplies a scaled voltage V.sub.OUT*R.sub.2/(R.sub.1+R.sub.2) to the inverting input V.sub.− of operational amplifier 104. So long as the supply voltage V.sub.IN sufficiently exceeds the desired voltage V.sub.OUT, amplifier 104 provides negative feedback, raising the control signal voltage V.sub.C (and regulated voltage V.sub.OUT) when the inverting input voltage V.sub.− is less than noninverting input voltage V.sub.+ and lowering the control signal voltage (and V.sub.OUT) when the inverting input voltage V.sub.− is greater than noninverting input voltage V.sub.+. In this fashion, amplifier 104 forces the difference between its input terminals to zero, thereby setting V.sub.OUT=V.sub.REF*(R.sub.1+R.sub.2)/R.sub.2.

[0015] Ideally, the regulated voltage V.sub.OUT is independent of the supply voltage V.sub.IN, and so long as the supply voltage's rate of variation does not exceed the amplifier's ability to adjust the control voltage, the performance is close to ideal. However, the pass transistor's inherent gate capacitance C.sub.G combines with the amplifier's output conductance to impose an upper limit on the rate of variation that can be corrected and thus an upper limit on the noise frequencies that can be suppressed.

[0016] It should be noted, however, that an intrinsic input capacitance (possibly augmented with a discrete or integrated input capacitor) C.sub.IN cooperates with the power supply impedance to act as a low pass filter that suppresses power supply noise above a certain cutoff frequency. For feasible combinations of input capacitance and supply impedance, this cutoff frequency is well above the upper limit that amplifier 104 can cope with. These two frequencies define an intermediate of noise frequencies that can leak through the illustrative voltage regulator to cause undesired variation in the regulated voltage V.sub.OUT. As one example, the range of intermediate frequencies is 2 megahertz to 10 megahertz for certain contemplated voltage regulator embodiments.

[0017] FIG. 2 shows an illustrative voltage regulator circuit 200 having added complexity to improve suppression of intermediate noise frequencies. Unlike voltage regulator circuit 100, voltage regulator circuit 200 employs a p-channel metal oxide semiconductor (PMOS) transistor as its pass transistor M.sub.P. (NMOS transistors conduct better for higher voltages whereas PMOS transistors conduct better for lower voltages.) To enable negative feedback for the PMOS pass transistor M.sub.P, the reference voltage V.sub.REF is provided to the inverting input V.sub.− of operational amplifier 204, while the scaled output voltage V.sub.OUT*R.sub.2/(R.sub.1+R.sub.2) is provided to the non-inverting input V.sub.+. Amplifier 204 amplifies the difference between V.sub.+ and V.sub.− to provide the feedback signal V.sub.FB.

[0018] A summing amplifier 208 combines the feedback signal V.sub.FB with a feed forward signal V.sub.FF to produce supply a control signal Vs to the gate of pass transistor M.sub.P. The control signal Vs is expressible as

[00001]$V_S=\left(1+\frac{R_{S1}}{R_{S2}}+\frac{R_{S1}}{R_{S3}}\right)V_{\mathrm{FB}}-\frac{R_{S1}}{R_{S3}}{V}_{\mathrm{FF}}.$

[0019] A feed forward amplifier 210 produces the feed forward signal V.sub.FF, which is expressible as

[00002]$V_{\mathrm{FF}}=V_B+\left(V_B-V_{\mathrm{IN}}\right)R_{\mathrm{FF}2}\left(\frac{1}{R_{\mathrm{FF}1}}+j\omega C_{\mathrm{FF}}\right).$

The feed forward amplifier acts as a high pass filter for frequencies in excess of approximately 1/2πR.sub.FF1C.sub.FF, which can be chosen so that the feed forward signal V.sub.FF represents the middle-frequency noise components of the supply voltage. The resistances of the summing amplifier 208 enable the control voltage to suppress these noise components from the regulated voltage V.sub.OUT.

[0020] The use of two additional operational amplifiers and their supporting components significantly increases circuit complexity, consuming more area, more power, and necessitating careful calibration for correct performance. The use of a PMOS pass transistor M.sub.P, which relies on reduced-mobility charge carriers, further limits the efficiency and performance of regulator circuit 200.

[0021] In contrast, the illustrative voltage regulator circuit 300 of FIG. 3 retains most of the simplicity of circuit 100, adding only an inverting buffer 310 with AC-coupling capacitors C.sub.FF and C.sub.C. The inverting buffer 310 is implementable as two NMOS transistors M1, M2, in series. Transistor M1 is coupled between ground and an intermediate node, while transistor M2 is coupled between the intermediate node and supply voltage V.sub.IN. A bias voltage V.sub.B2 is coupled to the gate of transistor M2, causing it to act essentially as a constant current source. A resistor R.sub.FF couples a corresponding bias voltage V.sub.B1 to the gate of transistor M1 so that in the absence of supply voltage variations, M1 acts as a current sink matched to the constant current source M2.

[0022] Coupling capacitor C.sub.FF couples variations of the supply voltage V.sub.IN to the gate of current sink transistor M1, producing a ripple cancellation signal voltage V.sub.RC on the intermediate node. Coupling capacitor C.sub.FF combines with resistor R.sub.FF to act as a high pass filter. For supply voltage variations having frequencies above 1/2πR.sub.FFC.sub.FF, the cancellation signal voltage V.sub.RC includes negative variations at the corresponding frequencies. Inverting buffer 310 can be configured to provide a gain of −1 for the range of intermediate noise frequencies described above. Coupling capacitor C.sub.C and gate capacitance C.sub.G can act as an impedance voltage divider, scaling the cancellation signal V.sub.RC by 1/(1+C.sub.G/C.sub.C). The gate voltage of pass transistor M0 is the control signal V.sub.C (see FIG. 1) with a superimposed scaled cancellation signal V.sub.RC:

[00003]$V_G=V_C+\frac{V_{\mathrm{RC}}}{1+\frac{C_G}{C_C}}$

The coupling capacitance C.sub.C is accordingly chosen to match the negative variations of the cancellation signal voltage with the corresponding supply voltage variations in the intermediate noise frequency range.

[0023] In this fashion, the illustrated regulator directly subtracts the supply voltage noise from the regulated voltage, substantially improving the power supply rejection ratio (PSRR) at intermediate noise frequencies, leading to significantly reduced jitter and reduced bit error rates in SerDes modules using the illustrated voltage regulator. The use of capacitive coupling and inverting buffer greatly reduces complexity, area, and power consumption as compared with the regulator circuit 200 (FIG. 2).

[0024] Numerous alternative forms, equivalents, and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. For example, voltage regulator circuit 300 is implemented using NMOS transistors, but those familiar with the art will recognize how the disclosed principles can be used with other semiconductor technologies including PMOS, CMOS, JFET, and BJT. It is intended that the claims be interpreted to embrace all such alternative forms, equivalents, and modifications that are encompassed in the scope of the appended claims