Decision feedback equalizer

Abstract

An amplifier output from an amplifier to an SR latch is used as a feedback signal through a buffer. An adder having a combination of an addition unit and an xh block is provided within the amplifier and transmits a feedback signal (analog signal) generated from the feedback signal FBD (digital signal) by the xh block to the addition unit and adds it to an output from a latch block. In the amplifier, the operation for adding the output from the latch block and the feedback signal occurs during a latch operation in the latch block.

Claims

1. A decision feedback equalizer that compensates an intersymbol interference caused by a dispersion property of a channel between a transmitter and a receiver, the decision feedback equalizer comprising: an amplifier configured to: receive, as an input signal, an analog signal transmitted from the transmitter to the receiver through the channel and amplify and output the input signal as a return-to-zero digital signal; a first latch circuit configured to latch and output the return-to-zero digital signal as a non-return-to-zero digital signal; and a buffer on a path for feeding back the output from the amplifier to the amplifier, wherein the amplifier includes: a sampling circuit configured to sample and output the input signal at predetermined cycles; a second latch circuit configured to latch and output an output corresponding to the sampling circuit; an adder including: a feedback signal generation circuit configured to generate a feedback signal depending on an amount of the intersymbol interference from an output of the amplifier and feed back the feedback signal through the buffer; and an addition circuit configured to add the feedback signal to the output of the second latch circuit; and a reset circuit configured to control input timing of the output from the sampling circuit to the second latch circuit and control input timing of the output from the second latch circuit to the addition circuit.

2. The decision feedback equalizer according to claim 1, wherein the sampling circuit includes: a first N-channel metal-oxide semiconductor (MOS) transistor having a source connected to a ground line and a gate that receives input of a clock signal; a second N-channel MOS transistor having a source connected to a drain of the first N-channel MOS transistor and a gate that receives input of a first component of the input signal as a differential signal; and a third N-channel MOS transistor having a source connected to the drain of the first N-channel MOS transistor and a gate that receives input of a second component of the input signal input as the differential signal.

3. The decision feedback equalizer according to claim 2, wherein the second latch circuit includes: a first P-channel MOS transistor and a second P-channel MOS transistor each having a source connected to a power supply line; a fourth N-channel MOS transistor having: a drain connected to a drain of the first P-channel MOS transistor; a gate connected to a gate of the first P-channel MOS transistor; and a source connected to a drain of the second N-channel MOS transistor; and a fifth N-channel MOS transistor having: a drain connected to a drain of the second P-channel MOS transistor, the gate of the first P-channel MOS transistor, and the gate of the fourth N-channel MOS transistor; a gate connected to a gate of the second P-channel MOS transistor and the drain of the first P-channel MOS transistor; and a source connected to a drain of the third N-channel MOS transistor.

4. The decision feedback equalizer according to claim 3, wherein the reset circuit includes: a third P-channel MOS transistor having a source connected to the power supply line, a drain connected to the drain of the first P-channel MOS transistor and the drain of the fourth N-channel MOS transistor, and a gate that receives input of a clock signal; a fourth P-channel MOS transistor having a source connected to the power supply line, a drain connected to the source of the fourth N-channel MOS transistor and the drain of the second N-channel MOS transistor, and a gate that receives input of a clock signal; a fifth P-channel MOS transistor having a source connected to the power supply line, a drain connected to the drain of the second P-channel MOS transistor and the drain of the fifth N-channel MOS transistor, and a gate that receives input of a clock signal; and a sixth P-channel MOS transistor having a source connected to the power supply line, a drain connected to the source of the fifth N-channel MOS transistor and the drain of the third N-channel MOS transistor, and a gate that receives input of a clock signal.

5. The decision feedback equalizer according to claim 4, wherein the feedback signal generation circuit includes: a seventh P-channel MOS transistor having a source connected to the power supply line and a gate that receives input of a control voltage; an eighth P-channel MOS transistor having a source connected to a drain of the seventh P-channel MOS transistor, a drain connected to the gate of the first P-channel MOS transistor, the gate of the fourth N-channel MOS transistor, the drain of the second P-channel MOS transistor, and the drain of the fifth N-channel MOS transistor, and a gate that receives a first component of the output from the amplifier fed back as a differential signal through the buffer; and a ninth P-channel MOS transistor having a source connected to the drain of the seventh P-channel MOS transistor, a drain connected to the drain of the first P-channel MOS transistor, the drain of the fourth N-channel MOS transistor, the gate of the second P-channel MOS transistor, and the gate of the fifth N-channel MOS transistor, and a gate that receives input of a second component of the output from the amplifier fed back as the differential signal through the buffer.

6. The decision feedback equalizer according to claim 1, comprising: a plurality of slices, wherein each the plurality of slices includes a combination of the amplifier, the latch circuit, and the buffer; wherein a first feedback signal generation circuit included in a first amplifier in a first slice of the plurality of slices generates a first feedback signal from a final output from a final amplifier in a final slice of the plurality of slices, which is fed back through a final buffer in the final slice; and a respective feedback signal generation circuit within a respective amplifier in each slice of the plurality of slices excluding the first slice generates a respective feedback signal from a respective output from a respective amplifier in a preceding slice, which is fed back through a respective buffer in the preceding slice.

7. A decision feedback equalizer that compensates an intersymbol interference caused by a dispersion property of a channel between a transmitter and a receiver, the decision feedback equalizer comprising: an amplifier configured to: receive, as an input signal, an analog signal transmitted from the transmitter to the receiver through the channel and amplify and output the input signal as a return-to-zero digital signal; a latch circuit configured to latch and output the return-to-zero digital signal as a non-return-to-zero digital signal; and a buffer on a path for feeding back the output from the amplifier to the amplifier, wherein the amplifier includes: a sampling circuit configured to sample and output the input signal at predetermined cycles; a second latch circuit configured to latch and output an output corresponding to the sampling circuit; and an adder including: a feedback signal generation circuit configured to generate a feedback signal depending on an amount of the intersymbol interference from an output of the amplifier and feed back the feedback signal through the buffer; and an addition circuit configured to add the feedback signal to the output of the second latch circuit.

8. The decision feedback equalizer according to claim 7, wherein the amplifier further comprises a reset circuit configured to control input timing of the output from the sampling circuit to the second latch circuit and control input timing of the output from the second latch circuit to the addition circuit.

9. A method for compensating an intersymbol interference caused by a dispersion property of a channel between a transmitter and a receiver, the method comprising: receiving, by an amplifier as an input signal, an analog signal transmitted from the transmitter to the receiver through the channel and amplify and output the input signal as a return-to-zero digital signal; latching and outputting, by a first latch circuit, the return-to-zero digital signal as a non-return-to-zero digital signal, wherein a buffer is provided on a path for feeding back the output from the amplifier to the amplifier; sampling and outputting, by a sampling circuit of the amplifier, the input signal at predetermined cycles; latching and outputting, by a second latch circuit of the amplifier, an output corresponding to the sampling circuit; generating, by the amplifier, a feedback signal depending on an amount of the intersymbol interference from an output of the amplifier and feed back the feedback signal through the buffer; and adding, by the amplifier, the feedback signal to the output of the second latch circuit.

10. The method according to claim 9, wherein the amplifier further comprises a reset circuit configured to control input timing of the output from the sampling circuit to the second latch circuit and control input timing of the output from the second latch circuit to the addition circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a diagram showing a configuration of essential parts of a decision feedback equalizer (DFE) according to Embodiment 1 of the present invention.

(2) FIG. 2 is a diagram showing a specific circuit configuration of an amplifier (adder-contained amplifier) in the DFE shown in FIG. 1.

(3) FIG. 3 is a timing chart showing operations of the DFE using the amplifier shown in FIG. 2.

(4) FIG. 4 is a diagram showing a configuration of essential parts of a DFE having a ¼ rate architecture (DFE according to Embodiment 2).

(5) FIG. 5 is a diagram showing a configuration of essential parts of a conventional DFE.

(6) FIG. 6 is a timing chart showing operations of the DFE shown in FIG. 5.

(7) FIG. 7 is a diagram showing a configuration of essential parts of a conventional DFE using an adder-contained amplifier.

(8) FIG. 8 is a diagram showing a specific circuit configuration of the amplifier in the DFE shown in FIG. 7.

(9) FIG. 9 is a timing chart showing operations of the DFE using the amplifier shown in FIG. 8.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

Embodiment 1

(10) With reference to drawings, embodiments of the present invention will be described in detail below. FIG. 1 is a diagram showing essential parts of a decision feedback equalizer (DFE) 100 according to Embodiment 1 of the present invention. In FIG. 1, the same reference signs are given to the same constituent elements as the constituent elements described with reference to FIG. 7, and the description will be omitted.

(11) In the DFE 100, in order to further reduce the feedback loop delay TFB, the amplifier output SAO is used as the feedback signal FBD through the buffer 3, and an amplifier (adder-contained amplifier (SE_SA)) having an adder 1C between the latch block 21-2 and the SR latch 22 is used.

(12) In other words, in the DFE 100, the adder 1C having a combination of an addition unit 21-5′ and an xh block 21-7 is provided within an amplifier 21C, and the xh block 21-7 transmits a feedback signal FB (analog signal) generated from a feedback signal FBD (digital signal) to the addition unit 21-5′.

(13) In the DFE 100, a reset block 21-3 is controlled by a clock signal CK and resets output nodes of the sampling block 21-1 and the latch block 21-2. In this case, while the clock signal CK is having “Low”, the output node of the sampling block 21-1 and the output node of the latch block 21-2 are pre-charged to VDD by the reset block 21-3. While the clock signal CK is having “High”, the pre-charging to VDD of the output node of the sampling block 21-1 and the output node of the latch block 21-2 is cancelled, and the output from the sampling block 21-1 is transmitted to the latch block 21-2, and the output from the latch block 21-2 is transmitted to the addition unit 21-5′. In other words, the reset block 21-3 controls input timing of the output from the sampling block 21-1 to the latch block 21-2 and input timing of the output from the latch block 21-2 to the addition unit 21-5′. The purpose of the reset block 21-3 is pre-charging for a sampling operation or a latch operation to be performed next, and the timing is determined by the clock signal CK.

(14) In the DFE 100, an operation for adding the output from the latch block 21-2 and the feedback signal FB from the xh block 21-7 occurs during the latch operation in the latch block 21-2.

(15) Thus, compared with the conventional DFE 201 shown in FIG. 7, the delay time TSAM is removed, and the feedback loop delay TFB is reduced to TLA+TBUF. As a result, the operational data rate of the receiver can further be increased, and the intersymbol interference of a high speed signal can be compensated.

(16) The amplifier 21C in the DFE 100 will be described with reference to a specific circuit configuration thereof. Here, a specific circuit configuration of the amplifier 21B in the conventional DFE 201 shown in FIG. 7 will be described first, and the specific circuit configuration of the amplifier 21C in the DFE 100 of this embodiment will then be described.

(17) FIG. 8 shows a specific circuit configuration of the amplifier 21B in the conventional DFE 201. This circuit is shown as a circuit in a case where the amplifier 21B is differential.

(18) In the circuit configuration, IN+ is one component of an input signal IN input as a differential signal, and IN− is the other component. S1+ is one component of the latch block input S1 occurring as a differential signal, and S1− is the other component. FBD+ is one component of the feedback signal FBD transmitted as a differential signal, and FBD− is the other component. SAO+ is one component of the amplifier output SAO output as a differential signal, and SAO− is the other component.

(19) In the amplifier 21B, the sampling block 21-1 includes an N-channel MOS transistor Mn1, an N-channel MOS transistor Mn2, and an N-channel MOS transistor Mn3. Here, the N-channel MOS transistor Mn1 has a source connected to a ground line and a gate that receives input of a clock signal CK. The N-channel MOS transistor Mn2 has a source connected to a drain of the N-channel MOS transistor Mn1 and a gate that receives input of the input signal IN+. The N-channel MOS transistor Mn3 has a source connected to the drain of the N-channel MOS transistor Mn1 and a gate that receives input of the input signal IN−.

(20) The latch block 21-2 includes a P-channel MOS transistor Mp1, a P-channel MOS transistor Mp2, an N-channel MOS transistor Mn4, and an N-channel MOS transistor Mn5. Here, the P-channel MOS transistor Mp1 and the P-channel MOS transistor Mp2 have sources connected to a power supply line. The N-channel MOS transistor Mn4 has a drain connected to a drain of the P-channel MOS transistor Mp1, a gate connected to a gate of the P-channel MOS transistor Mp1, and a source connected to a drain of the N-channel MOS transistor Mn2. A drain, a gate and a source of the N-channel MOS transistor Mn5 are connected in the way described below. The drain of the N-channel MOS transistor Mn5 is connected to the drain of the P-channel MOS transistor Mp2 and a connection point between the gate of the P-channel MOS transistor Mp1 and the gate of the N-channel MOS transistor Mn4. The gate of the N-channel MOS transistor Mn5 is connected to a gate of the P-channel MOS transistor Mp2 and a connection point between the drain of the P-channel MOS transistor Mp1 and the drain of the N-channel MOS transistor Mn4. The source of the N-channel MOS transistor Mn5 is connected to a drain of the N-channel MOS transistor Mn3.

(21) The reset block 21-3 includes a P-channel MOS transistor Mp3, a P-channel MOS transistor Mp4, a P-channel MOS transistor Mpg, and a P-channel MOS transistor Mph. Here, the P-channel MOS transistor Mp3 has a source connected to the power supply line, a drain connected to a connection point between the drain of the P-channel MOS transistor Mp1 and the drain of the N-channel MOS transistor Mn4, and a gate that receives input of a clock signal CK. The P-channel MOS transistor Mp4 has a source connected to the power supply line, a drain connected to a connection point between the source of the N-channel MOS transistor Mn4 and a drain of the N-channel MOS transistor Mn2, and a gate that receives input of a clock signal CK. The P-channel MOS transistor Mpg has a source connected to the power supply line, a drain connected to a connection point between the drain of the P-channel MOS transistor Mp2 and the drain of the N-channel MOS transistor Mn5, and a gate that receives input of a clock signal CK. The P-channel MOS transistor Mp6 has a source connected to the power supply line, a drain connected to a connection point between the source of the N-channel MOS transistor Mn5 and the drain of the N-channel MOS transistor Mn3, and a gate that receives input of a clock signal CK.

(22) The xh block 21-6 includes an N-channel MOS transistor Mn6, an N-channel MOS transistor Mn7, and an N-channel MOS transistor Mn8. Here, the N-channel MOS transistor Mn6 has a source connected to the ground line and a gate that receives input of the clock signals CK. The N-channel MOS transistor Mn7 has a source connected to a drain of the N-channel MOS transistor Mn6, a drain connected to a connection point between the source of the N-channel MOS transistor Mn5 and the drain of the P-channel MOS transistor Mp6, and a gate that receives input of the feedback signal FBD+. The N-channel MOS transistor Mn8 has a source connected to the drain of the N-channel MOS transistor Mn6, a drain connected to a connection point between the drain of the P-channel MOS transistor Mp4 and the source of the N-channel MOS transistor Mn4, and a gate that receives input of the feedback signal FBD−.

(23) FIG. 9 shows a timing chart indicating operations of the DFE 201 including the amplifier 21B shown in FIG. 8. In the DFE 201 including the amplifier 21B, when the clock signal CK has “Low”, the nodes of S1+, S1−, SAO+ and SAO− are charged to VDD by the reset block 21-3. When the clock signal CK is shifted to “High”, the sampling block 21-1 and the xh block 21-6 start pulling current from the two nodes of S1+ and S1−.

(24) At the two nodes of S1+ and S1−, the current by the sampling block 21-1 is added to the current by the xh block 21-6. The added current is transmitted to the two nodes of SAO+ and SAO−. As a result, in a sampling operation, SAO− depends on the current by IN+, and FBD− and SAO+ depend on current by IN− and FBD+.

(25) After the sampling operation, VDI that is “SAO.sup.+−SAO.sup.−” is α*{(IN.sup.+−IN.sup.−)−h*(FBD.sup.+−FBD.sup.−)}. Here, α is a gain of the sampling operation, and h is an intersymbol interference coefficient depending on the ratio between the current flowing in the N-channel MOS transistor Mn1 and the current flowing in the N-channel MOS transistor Mn6. Because FBD+ and FBD.sup.− are digital signals of “1” or “0”, VDI is α*{(IN.sup.+−IN.sup.−)±h}. However, this is the same result as that of a case where the DFE 201 shown in FIG. 7 has a single-end architecture.

(26) When SAO.sup.+ or SAO.sup.− is lower than “VDD−V.sub.TH”, the P-channel MOS transistors Mp1 and Mp2 are turned on, and the latch block 21-2 starts a latch operation. V.sub.TH is a threshold voltage of the P-channel MOS transistors Mp1 and Mp2. After the latch operation, one of SAO+ and SAO is shifted to have V.sub.DD, and the other one is shifted to have V.sub.SS.

(27) In the DFE 201 including the differential amplifier 21B, in order to properly remove the intersymbol interference, FBD.sup.+ and FBD.sup.− of the (n−1)th data are required to arrive before the n-th sampling of the clock signal CK. Therefore, the feedback loop delay T.sub.FB (T.sub.FB=T.sub.SAM+T.sub.LA+T.sub.BUF) is required to be smaller than 1 UI.

(28) FIG. 2 shows a specific circuit configuration of the amplifier 21C in the DFE too (FIG. 1) of this embodiment. This circuit is also shown as a circuit in a case where the amplifier 21C is differential. FIG. 3 shows a timing chart corresponding to FIG. 9.

(29) In this circuit, instead of the xh block 21-6 in the conventional amplifier 21B shown in FIG. 8, an xh block 21-7 using P-channel MOS transistors Mp7 to Mp9 is used.

(30) Because configurations of a sampling block 21-1, a latch block 21-2 and a reset block 21-3 in this circuit are the same as the configurations of the sampling block 21-1, the latch block 21-2 and the reset block 21-3 in the amplifier 21B shown in FIG. 8, the description will be omitted.

(31) In the amplifier 21C, the xh block 21-7 includes a P-channel MOS transistor Mp7, a P-channel MOS transistor Mp8, and a P-channel MOS transistor Mp9. Here, the P-channel MOS transistor Mp7 has a source connected to a power supply line and a gate that receives input of a control voltage VB. A drain, a gate and a source of the P-channel MOS transistor Mp8 are connected in the way described below. The source of the P-channel MOS transistor Mp8 is connected to a drain of the P-channel MOS transistor Mp7. The drain of the P-channel MOS transistor Mp8 is connected to a connection point between the gate of the P-channel MOS transistor Mp1 and the gate of the N-channel MOS transistor Mn4 and a connection point between the drain of the P-channel MOS transistor Mp2 and the drain of the N-channel MOS transistor Mn5. The gate of the P-channel MOS transistor Mp8 receives input of the feedback signal FBD+. A drain, a gate and a source of the P-channel MOS transistor Mp9 are connected in the way described below. The source of the P-channel MOS transistor Mp9 is connected to the drain of the P-channel MOS transistor Mp7. The drain of the P-channel MOS transistor Mp9 is connected to a connection point between the drain of the P-channel MOS transistor Mp1 and the drain of the N-channel MOS transistor Mn4 and a connection point between the gate of the P-channel MOS transistor Mp2 and the gate of the N-channel MOS transistor Mn5. The gate of the P-channel MOS transistor Mp9 receives input of the feedback signal FB.sup.−.

(32) In the amplifier 21C, an offset voltage of −α*h*(FBD.sup.+−FBD.sup.−) is added to the output from the latch block 21-2 by the xh block 21-7. Because of this addition of the offset voltage, VDI is α*(IN.sup.+−IN.sup.−)−α*h*(FBD.sup.+−FBD.sup.−). This exhibits the same result as that of the amplifier 21B shown in FIG. 8. α*h is controlled by a control voltage VB.

(33) In the amplifier 21C, because the offset voltage is added to the output from the latch block 21-2, the arrival time of the feedback signal (FBD.sup.+, FBD.sup.−) is alleviated to the starting time of a latch operation. In other words, in order to properly remove the intersymbol interference, FBD.sup.+ and FBD.sup.− of the (n−1)th data are required to arrive before the latch operation of the n-th data.

(34) Because the feedback loop includes a latch operation in the amplifier 21C and a buffer operation in the buffer 3, the feedback loop delay T.sub.FB is T.sub.LA+T.sub.BUF. In this amplifier 21C, T.sub.FB is smaller than that of the conventional amplifier 21B, providing an effect that the operational data rate of the DFE 100 is further increased.

Embodiment 2

(35) The DFE 100 shown in FIG. 1 can be implemented as a ¼ rate architecture. FIG. 4 shows a configuration of essential parts of a DFE 101 having a ¼ rate architecture. The DFE 101 includes four slices SL1 to SL4 where one slice includes a combination of the amplifier 21C, the SR latch 22 and the buffer 3 shown in FIG. 1.

(36) The first slice SL1 includes an amplifier 21C.sub.1, an SR latch 22.sub.1, and a buffer 3.sub.1. The second slice SL2 includes an amplifier 21C.sub.2, an SR latch 22.sub.2, and a buffer 3.sub.2. The third slice SL3 includes an amplifier 21C.sub.3, an SR latch 22.sub.3, and a buffer 3.sub.3. The fourth slice SL4 includes an amplifier 21C.sub.4, an SR latch 22.sub.4, and a buffer 3.sub.4.

(37) In the DFE 101, the xh block 21-7 within the amplifier 21C.sub.1 in the first slice SL1 generates a feedback signal FB from an output from the amplifier 21C.sub.4 in the final (fourth) slice SL4, which is fed back through the buffer 3.sub.4 in the final (fourth) slice SL4, instead of an output from the amplifier 21C.sub.1, which is fed back through the buffer 3.sub.1 in the first slice SL1.

(38) The amplifier 21C.sub.2 in the second slice SL2 generates a feedback signal FB from an output from the amplifier 21C.sub.1 in the preceding slice SL1, which is fed back through the buffer 3.sub.1 in the preceding slice SL1, instead of an output from the amplifier 21C.sub.2 in the second slice SL2, which is fed back through the buffer 3.sub.2 in the second slice SL2.

(39) The amplifier 21C.sub.3 in the third slice SL3 generates a feedback signal FB from an output from the amplifier 21C.sub.2 in the preceding slice SL2, which is fed back through the buffer 3.sub.2 in the preceding slice SL2, instead of an output from the amplifier 21C.sub.3 in the third slice SL3, which is fed back through the buffer 3.sub.3 in the third slice SL3.

(40) The amplifier 21C.sub.4 in the fourth slice SL4 generates a feedback signal FB from an output from the amplifier 21C.sub.3 in the preceding slice SL3, which is fed back through the buffer 3.sub.3 in the preceding slice SL3, instead of an output from the amplifier 21C.sub.4 in the fourth slice SL4, which is fed back through the buffer 3.sub.4 in the fourth slice SL4.

(41) In this DFE 101, the amplifiers 21C.sub.1, 21C.sub.2, 21C.sub.3 and 21C.sub.4 are synchronized by a clock signal CK0, a clock signal CK90, a clock signal CK180 and a clock signal CK270, respectively. In this example, it is assumed that the amplifiers 21C.sub.1, 21C.sub.2, 21C.sub.3 and 21C.sub.4 have the circuit configuration shown in FIG. 2.

(42) The clock signals CK0, CK90, CK180 and CK270 have a cycle of 4×UI where UI is the same as the RX input. Sampling operations are sequentially performed in the amplifiers 21C.sub.1, 21C.sub.2, 21C.sub.3 and 21C.sub.4 in order of the clock signal CK0, the clock signal CK90, the clock signal CK180, and the clock signal CK270. The amplifier 21C.sub.2 starts a sampling operation by using the clock signal CK90 after one UI from the sampling by the clock signal CK0 in the amplifier 21C.sub.1.

(43) After the next one UI, the amplifier 21C.sub.3 starts a sampling operation by using the clock signal CK180. After the further next one UI, the amplifier 21C.sub.4 starts a sampling operation. Then, after the further next one UI, the amplifier 21C.sub.1 starts a sampling operation again. The sampling operations are repeated in the order described above.

(44) For a DFE operation, an amplifier output SAO0 that is an output from the amplifier 21C.sub.1 synchronized by the clock signal CK0 is transmitted to the amplifier 21C.sub.2 as FBD0 through the buffer 3.sub.1. An amplifier output SAO90 that is an output from the amplifier 21C.sub.2 synchronized by the clock signal CK90 is transmitted to the amplifier 21C.sub.3 as FBD90 through the buffer 3.sub.2. An amplifier output SAO180 that is an output from the amplifier 21C.sub.3 synchronized by the clock signal CK180 is transmitted to the amplifier 21C.sub.4 as FBD180 through the buffer 3.sub.3. An amplifier output SAO270 that is an output from the amplifier 21C.sub.4 synchronized by the clock signal CK270 is transmitted to the amplifier 21C.sub.1 as FBD270 through the buffer 3.sub.4.

Expansion of the Embodiments

(45) Having described the present invention with reference to the embodiments, the present invention is not limited to the embodiments. Various changes that can be understood by those skilled in the art without departing from the technical spirit of the present invention can be made to the configuration and details of the present invention.

REFERENCE SIGNS LIST

(46) 1C Adder 2C Flip-flop 3, 31 to 34 Buffer 21C, 21C1 to 21C4 Amplifier (adder-contained amplifier) 21-1 Sampling block 21-2 Latch block 21-3 Reset block 21-4 Addition unit 21-5′ Addition unit 21-7 xh block 22, 221 to 224 SR latch Mp1 to Mp9 P-channel MOS transistor Mn1 to Mn5 N-channel MOS transistor SL1 to SL4 Slice 100, 101 DFE 22, 221 to 224 SR latch Mp1 to Mp9 P-channel MOS transistor Mn1 to Mn5 N-channel MOS transistor SL1 to SL4 Slice 100, 101 DFE.