Heterogeneous structures comprising III-V semiconductors and metal oxide dielectrics, and a method of fabrication thereof
11735643 · 2023-08-22
Assignee
Inventors
Cpc classification
H01L29/66462
ELECTRICITY
H01L29/7786
ELECTRICITY
H01L23/3171
ELECTRICITY
H01L21/02172
ELECTRICITY
International classification
H01L29/12
ELECTRICITY
H01L29/66
ELECTRICITY
Abstract
Systems and methods for passivation of III-V semiconductors to create heterogeneous structures based on such semiconductors, to the structures themselves, and to devices using passivated III-V semiconductors, such as metal oxide-semiconductor field effect transistors (MOSFET) and Hall effect sensors using III-V semiconductors.
Claims
1. A heterogeneous structure comprising: a semiconductor and a layer of a dielectric grown on a surface of the semiconductor, the structure having an interface between the dielectric and the semiconductor, wherein the semiconductor is passivated while depositing the dielectric on the surface of the semiconductor, wherein the semiconductor is passivated via RF sputtering in presence of oxygen, thereby obtaining a high mobility interface between the semiconductor and the dielectric, wherein said interface is formed between the semiconductor GaAs and the dielectric MgO, the interface having the charge mobility in a range from about 1000 to more than 3000 cm.sup.2/Vs.
2. The structure of claim 1, wherein the structure has a charge mobility μ being close to or higher than the charge mobility of the bulk semiconductor.
3. The structure of claim 1, wherein the dielectric comprises one or more metal oxides.
4. The structure of claim 3, wherein the dielectric comprises one or more metal oxides selected from a group comprising MgO, SiO.sub.2, HfO.sub.2 ZnO, Al.sub.2O.sub.3.
5. The structure of claim 1, in which the charge mobility of said interface is greater than or equal to 10.sup.3 cm.sup.2/Vsec at room temperature.
6. The structure of claim 1, wherein the semiconductor is selected from a group consisting of a semi-insulating, non-doped semiconductor, an n-type semiconductor or a p-type doped semiconductor.
7. A semiconductor device incorporating the structure of claim 1, wherein the device is a MOSFET or a Hall effect sensor.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) The invention will be further described and illustrated with reference to the embodiments and features presented in the following non-limiting drawings, in which:
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DETAILED DESCRIPTION OF THE INVENTION
(10) In the following description, numerous details are set forth for the purpose of explanation. However, one of ordinary skill in the art will realize that the invention may be practiced without the use of these specific details.
(11) An object of the invention is directed to providing a technique of fabrication heterogeneous structures comprising III-V semiconductors and metal oxide dielectrics, with free of pinning high mobility interfaces there-between.
(12) The heterogeneous structures are produced by a direct RF sputtering of the metal oxide material on the III-V semiconductor surface in the atmosphere containing argon and oxygen.
(13) The Inventors suggest an original, alternative approach to fabrication the high mobility interface between GaAs and metal oxide dielectrics, which is the most important and demanded combination for the modern semiconductor industry. Exposure of the untreated semi-insulating GaAs wafers to the Ar/02 plasma during reactive RF sputtering of metal oxides leads to formation of the n-type conducting interfacial channel. Resistance of samples fabricated in the Ar/02 atmosphere can be as low as 10.sup.5Ω/down from 10.sup.10Ω/ of those sputtered without oxygen. The n-type conductance channel is with the surface charge density of 10.sup.7 to 10.sup.10 cm.sup.−2, depending on RF plasma excitation power and oxygen content during the deposition. Room temperature Hall mobility is up to 6000 cm.sup.2/Vsec, which implies the self-cleaning of the GaAs surface from the native oxide defects and formation of the pinning-free interface. The conducting channel is formed during deposition of any of the tested metal oxide dielectrics: MgO, SiO.sub.2, Al.sub.2O.sub.3 and HfO.sub.2, of ZnO, or of any combination thereof.
Experimental Data
(14) Metal oxide dielectrics: MgO, SiO.sub.2, Al.sub.2O.sub.3 and HfO.sub.2 were RF sputtered on 5 mm×5 mm slices of commercial SI—GaAs [001] wafers at room temperature. 500 μm thick compensated wafers, usually used as insulating substrates for film deposition, were supplied by different producers, including CMK and XTAL. Their room temperature resistance in dark was immeasurable (higher than 20 GO, which is the highest resistance value we were able to measure) but decreased to 10.sup.9-10.sup.10Ω in the ambient laboratory illumination due to the light induced excitations. No chemical or thermal treatment of the wafers was done prior to deposition. The depositions were performed at 4 to 5 mtorr of argon with the added flow of air or 99.999% oxygen. The base chamber pressure prior to deposition was about 1×10.sup.−7 torr.
(15) Hygroscopic targets, such as MgO, exposed to the ambient atmosphere were cleaned by pre-sputtering for 20 minutes at 5 W/cm.sup.2 rf power to remove the surface contaminated layer. The rf power density delivered to the targets varied between 2.5 W/cm.sup.2 and 12 W/cm.sup.2. Only a limited number of samples were fabricated at 12 W/cm.sup.2 due to an excessive heat load. The deposition rate varied between 0.1 nm/sec to 0.3 nm/sec, subject to the applied power, target material and oxygen content in the chamber. Most of the samples were deposited in the home-made RF sputtering system using 2 inch targets (ACI alloys Inc.) located 20 cm from the substrate. A number of control samples were deposited in the commercial Vinci Technologies magnetron sputtering installation. All samples fabricated in both systems demonstrated similar properties. Two types of electric contacts were used: (i) NiGeAu alloyed Ohmic contacts grown on GaAs substrate prior to depositing the metal oxides films; (ii) alternatively, Al/Si wires were bonded to the film surface after the deposition. Both types of contacts revealed the same results. Resistance and Hall effect measurements were done using the Van der Paw four contacts protocol. Four probe and two-probe measurements using the Keithley electrometer were used for the high resistance samples in the G range. The results of the two probe measurements were consistent with the four probe ones. Structural analyzes were done by X-ray diffraction, high-resolution transmission electron microscopy, cross-sectional TEM, TOF-SIMS and XPS.
RESULTS AND DISCUSSION
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(17) Resistance of the conducting interface depends on the deposition conditions including the oxygen concentration, RF power and the substrate used, but also on illumination and time elapsed after the fabrication.
(18) The density of the charge carriers and their mobility were extracted from the Hall effect measurements.
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Linearity of the Hall resistance indicates the dominance of a single negative charge carrier.
(20) The planar charge carrier density n and Hall mobility μ were calculated from the resistance and Hall coefficient as:
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Where R.sub.□ is the planar resistance (per square).
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(24) Formation of the conductance channel during the reactive sputtering of dielectrics on GaAs is a general property.
(25) Transformation of the GaAs interface occurs gradually during the sputtering process.
(26) The plasma excitation power is important in defining the properties of the conducting channel, as illustrated in
(27) The results presented here are quite surprising after so many dedicated efforts to fabricate the defect-free interface between GaAs and metal-oxides. A number of characterization tools were employed in attempt to reveal the compositional or structural uniqueness of GaAs(O)/MgO samples. The cross-sectional high resolution TEM, XPS and TOF-SIMS tests did not reveal a measurable difference between samples sputtered with and without oxygen, although their conductance properties differed by orders of magnitude. The cross-section TEM analysis of one of the samples indicated the formation of Ga.sub.2O.sub.3 interface layer between GaAs and SiO.sub.2 overlayer, however this observation was not confirmed in other samples. One can speculate that reactive sputtering leads to redistribution of the surface oxides favoring the more stable Ga.sub.2O.sub.3 that makes the pinning free interface with GaAs when deposited in situ. Similar to the atomic layer deposition, the process of self cleaning occurs at the very early stages of the reactive sputtering exposure, and the process is terminated when the layer of the metal oxide covers GaAs. Exposure to the Ar/O.sub.2 plasma is a standard procedure used to clean the GaAs surfaces. However, such a process alone without passivation, performed using the Plasma Asher system, did not improve either conductance or mobility. Therefore, the very presence of the metal oxide layer formed simultaneously with exposure of the surface to reactive plasma seems to protect and conserve the high mobility properties of the interfacial channel.
CONCLUSIONS
(28) To summarize, the semi-insulating GaAs used as a substrate for film deposition, becomes conducting during the reactive sputtering of insulating metal oxide dielectrics in Ar/02 plasma. The conducting interfacial channel generated during the process is n-type with the surface charge density of 10.sup.7 to 11.sup.10 cm.sup.−2, depending on RF plasma excitation power and oxygen content during the deposition. Room temperature Hall mobility is up to 6000 cm.sup.2/Vsec, the value approaching the room temperature mobility of clean GaAs crystals. The conducting channel is formed during deposition of any of the tested metal oxide dielectrics: MgO, SiO.sub.2, Al.sub.2O.sub.3 and HfO.sub.2. Other metal oxide dielectrics (for example, ZnO) are believed to demonstrate the same effect. Such dramatic enhancement of the charge carrier density and improvement of mobility imply the self-cleaning of GaAs surface from the native oxide defects and formation of the pinning-free interface.
(29) The Inventors have proposed at least 3 implementations/devices which are characterized by the dramatically high charge density and improved mobility, and which may be manufactured by the suggested method: 1. MOSFET (metal oxide semiconductor field effect transistor) in which the insulating dielectric is deposited on III-V semiconductor. 2. Hall Effect device with low carrier density and high carrier mobility (the device that used to measure the magnitude of a magnetic field). 3. Device containing III-V semiconductor-metal oxide insulator element, in which the charge carrier density is modulated either by a wide spectrum light or by illumination in the selected frequency range. Results obtained in the samples fabricated by the proposed method are superior to the previously known
(30) Having thus described several embodiments for practicing the inventive method, its advantages and objectives can be easily understood. Variations from the description above may and can be made by one skilled in the art without departing from the scope of the invention.
(31) Accordingly, this invention is not to be limited by the embodiments as described, which are given by way of example only and not by way of limitation.
REFERENCES
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