METHOD FOR FORMING A USEFUL SUBSTRATE TRAPPING STRUCTURE

Abstract

The invention relates to a method of forming a trapping structure of a useful substrate designed to trap charges and limit at least one of crosstalk, radio frequency losses, and distortions of a device that may be formed on or in the useful substrate. Formation of the trapping structure includes forming a first layer that includes amorphous silicon carbide and forming a second layer covering the first layer that comprises an insulating or semiconductor material in an amorphous state and having a crystallisation temperature lower than that of the amorphous silicon carbide.

Claims

1. A method for the formation of a useful substrate comprising a trapping structure, the trapping structure being designed to at least one of trap charges and limit at least one of crosstalk, radio frequency losses and distortion of a device formed on or in the useful substrate, comprising: a) supplying a support substrate; b) forming a first layer comprising amorphous silicon carbide on the support substrate; c) forming a second layer covering the first layer, the second layer comprising an insulating or semiconductor material in an amorphous state and having a crystallisation temperature lower than that of the amorphous silicon carbide; and d) conducting a heat treatment to degas the first layer and the second layer and to crystallise the second layer and the first layer.

2. The method for the formation of a useful substrate according to claim 1, wherein the amorphous silicon carbide forming the first layer has a carbon content of less than 50%.

3. The method for the formation of a useful substrate according to claim 1, wherein the amorphous silicon carbide forming the first layer has a carbon content of between 30% and 50%.

4. The method for the formation of a useful substrate according to claim 1, comprising performing step b) in a chemical vapour phase deposition chamber.

5. The method for the formation of a useful substrate according to claim 1, comprising performing step b) in a plasma enhanced chemical vapour phase deposition chamber.

6. The method for the formation of a useful substrate according to claim 1, the method also comprising of forming an insulating layer and a semiconductor layer, in order and covering the trapping structure.

7. The method for the formation of a useful substrate according to claim 6, wherein forming the insulating layer and the semiconductor layer includes transferring the insulating layer and the semiconductor layer from a donor substrate onto the second layer.

8. The method for the formation of a useful substrate according to claim 7, wherein transferring includes: 1) supplying the donor substrate; 2) forming the insulating layer on one face of the donor substrate; 3) forming an embrittlement zone in the donor substrate that, with the insulating layer, delimits the semiconductor layer; 4) assembling the insulating layer on the second layer and 5) fracturing the donor substrate in the embrittlement zone to transfer the insulating layer and the semiconductor layer onto the second layer.

9. The method for the formation of a useful substrate according to claim 1, comprising forming the trapping structure in at least one isolation trench, being covered by an insulating material filling this trench.

10. The method for the formation of a useful substrate according to claim 9, comprising forming the trapping structure is formed directly in contact with the substrate and defines a bottom of the at least one isolation trench.

11. The method for the formation of a useful substrate according to claim 1, wherein during forming the second layer covering the first layer, the second material of the second layer is an amorphous semiconductor, said layer having a first region and a second region distinguished from each other by a different concentration of dopant elements of said second material.

12. The method for the formation of a useful substrate according to claim 11, wherein the first region has a concentration of dopant elements of an unintentionally doped type.

13. The method for the formation of a useful substrate according to claim 11, wherein the first region of the second layer with a corresponding region of the first layer forms a trapping substructure, and the second region of the second layer with a corresponding region of the first layer forms a second trapping substructure, the method further comprising forming at least one isolation trench filled with an insulating material to separate the first trapping substructure from the second trapping substructure.

14. The method for the formation of a useful substrate according to claim 11, further comprising the following sub-steps: removing the first layer and the second layer on a part of the support substrate; and forming a semiconductor layer at least partially covering the part of the support substrate from which the first layer and the second layer have been removed.

15. The method for the formation of a useful substrate according to claim 1, wherein the material forming the second layer includes at least one material chosen from among HfO.sub.2, Al.sub.2O.sub.3, and Si.sub.1-xGe.sub.x in which x is less than 0.25.

16. The method for the formation of a useful substrate according to claim 1, wherein at least one of the first layer has a thickness of between 10 nm and 50 nm and the second layer has a thickness of between 5 nm and 150 nm.

17. A useful substrate having a trapping structure for at least one of trapping charges and limiting at least one of crosstalk, radio frequency losses and distortion of a device configured to be formed on or in the trapping structure, comprising: a support substrate provided with a front face; a trapping structure covering the front face; an insulating layer covering the trapping structure; and a semiconductor layer covering the insulating layer; wherein the trapping structure comprises: a first layer comprising polycrystalline silicon carbide; and a second layer covering the first layer, that comprises an insulating or semiconductor material in a polycrystalline state, said material having a crystallisation temperature lower than that of amorphous silicon carbide when in an amorphous state.

18. The substrate according to claim 17, wherein a device is formed on or in a trap-rich layer of the trapping structure.

19. The substrate according to claim 18, wherein the device is a radio frequency device.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Other characteristics and advantages will become clear in the following description of a method for a trapping structure according to the invention, given as non-imitative examples, with reference to the appended drawings in which:

[0060] FIG. 1 is a diagrammatic representation of an SOI substrate known in prior art and without a trap-rich layer, in particular the SOI substrate is represented on a section plane perpendicular to a principal face of said SOI substrate;

[0061] FIG. 2 is a diagrammatic representation of an RF SOI substrate known in prior art and provided with a trap-rich layer intercalated between the insulation layer and the support substrate, in particular the RF SOI substrate is shown in a section plane perpendicular to a principal face of said SOI substrate;

[0062] FIG. 3 is a representation of a useful substrate according to this invention, in particular the useful substrate is represented in a section plane perpendicular to the front face of the support substrate;

[0063] FIG. 4 is a diagrammatic representation of steps a) and b) for forming a first layer on a front face of a support substrate according to this invention, in particular the support substrate is represented in a section plane perpendicular to a front face of the support substrate;

[0064] FIG. 5 is a diagrammatic representation of a step c) to form a second layer covering the first layer according to this invention, in particular the support substrate is represented in a section plane perpendicular to a front face of the support substrate;

[0065] FIG. 6 is a diagrammatic representation of a step 2) forming an insulating layer on a principal face of a donor substrate according to this invention, in particular the donor substrate is represented in a section plane perpendicular to a principal face of the support substrate;

[0066] FIG. 7 is a diagrammatic representation of a step 3) forming an embrittlement zone, in particular by implantation of species in the donor substrate in order to delimit the semiconductor layer in said donor substrate according to this invention, in particular the donor substrate is represented in a section plane perpendicular to a principal face of the donor substrate;

[0067] FIG. 8 is a diagrammatic representation of an assembly step 4) according to this invention, in particular the donor substrate is represented in a section plane perpendicular to a principal face of the donor substrate;

[0068] FIG. 9 is a diagrammatic representation of a fracture step 5) according to this invention, in particular the support substrate is represented in a section plane perpendicular to a front face of the support substrate;

[0069] FIG. 10 is a diagrammatic representation of a useful substrate used for hybridisation, in particular including the formation of zones A of HR SOI, and zones B of solid silicon;

[0070] FIG. 11 is a representation of a second example embodiment for forming the trapping structure according to this invention;

[0071] FIG. 12 is a representation of a third example embodiment for forming the trapping structure according to this invention,

[0072] FIG. 13 is a representation of a fourth example embodiment for forming the trapping structure according to this invention,

DETAILED PRESENTATION OF PARTICULAR EMBODIMENTS

[0073] This invention relates to a method of forming a useful substrate trapping structure, and designed to trap charges, and/or limit crosstalk and/or radio frequency losses of a device that may be formed on or in the useful substrate,

[0074] The formation of the trapping structure can include the following operations in particular:

[0075] a) supply the useful substrate,

[0076] b) a step to form a first layer comprising amorphous silicon carbide on the useful substrate;

[0077] c) a step to form a second layer covering the first layer, that comprises an insulating or semiconductor material in an amorphous state and having a crystallisation temperature lower than that of the amorphous silicon carbide.

[0078] According to one possibility, not included in the invention, the insulating or semiconductor material may be in a polycrystalline state during the second layer formation stage.

[0079] In particular, the method according to this invention relates to the problem of forming a trapping structure that retains its trapping properties when subjected to significant heat treatments, and in particular that can be performed at temperatures of the order of 1000° C. or even 1100° C.

[0080] This trapping structure can advantageously be used in the framework of the formation of a useful substrate of the semiconductor on insulator type, for example for radio frequency applications (hereinafter “RF”). In this case, the useful substrate comprises a support substrate on one face of which, called the front face, a stack of layers is formed, on which there are the trapping structure, an insulating layer and a semiconductor layer, starting from the front face.

[0081] FIGS. 3 to 9 show a first example embodiment of the method of forming the trapping structure for the manufacture of a useful substrate 10 of the semiconductor on insulator type according to the invention.

[0082] In particular, as illustrated on FIG. 3, the useful substrate 10 comprises a support substrate 20 on one face of which, called the front face 21, a stack 11 of layers is formed, on which there are a trapping structure 30, an insulating layer 40 and a semiconductor layer 50, starting from the front face 21.

[0083] The trapping structure 30 comprises in particular, starting from the front face 21, a first layer 31 and a second layer 32 covering the first layer 31.

[0084] As shown in FIG. 4, the method comprises in particular a step a) for the supply of a support substrate 20.

[0085] For example, the support substrate 20 may comprise silicon, and more specifically high resistivity silicon that has a resistivity of more than 1 kOhm.cm.

[0086] However, the invention is not limited to the use of silicon alone, and a person skilled in the art may use his or her general knowledge and the following description, to consider any other type of material. For example, the substrate 20 may comprise at least materials chosen from among glass, quartz, a ceramic.

[0087] The method also includes a step b) to form a first layer 31 on a front face 21 of a support substrate 20 (FIG. 4).

[0088] The formation of the first layer 31 may be preceded by a step to clean the front face 21 before removing all traces of contaminant.

[0089] Moreover, the first layer 31 according to this invention comprises silicon carbide, advantageously with an atomic carbon content of less than 50% (it is understood that the atomic carbon content is strictly greater than 0%), advantageously between 30% and 50%.

[0090] The formation of this first layer 31 may involve a chemical vapour phase deposition, and in particular a plasma enhanced chemical vapour phase deposition. The deposition temperature can be between 320° C. and 480° C., for example 350° C.

[0091] Furthermore, the first layer 31 may be between 5 nm and 50 nm thick.

[0092] Step b) is followed by step c) to form a second layer 32 covering the first layer 31 (illustrated in FIG. 5).

[0093] This second layer 32 comprises in particular an insulating or semiconductor material in an amorphous state having a crystallisation temperature lower than that of the amorphous silicon carbide. For example, the material forming the second layer 32 may comprise at least one material chosen from among: HfO.sub.2, Al.sub.2O.sub.3, Si.sub.1-x,Ge.sub.x in which x is less than 0.25, or amorphous silicon.

[0094] Furthermore, the second layer 32 can be between 5 nm and 15 nm thick.

[0095] The formation of this second layer 32 may comprise a chemical vapour phase deposition, for example a plasma enhanced chemical vapour phase deposition.

[0096] In a particularly advantageous way, the first layer 31 and the second layer 32 are formed in the same deposition chamber without venting the chamber. Such a sequence protects the first layer 31 from moisture after step b).

[0097] The invention is not limited to this deposition technique alone and may alternatively comprise a chemical vapour deposition of an organometallic precursor, or a deposition in atomic layers.

[0098] The method may also comprise a step d) that comprises the performance of a heat treatment intended to crystallise the material forming the second layer 32 exclusively. The size of the grains formed during crystallisation is also limited to the thickness of the second layer 32. Thus, the consideration of a second thin layer, for example with a thickness of between 5 nm and 15 nm, makes it possible to impose that the size of said grains is also within this range.

[0099] In this regard, the heat treatment may comprise a fast thermal annealing that comprises a temperature rise to a temperature of less than 1100° C., advantageously less than 1050° C., and that lasts for less than 10 seconds, advantageously less than 1 second.

[0100] This heat treatment may also be followed by an additional heat treatment designed to degas the first layer 31 and the second layer 32. This additional heat treatment, with a view to degassing layers 31 and 32, also leads to crystallisation of the first layer 31. Consideration of the second layer 32, crystallised during the heat treatment, makes it possible to limit the size of grains formed during the crystallisation of the first layer 32 during this additional heat treatment. In particular, the grains of the second layer 32 act as germs during crystallisation.

[0101] A high atomic carbon content, in particular between 30% and 50%, increases the thermal budget necessary for the crystallisation of silicon carbide, but also contributes to slowing this crystallisation. Thus, the combination of a high carbon content and the second layer according to the terms of this invention make it possible to limit the size of grains in the first layer, and to freeze their structure during subsequent heat treatments that may occur.

[0102] The method according to this invention may also include a transfer of the insulating layer 40 and the semiconductor layer 50 from a donor substrate 60 onto the second layer 32.

[0103] The transfer may include a step 1) to supply a donor substrate 60.

[0104] For example, the donor substrate 60 may comprise silicon, and particularly monocrystalline silicon. The insulating layer 40 may comprise silicon dioxide and be between about 10 nm and 1000 nm thick.

[0105] The method also includes a step 2) to form the insulating layer 40 on a face called the principal face 61 of the donor substrate 60 (FIG. 6).

[0106] The insulating layer 40 can be formed during a deposition step, or simply be the result of a thermal oxidation step of the silicon donor substrate 60.

[0107] Step 2) is followed by a step 3) to form an embrittlement zone 62 in the donor substrate 60 that, with the insulating layer 40, delimits the semiconductor layer 30 (FIG. 7). In other words, the semiconductor layer 50 extends from the principal face 61 of the donor substrate 60 with a thickness determined by the position of the embrittlement zone 62.

[0108] Formation of the embrittlement zone 62 may comprise a step to implant species, particularly light ions such as hydrogen ions and/or helium ions. For example, the dose of implanted species may be greater than 10.sup.16 atoms/cm.sup.2.

[0109] The method may also comprise a step 4) for assembling the insulating layer 40 with the second layer 32 (FIG. 8).

[0110] For example, the assembly step may comprise a molecular bonding by contact between the insulating layer 40 and the second layer 32.

[0111] Finally, step 4) may be followed by a step 5) to fracture the donor substrate at the embrittlement zone 62 so as to transfer the insulating layer 40 and the semiconductor layer 50 onto the second layer 32 (FIG. 9).

[0112] Finishing steps, such as polishing and/or heat treatments, may also be considered to reinforce the assembly interface and/or smooth the face of the semiconductor layer 50 exposed to the outside environment.

[0113] Thus the method according to this invention can be used to form a useful substrate 10 of the semiconductor on insulator type that comprises a trapping structure formed from the first layer 31 and the second layer 32.

[0114] In particular, in this invention, the first layer 31 comprises silicon carbide, in particular with an atomic carbide content between 30% and 50%. The carbon atoms contained in the first layer 31 are all trapping sites that enhance the trapping capabilities of the trapping structure 30. They also limit crystallisation of the first layer 31.

[0115] Consideration of the second layer 32, made of a material with a crystallisation temperature lower than that of amorphous silicon carbide, makes it possible to crystallise the second layer before the first layer 31. Since this layer may be thin, the grains formed during its crystallisation remain small (less than the thickness of the second layer), and act as germs for crystallisation of the silicon carbide in the first layer that may occur during thermal annealing. In other words, the size of silicon carbide grains that can be formed is governed by the grain size of the material forming the first layer.

[0116] The useful substrate 10 thus obtained may advantageously comprise a second layer 32 made of polycrystalline silicon, and a relatively thin insulation layer 40, for example between 2 nm and 25 nm thick.

[0117] This configuration known as UTBB SOI (for SOI substrate with an ultra-thin body and buried oxide layer) is also associated with a relatively thin semiconductor layer 50 (FIG. 10).

[0118] Such a UTBB SOI substrate can advantageously be used, for example, to co-integrate RF devices with logical devices. In this regard, this co-integration may involve the formation of zones “B” in which the stack 11 is replaced by monocrystalline silicon while keeping the stack 11 in zones “A”. In addition, zones “A” and “B” are advantageously separated from each other by STI isolation trenches.

[0119] The formation of zones “B” may involve firstly the production of the STI isolation trenches, then etching of the stack 11 and finally growth of monocrystalline silicon (epitaxial growth).

[0120] The consideration of relatively thin layers facilitates the etching step for the creation of hybrid zones “B”.

[0121] Advantageously, the second layer 32, that includes small grains, enables control over the variability of the threshold voltage associated with the back gate of a transistor that may be formed on or in the semiconductor layer 50.

[0122] Furthermore, the depth of the STI isolation trenches, that is greater than the total thickness of the stack 11, thus reduces the leakage paths between zones “A”.

[0123] FIG. 11 shows a second example of an embodiment for forming the trapping structure 30 starting from a silicon on insulator substrate 70.

[0124] The silicon on insulator substrate 70 comprises in particular a silicon substrate 71, and a second insulating layer 41 and a second semiconductor layer 51 covering a principal face of this substrate.

[0125] This example includes the formation of first STI trenches 1 and second STI trenches 2 on a silicon on insulator substrate 70. This formation includes in particular etching of the second insulation layer 41 and the second semiconductor layer 51. In this example, the STI trenches 1 and 2 are filled with an insulating material 72, for example silicon dioxide. However, the second STI trenches 2 also comprise the trapping structure 30 intercalated between firstly the bottom part and possibly the walls of the said trench, and secondly the insulating material 72. In other words, the trapping structure 30 is formed before the insulating material 72.

[0126] Details relating to the formation of the STI trenches 1 and 2 are known to a person skilled in the art and are therefore not presented in this application.

[0127] In addition, the trapping structure 30 is formed in a manner that does not present a section exposed to the external environment. In other words, formation of the trapping structure may involve etching of the trapping structure at the walls of the second STI trenches 2.

[0128] This second embodiment may also comprise consideration of zones A2 and zones B2. In this regard, zones A2 are zones in which the second insulation layer 41 and the second semiconductor layer 51 are preserved, while these two layers 41 and 51 are replaced by monocrystalline silicon in the second zones B2.

[0129] STI 2 are then advantageously used for the formation of passive components 73, such as inductors.

[0130] FIG. 12 shows a third example of the formation of the trapping structure 30.

[0131] Like the second embodiment, the silicon on insulator substrate 70 is also considered.

[0132] This third embodiment comprises the formation of the first STI trenches 1, and hybrid zones B2 while retaining the zones A2 described above.

[0133] In this example, the trapping structure 30 is formed covering the hybrid zones B2.

[0134] The different embodiments of this invention use a trapping structure that has reduced sensitivity to heat treatments.

[0135] Furthermore, this trapping structure does not use an interface layer that can disturb interactions between free carriers and the traps of the trapping structure.

[0136] It is understood that each embodiment considered in this invention may use elements of the other embodiments presented, provided that they are compatible.

[0137] FIG. 13 illustrates a useful substrate according to a fourth example embodiment for forming the trapping structure according to this invention.

[0138] For the purpose of this example, the second layer 32 has a first region 32A and a second region 32B distinguished from each other by different concentrations of doping elements of said second material. Thus for example, the first region 32A may have a concentration of dopant elements of the unintentionally doped type, and the second region 32B may have a concentration of dopant elements of the intentionally doped type, for example because of a localised doping elements implantation step. According to this example, the second region 32B of the second layer 32 then has a higher concentration of dopant elements than the first region 32B of the second layer 32.

[0139] Obviously, without going outside the scope of the invention, it is also possible that the first and second regions 32A, 32B of the second layer 32, are both of a intentionally doped type, these regions being distinguished from each other by a concentration of doping elements. Thus, the second region 32B may have a concentration of dopant elements of the same type as that of the first region 32A of the second layer 32, for example an N (or P) type doping, with a higher concentration of said doping elements, or it may have a concentration of doping elements of a type distinct from that of the first 32A region of the second layer 32, for example the first region 32A having N type doping and the second region 32B having P type doping.

[0140] Such a presence of a first region 32A and a second region 32B with different configurations of doping elements (this difference may be related to the type of conductivity, with conductivities being opposite, or one may have one type among N and

[0141] P doping, and the other a conductivity type of the intrinsic doping type, or related to distinct concentrations for each), makes it possible for the second layer 32 to provide different functions. For example, through one of these regions 32A, 32B, the second layer 32 can provide a back gate function for field effect transistors made in the second semiconductor layer 51, and through the other region 32A, 32B, can provide a trapping zone function for components with no back gate.

[0142] As shown in FIG. 13, in this fourth example, the first region 32A of the second layer 32 with a corresponding region 31A of the first layer 31 forms a trapping substructure 30A. Similarly, the second region 32B of the second layer 32 with a corresponding region 31B of the first layer 31 forms a second trapping substructure 30B. The first trapping substructure 30A and the second trapping substructure 30B are separated from each other by an STI isolation trench 3 filled with insulating material 72.

[0143] Note that each of these trapping substructures is associated with a second insulation layer 41 and the corresponding second semiconductor layer 51. In this way, two distinct zones C2, C3 are formed in the useful substrate, one C3 associated with the first trapping substructure 30A and the other C2 associated with the second trapping substructure 30B.

[0144] According to one possibility of this fourth embodiment, and in exactly the same way as for the first, second and third example embodiments of the formation of the trapping structure according to this invention, a zone B of the useful substrate may be provided in which the second insulation layer 41 and the second semiconductor layer are replaced by monocrystalline silicon. In accordance with the first, second and third example embodiments, said zone B is separated from the two zones C2, C3 by an STI isolating trench 3 filled with insulating material 72. Such a useful substrate may be made by the use of a production method according to the invention for which:

[0145] during step d) to form the second layer 32 covering the first layer 31, the second material is an amorphous semiconductor, said second layer 32 having a first region 32A and a second region 32B distinguished from each other by a different concentration of dopant elements of said second material;

[0146] it is included the formation of at least one STI isolation trench 3 filled with an insulating material to separate the first trapping substructure 30A from the second trapping substructure 30B.

[0147] It should be noted that in this method, the step d) to form the second layer 32 may comprise a localised implantation step for at least one of the first and second regions 32A, 32B of the second layer 32 so that first region 32A and the second region 32B may be provided with different concentrations of doping elements.

[0148] According to the possibility by which a zone B of the useful substrate is provided in which the second insulation layer 41 and the second semiconductor layer are replaced by monocrystalline silicon, the method may include a later step comprising the following sub-steps:

[0149] removal of the first layer 31 and the second layer 32 on a part of the support substrate 20;

[0150] the formation of a semiconductor layer at least partially covering the part of the support substrate from which the first layer and the second layer have been removed.

REFERENCES

[0151] [1] WO 2012/127006;

[0152] [2] WO 2017/144821;

[0153] [3] US 2016/0071959;

[0154] [4] Yoshimo Miura et al., “Paramagnetic Defects Related to Positive Charges in Silicon Oxynitride Films”, Jpn. J. Appl. Phys., Vol. 39, pp. L 987-L989, (2000).