Wafer structure

Abstract

A wafer structure is disclosed and includes a chip substrate and a plurality of inkjet chips. The chip substrate is a silicon substrate fabricated by a semiconductor process. At least one inkjet chip is directly formed on the chip substrate by the semiconductor process and diced into the at least one inkjet chip for inkjet printing. Each of the inkjet chip includes a plurality of ink-drop generators produced by a semiconductor process and formed on the chip substrate. Each of the ink-drop generators includes a thermal-barrier layer, a resistance heating layer, a conductive layer, a protective layer, a barrier layer, an ink-supply chamber and a nozzle.

Claims

1. A wafer structure, comprising: a chip substrate, which is a silicon substrate; and at least one inkjet chip directly formed on the chip substrate which is diced into the at least one inkjet chip for inkjet printing; wherein each of the inkjet chip comprises: at least one ink-supply channel configured to provide ink; and a plurality of ink-drop generators formed on the chip substrate and respectively connected to the at least one ink-supply channel, wherein each of the ink-drop generators comprises a thermal-barrier layer, a resistance heating layer, a conductive layer, a protective layer, a barrier layer, an ink-supply chamber and a nozzle; wherein the thermal-barrier layer is a heat insulation material formed on the chip substrate, the resistance heating layer is a resistance material formed on the thermal-barrier layer, the conductive layer is a conductive material, a part of the conductive layer is formed on the resistance heating layer, a part of the protective layer is formed on the resistance heating layer and the rest part of the protective layer is formed on the conductive layer, and the barrier layer is a polymer material directly formed on the protective layer, wherein the ink-supply chamber and the nozzle are integrally formed in the barrier layer, and the ink-supply chamber has a bottom in communication with the protective layer and a top in communication with the nozzle, wherein the barrier layer includes two opposite inner sidewalls defining two opposite sides of the ink-supply chamber, each of the two opposite inner sidewalls of the barrier layer continuously extends from a respective one of two opposite sides of a top surface of a continuous portion of the protective layer toward the nozzle, the two opposite inner sidewalls of the barrier layer entirely and directly overlap with the conductive layer in a direction normal to the bottom of the ink-supply chamber, and the top surface of the continuous portion of the protective layer is the bottom of the ink-supply chamber, and wherein an ink supply path is formed between the at least one ink-supply channel and the ink-supply chamber of each of the plurality of ink-drop generators, and the ink supply path is configured to supply the ink from the at least one ink-supply channel to the ink-supply chamber in a plane parallel with the bottom of the ink supply chamber.

2. The wafer structure according to claim 1, wherein the heat insulation material is one selected from the group consisting of field oxide (FOX), silicon dioxide (SiO.sub.2), silicon nitride (Si.sub.3N.sub.4) and phosphosilicate glass (PSG).

3. The wafer structure according to claim 1, wherein the resistance material is one selected from the group consisting of poly silicon, tantalum aluminide (TaAl), tantalum (Ta), tantalum nitride (TaN), tantalum disilicide (Si.sub.2Ta), carbon (C), silicon carbide (SiC), indium tin oxide (ITO), Zinc oxide (ZnO), cadmium sulfide (CdS), hafnium diboride (HfB.sub.2), titanium tungsten alloy (TiW) and titanium nitride (TiN).

4. The wafer structure according to claim 1, wherein the conductive material is one selected from the group consisting of aluminum (Al), aluminum copper alloy (AlCu), aluminum silicon alloy (AlSi), gold (Au), palladium (Pd), palladium silver alloy (PdAg), platinum (Pt), aluminum silicon copper (AlSiCu), niobium (Nb), vanadium (V), hafnium (Hf), titanium (Ti), zirconium (Zr) and yttrium (Y).

5. The wafer structure according to claim 1, wherein the protective layer includes a first protective layer served as a lower layer stacked by a second protective layer served as an upper layer.

6. The wafer structure according to claim 5, wherein the first protective layer is a passivation material and, the passivation material is one selected from the group consisting of silicon nitride (Si.sub.3N.sub.4), silicon dioxide (SiO.sub.2), titanium dioxide (TiO.sub.2), hafnium dioxide (HfO.sub.2), zirconium dioxide (ZrO.sub.2), tantalum pentoxide (Ta.sub.2O.sub.5), dirhenium heptoxide (Re.sub.2O.sub.7), niobium pentoxide (Nb.sub.2O.sub.5), diuranium pentoxide (U.sub.2O.sub.5), tungsten trioxide (WO.sub.3), silicon oxynitride (Si.sub.4O.sub.5N.sub.3) and silicon carbide (SiC).

7. The wafer structure according to claim 5, wherein the second protective layer is a metallic material and the metallic material is one selected from the group consisting of tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN) and tungsten nitride (TiW).

8. The wafer structure according to claim 1, wherein the polymer material is one selected from the group consisting of polyimide and an organic plastic material.

9. The wafer structure according to claim 1, wherein the inkjet chip further comprises a plurality of manifolds, the at least one ink-supply channel is in communication with the plurality of the manifolds, and the plurality of manifolds are in communication with each of the ink-supply chambers of the ink-drop generators.

10. The wafer structure according to claim 1, wherein the conductive layer is connected to a conductor to form an inkjet control circuit.

11. The wafer structure according to claim 1, wherein the conductive layer is connected to a conductor which is a gate of a metal oxide semiconductor field effect transistor.

12. The wafer structure according to claim 1, wherein the conductive layer is connected to a conductor which is a gate of a complementary metal oxide semiconductor.

13. The wafer structure according to claim 1, wherein the conductive layer is connected to a conductor which is a gate of an N-type metal oxide semiconductor.

14. The wafer structure according to claim 1, wherein the inkjet chip has a printing swath equal to or greater than 0.25 inches, and the inkjet chip has a width ranging from 0.5 mm to 10 mm.

15. The wafer structure according to claim 14, wherein the inkjet chip has the printing swath ranging from 0.25 inches to 1.25 inches.

16. The wafer structure according to claim 14, wherein the inkjet chip has the printing swath ranging from at least 1.25 inches to 12 inches.

17. The wafer structure according to claim 14, wherein the printing swath of the inkjet chip is at least 12 inches.

18. The wafer structure according to claim 14, wherein the printing swath of the inkjet chip is 8.3 inches.

19. The wafer structure according to claim 14, wherein the printing swath of the inkjet chip is 11.7 inches.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The above contents of the present disclosure will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:

(2) FIG. 1 is a schematic cross-sectional view illustrating an ink-drop generator according to the prior art;

(3) FIG. 2 is a schematic view illustrating a wafer structure according to an embodiment of the present disclosure;

(4) FIG. 3 is a schematic cross-sectional view illustrating the ink-drop generators on the wafer structure according to the embodiment of the present disclosure;

(5) FIG. 4A is a schematic view illustrating the ink-supply channels, the manifolds and the ink-supply chamber arranged on the inkjet chip of the wafer structure according to the embodiment of the present disclosure,

(6) FIG. 4B is a partial enlarged view illustrating the region C of FIG. 4A;

(7) FIG. 4C is a schematic view illustrating the nozzles formed and arranged on the inkjet chip of FIG. 4A;

(8) FIG. 4D is a schematic view illustrating the ink-supply channels and the elements of the conductive layer arranged on the inkjet chip of the wafer structure according to another embodiment of the present disclosure;

(9) FIG. 5 is a schematic view illustrating the circuit diagram for heating the resistance heating layer under the control and excitement of the conductive layer according to the embodiment of the present disclosure;

(10) FIG. 6 is an enlarged view illustrating the ink-drop generators formed and arranged on the wafer structure according to the embodiment of the present disclosure; and

(11) FIG. 7 is a schematic view illustrating an internal carrying system applied to an inkjet printer.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

(12) The present disclosure will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed.

(13) Please refer to FIG. 2. The present disclosure provides a wafer structure 2. The wafer structure 2 includes a chip substrate 20 and a plurality of inkjet chips 21. Preferably but not exclusively, the chip substrate 20 is a silicon substrate and fabricated by a semiconductor process. In an embodiment, the chip substrate 20 is fabricated by the semiconductor process on a 12-inch wafer. In another embodiment, the chip substrate 20 is fabricated by the semiconductor process on a 16-inch wafer.

(14) In the embodiment, the plurality of inkjet chips 21 are directly formed on the chip substrate 20 by the semiconductor process, respectively, and the inkjet chips 21 are diced into at least one inkjet chip 21 for a printhead 111. In the embodiment, each of the inkjet chips 21 includes a plurality of ink-drop generators 22 formed on the chip substrate 20 by the semiconductor process. As shown in FIG. 3, each of the ink-drop generators 22 includes a thermal-barrier layer 221, a resistance heating layer 222, a conductive layer 223, a protective layer 224, a barrier layer 225, an ink-supply chamber 226 and a nozzle 227.

(15) In the embodiment, the thermal-barrier layer 221 is a heat insulation material formed on the chip substrate 20. Preferably but not exclusively, the heat insulation material is one selected from the group consisting of field oxide (FOX), silicon dioxide (SiO.sub.2), silicon nitride (Si.sub.3N.sub.4) and phosphosilicate glass (PSG).

(16) In the embodiment, the resistance heating layer 222 is a resistance material formed on the thermal-barrier layer 221. Preferably but not exclusively, the resistance material is one selected from the group consisting of poly silicon, tantalum aluminide (TaAl), tantalum (Ta), tantalum nitride (TaN), tantalum disilicide (Si.sub.2Ta), carbon (C), silicon carbide (SiC), indium tin oxide (ITO), Zinc oxide (ZnO), cadmium sulfide (CdS), hafnium diboride (HfB.sub.2), titanium tungsten alloy (TiW) and titanium nitride (TiN).

(17) In the embodiment, the conductive layer 223 is a conductive material formed on the resistance heating layer 222. Preferably but not exclusively, the conductive material is one selected from the group consisting of aluminum (Al), aluminum copper alloy (AlCu), aluminum silicon alloy (AlSi), gold (Au), palladium (Pd), palladium silver alloy (PdAg), platinum (Pt), aluminum silicon copper (AlSiCu), niobium (Nb), vanadium (V), hafnium (Hf), titanium (Ti), zirconium (Zr) and yttrium (Y).

(18) In the embodiment, a part of the protective layer 224 is formed on the resistance heating layer 222. The rest part of the protective layer 224 is formed on the conductive layer 223. The protective layer 224 includes a first protective layer 224A served as a lower layer stacked by a second protective layer 224B served as an upper layer. The first protective layer 224A is a passivation material. Preferably but not exclusively, the passivation material is one selected from the group consisting of silicon nitride (Si.sub.3N.sub.4), silicon dioxide (SiO.sub.2), titanium dioxide (TiO.sub.2), hafnium dioxide (HfO.sub.2), zirconium dioxide (ZrO.sub.2), tantalum pentoxide (Ta.sub.2O.sub.5), dirhenium heptoxide (Re.sub.2O.sub.7), niobium pentoxide (Nb.sub.2O.sub.5), diuranium pentoxide (U.sub.2O.sub.5), tungsten trioxide (WO.sub.3), silicon oxynitride (Si.sub.4O.sub.5N.sub.3) and silicon carbide (SiC). The second protective layer 224B is a metallic material. The metallic material is one selected from the group consisting of tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN) and tungsten nitride (TiW).

(19) In the embodiment, the barrier layer 225 is a polymer material formed on the protective layer 224. The polymer material is one selected from the group consisting of polyimide and an organic plastic material. Moreover, the ink-supply chamber 226 and the nozzle 227 are integrally formed in the barrier layer 225. In the embodiment, a bottom of the ink-supply chamber 226 is in communication with the protective layer 224. The top of the ink-supply chamber 226 is in communication with the nozzle 227.

(20) The internal structure of the ink drop generator 22 and the materials used for producing it have been disclosed in detail above, and how the ink drop generator 22 is fabricated by the semiconductor process on the chip substrate 20 is described below.

(21) Firstly, a thin film of the thermal-barrier layer 221 is formed on the chip substrate 20, and the resistance heating layer 222 and the conductive layer 223 are successively disposed thereon by sputtering. The required size is defined by the process of photolithography. Afterwards, the protective layer 224 is coated thereon through a sputtering device or a chemical vapor deposition (CVD) device. Then, the ink-supply chamber 226 is formed on the protective layer 224 by compression molding of a polymer film, and the nozzle 227 is formed by compression molding of a polymer film coated thereon, so as to integrally form the barrier layer 225 on the protective layer 224. In this way, the ink-supply chamber 226 and the nozzle 227 are integrally formed in the barrier layer 225. Alternatively, in another embodiment, a polymer film is formed on the protective layer 224 to directly define the ink-supply chamber 226 and the nozzle 227 by a photolithography process. In this way, the ink-supply chamber 226 and the nozzle 227 are also integrally formed in the barrier layer 225. The bottom of the ink-supply chamber 226 is in communication with the protective layer 224, and the top of the ink-supply chamber 226 is in communication with the nozzle 227. In the embodiment, the chip substrate 20 is a silicon substrate made of silicon oxide (SiO.sub.2). The resistance heating layer 222 is made of a tantalum aluminide (TaAl) material. The conductive layer 223 is made of an aluminum (Al) material. The protective layer 224 is formed by stacking a second protective layer 224B as an upper layer above on a first protective layer 224A as an under layer. The first protective layer 224A is made of a silicon nitride (Si.sub.3N.sub.4) material. The second protective layer 224B is made of a silicon carbide (SiC) material. The barrier layer 225 is made of a polymer material.

(22) Certainly, in the embodiment, the ink-drop generator 22 of the inkjet chip 21 is fabricated by the semiconductor process on the wafer substrate 20. Furthermore, in the process of defining the required size by the lithographic etching process as shown in FIGS. 4A to 4B, at least one ink-supply channel 23 and a plurality of manifolds 24 are defined. Then, the ink-supply chamber 226 is formed on the protective layer 224 by dry film compression molding, and a dry film is coated to form the nozzle 227 by dry film compression molding, so that the barrier layer 225 is integrally formed on the protective layer 224 as shown in FIG. 3. Moreover, the ink-supply chamber 226 and the nozzle 227 are integrally formed in the barrier layer 225. In the embodiment, the bottom of the ink-supply chamber 226 is in communication with the protective layer 224, and the top of the ink-supply chamber 226 is in communication with the nozzle 227. The plurality of nozzles 227 are directly exposed on the surface of the inkjet chip 21 and arranged in the required arrangement, as shown in FIG. 4D. Therefore, the ink-supply channels 23 and the plurality of manifolds 24 are also fabricated by the semiconductor process at the same time. Each of the plurality of ink-supply channels 23 provides ink, and the ink-supply channel 23 is in communication with the plurality of manifolds 24. Moreover, the plurality of manifolds 24 are in communication with each of the ink-supply chambers 226 of the ink-drop generators 22. As shown in FIG. 4B, the resistance heating layer 222 is formed and exposed in the ink-supply chamber 226. The resistance heating layer 222 has a rectangular area formed with a length HL and a width HW.

(23) Please refer to FIGS. 4A and 4C. The number of the at least one ink-supply channel 23 may be one to six. As shown in FIG. 4A, the number of the at least one ink-supply channel 23 arranged on a single inkjet chip 21 is one, thereby providing monochrome ink. Preferably but not exclusively, the monochrome ink is selected from the group consisting of cyan, magenta, yellow and black ink. As shown in FIG. 4C, the number of the at least one ink-supply channel 23 arranged on a single inkjet chip 21 is six, thereby providing six-color ink of black, cyan, magenta, yellow, light cyan and light magenta, respectively. Certainly, in other embodiments, the number of the at least one ink-supply channel 23 arranged on a single inkjet chip 21 may be four, thereby providing four-color ink of cyan, magenta, yellow and black, respectively. The number of the ink-supply channels 23 is adjustable and can be designed according to the practical requirements.

(24) Please refer to FIG. 3, FIG. 4A, FIG. 4C and FIG. 5. In the embodiment, the conductive layer 223 is fabricated by the semiconductor process on the wafer structure 2. Preferably but not exclusively, the conductors connected in the conductive layer 223 fabricated by the semiconductor process of less than 90 nanometers form an inkjet control circuit. In that, more metal oxide semiconductor field-effect transistors (MOSFETs) are arranged in the inkjet control circuit zone 25 to control the resistance heating layer 222. Therefore, the resistance heating layer 222 is activated for heating as the circuit is formed. Alternatively, the resistance heating layer 222 is not activated for heating as the circuit is not formed. That is, as shown in FIG. 5, when a voltage Vp is applied to the resistance heating layer 222, the transistor switch Q controls the circuit state of the resistance heating layer 222 by grounding. When one end of the resistance heating layer 222 is grounded, a circuit is formed to activate the resistance heating layer 222 for heating. Alternatively, if the resistance heating layer 222 is not grounded, the circuit is not formed and the resistance heating layer 222 is not activated for heating. Preferably but not exclusively, the transistor switch Q is a metal oxide semiconductor field effect transistor (MOSFET), and the conductor connected by the conductive layer 223 is a gate G of the metal oxide semiconductor field effect transistor (MOSFET). In other embodiments, the conductor connected by the conductive layer 223 is a gate G of a complementary metal oxide semiconductor (CMOS). Alternatively, the conductor connected by the conductive layer 223 is a gate G of an N-type metal oxide semiconductor (NMOS), but not limited thereto. The conductor connected by the conductive layer 223 is adjustable and can be selected according to the practical requirements for the inkjet control circuit. Certainly, in an embodiment, the conductor connected by the conductive layer 223 is fabricated by the semiconductor process of 65 nanometers to 90 nanometers, to form the inkjet control circuit. In an embodiment, the conductor connected by the conductive layer 223 is fabricated by the semiconductor process of 45 nanometers to 65 nanometers, to form the inkjet control circuit. In an embodiment, the conductor connected by the conductive layer 223 is fabricated by the semiconductor process of 28 nanometers to 45 nanometers, to form the inkjet control circuit. In an embodiment, the conductor connected by the conductive layer 223 is fabricated by the semiconductor process of 20 nanometers to 28 nanometers, to form the inkjet control circuit. In an embodiment, the conductor connected by the conductive layer 223 is fabricated by the semiconductor process of 12 nanometers to 20 nanometers, to form the inkjet control circuit. In an embodiment, the conductor connected by the conductive layer 223 is fabricated by the semiconductor process of 7 nanometers to 12 nanometers, to form the inkjet control circuit. In an embodiment, the conductor connected by the conductive layer 223 is fabricated by the semiconductor process of 2 nanometers to 7 nanometers, to form the inkjet control circuit. It is understandable that the more sophisticated the semiconductor process technology is, the more groups of inkjet control circuits can be fabricated within the same unit volume.

(25) As described above, the present disclosure provides the wafer structure 2 including the chip substrate 20 and the plurality of inkjet chips 21. The chip substrate 20 is fabricated by the semiconductor process, so that more inkjet chips 21 required can be arranged on the chip substrate 20. The restriction of the chip substrate 20 for the inkjet chips 21 is reduced. Moreover, the unused area on the chip substrate 20 is reduced. Consequently, the utilization of the chip substrate 20 is improved, the vacancy rate of the chip substrate 20 is reduced, and the manufacturing cost is reduced. At the same time, the printing quality pursuit of higher resolution and higher printing speed is achieved.

(26) The design of the resolution and the sizes of printing swath Lp of the inkjet chips 21 are described below.

(27) As shown in FIGS. 4D and 6, each of the inkjet chips 21 covers a rectangular area with a length L and a width W, and a printing swath Lp. In the embodiment, each of the inkjet chips 21 includes a plurality of ink-drop generators 22 produced by the semiconductor process on the chip substrate 20. In the inkjet chip 21, the plurality of ink-drop generators 22 are arranged in the longitudinal direction to form a plurality of longitudinal axis array groups (Ar1 . . . Arn) having a pitch M maintained between two adjacent ink-drop generators 22 in the longitudinal direction; and the plurality of ink-drop generators 22 are also arranged in the horizontal direction to form a plurality of horizontal axis array groups (Ac1 . . . Acn) having a central stepped pitch P maintained between two adjacent ink-drop generators 22 in the horizontal direction. That is, as shown in FIG. 6, the pitch M is maintained between the ink-drop generator 22 with the coordinate (Ar1, Ac1) and the ink-drop generator 22 with the coordinate (Ar1, Ac2). Moreover, the central stepped pitch P is maintained between the ink-drop generator 22 with the coordinate (Ar1, Ac1) and the ink-drop generator 22 with the coordinate (Ar2, Ac1). The resolution number of dots per inch (DPI) for the inkjet chip 21 is equal to 1/(the central stepped pitch P). Therefore, in order to achieve the required higher resolution, a layout design with a resolution of at least 600 DPI is utilized in the present disclosure. Namely, the central stepped pitch P is at least equal to 1/600 inches or less. Certainly, the resolution DPI of the inkjet chip 21 in the present disclosure can also be designed with at least 600 DPI to 1200 DPI. That is, the central stepped pitch P is equal to at least 1/600 inches to 1/1200 inches. Preferably but not exclusively, the resolution DPI of the inkjet chip 21 is designed with 720 DPI, and the central stepped pitch P is at least equal to 1/720 inches or less. Preferably but not exclusively, the resolution DPI of the inkjet chip 21 in the present disclosure is designed with at least 1200 DPI to 2400 DPI. That is, the central stepped pitch P is equal to at least 1/1200 inches to 1/2400 inches. Preferably but not exclusively, the resolution DPI of the inkjet chip 21 in the present disclosure is designed with at least 2400 DPI to 24000 DPI. That is, the central stepped pitch P is equal to at least 1/2400 inches to 1/24000 inches. Preferably but not exclusively, the resolution DPI of the inkjet chip 21 in the present disclosure is designed with at least 24000 DPI to 48000 DPI. That is, the central stepped pitch P is equal to at least 1/24000 inches to 1/48000 inches.

(28) In the embodiment, the inkjet chip 21 disposed on the wafer structure 2 has a printing swath Lp, which is more than 0.25 inches. Preferably but not exclusively, the printing swath Lp of the inkjet chip 21 ranges from at least 0.25 inches to 0.5 inches. Preferably but not exclusively, the printing swath Lp of the inkjet chip 21 ranges from at least 0.5 inches to 0.75 inches. Preferably but not exclusively, the printing swath Lp of the inkjet chip 21 ranges from at least 0.75 inches to 1 inch. Preferably but not exclusively, the printing swath Lp of the inkjet chip 21 ranges from at least 1 inch to 1.25 inches. Preferably but not exclusively, the printing swath Lp of the inkjet chip 21 ranges from at least 1.25 inches to 1.5 inches. Preferably but not exclusively, the printing swath Lp of the inkjet chip 21 ranges from at least 1.5 inches to 2 inches. Preferably but not exclusively, the printing swath Lp of the inkjet chip 21 ranges from at least 2 inches to 4 inches. Preferably but not exclusively, the printing swath Lp of the inkjet chip 21 ranges from at least 4 inches to 6 inches. Preferably but not exclusively, the printing swath Lp of the inkjet chip 21 ranges from at least 6 inches to 8 inches. Preferably but not exclusively, the printing swath Lp of the inkjet chip 21 ranges from at least 8 inches to 12 inches. Preferably but not exclusively, the printing swath Lp of the inkjet chip 21 is 8.3 inches, and 8.3 inches is the page width of the A4-size paper, so that the inkjet chip 21 is provided with the page width print function on the A4-size paper. Preferably but not exclusively, the printing swath Lp of the inkjet chip 21 is 11.7 inches, and 11.7 inches is the page width of the A3-size paper, so that the inkjet chip 21 is provided with the page width print function on the A3-size paper. Preferably but not exclusively, the printing swath Lp of the inkjet chip 21 is equal to or greater than 12 inches. In the embodiment, the inkjet chip 21 disposed on the wafer structure 2 has a width W, which ranges from at least 0.5 mm to 10 mm. Preferably but not exclusively, the width W of the inkjet chip 21 ranges from at least 0.5 mm to 4 mm. Preferably but not exclusively, the width W of the inkjet chip 21 ranges from at least 4 mm to 10 mm.

(29) In the present disclosure, the wafer structure 2 is provided and includes the chip substrate 20 and the plurality of inkjet chips 21. The chip substrate 20 is fabricated by the semiconductor process, so that a larger number of required inkjet chips 21 can be arranged on the chip substrate 20. Therefore, the plurality of inkjet chips 21 diced from the wafer structure 2 of the present disclosure can be implemented for inkjet printing of a printhead 111. Please refer to FIG. 7. In the embodiment, the carrying system 1 is mainly used to support the structure of the printhead 111 in the present disclosure. The carrying system 1 includes a carrying frame 112, a controller 113, a first driving motor 116, a position controller 117, a second driving motor 119, a paper feeding structure 120 and a power source 121. The power source 121 provides electric energy for the operation of the entire carrying system 1. In the embodiment, carrying frame 112 is mainly used to accommodate the printhead 111 and includes one end connected with the first driving motor 116, so as to drive the printhead 111 to move along a linear track in the direction of a scanning axis 115. Preferably but not exclusively, the printhead 111 is detachably or permanently installed on the carrying frame 112. The controller 113 is connected to the carrying frame 112 to transmit a control signal to the printhead 111. Preferably but not exclusively, in the embodiment, the first driving motor 116 is a stepping motor. The first driving motor 116 is configured to move the carrying frame 112 along the scanning axis 115 according to a control signal sent by the position controller 117, and the position controller 117 determines the position of the carrying frame 112 on the scanning axis 115 through a storage device 118. In addition, the position controller 117 is also configured to control the operation of the second driving motor 119 to drive the printing medium 122, such as paper, and the paper feeding structure 120. In that, the printing medium 122 is moved along the direction of a feeding axis 114. After the printing medium 122 is positioned in the printing area (not shown), the first driving motor 116 is driven by the position controller 117 to move the carrying frame 112 and the printhead 111 along the scanning axis 115 for printing on the printing medium 122. After one or more scanning is performed along the scanning axis 115, the position controller 117 controls the second driving motor 119 to operate and drive the printing medium 122 and the paper feeding structure 120. In that, the printing medium 122 is moved along the feeding axis 114 to place another area of the printing medium 122 into the printing area. Then, the first driving motor 116 drives the carrying frame 112 and the printhead 111 to move along the scanning axis 115 for performing another line of printing on the printing medium 122. When all the printing data is printed on the printing medium 122, the printing medium 122 is pushed out to an output tray (not shown) of the inkjet printer, so as to complete the printing action.

(30) In summary, the present disclosure provides a wafer structure including a chip substrate and a plurality of inkjet chips. The chip substrate is fabricated by a semiconductor process, so that more inkjet chips required are arranged on the chip substrate. Furthermore, the inkjet chips having different sizes of printing swath are directly generated in the same inkjet chip by semiconductor process at the same time. Simultaneously, the ink-supply chamber and the nozzle of the ink-drop generator are integrally formed in a barrier layer by the semiconductor process for fabricating the ink-drop generator, so that such semiconductor process for fabricating the inkjet chips can arrange a layout of a printing inkjet design for higher resolution and higher performance. The wafer structure is diced into the inkjet chips used in inkjet printing to reduce the manufacturing cost of the inkjet chips and fulfill the requirement of printing quality pursuit of higher resolution and higher printing speed. The present disclosure includes the industrial applicability and the inventive steps.

(31) While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.