Sample and hold circuit and method

Abstract

Disclosed is a sample and hold circuit and method capable of amplifying an input signal. The method includes: in a sample phase, receiving a first (second) input signal with top electrodes of first (second) capacitors, and receiving the second (first) input signal with all bottom electrode(s) of at least a part of the first (second) capacitors; in a hold phase, stopping receiving the first (second) input signal with the top electrodes of the first (second) capacitors, and receiving a first (second) group of reference signals with the bottom electrodes of the first (second) capacitors, so that the first (second) capacitors provide a first (second) sample voltage on the top electrodes of the multiple first (second) capacitors through charge redistribution, wherein the first and second input signals are a pair of differential signals and they are opposite to each other.

Claims

1. A sample and hold circuit, comprising: a control circuit configured to generate a first input switch control signal and a first set of switch control signals, and to generate a second input switch control signal and a second set of switch control signals; a first input switch configured to be turn on according to the first input switch control signal in a sample phase and thereby transmit a first input signal, and to be turned off according to the first input switch control signal in a hold phase; a first set of switches configured to operate according to the first set of switch control signals; a first capacitor array including first capacitors coupled to the first input switch and the first set of switches, wherein top electrodes of the first capacitors receive the first input signal through the first input switch in the sample phase, all bottom electrode(s) of at least a part of the first capacitors receive(s) a second input signal through the first set of switches in the sample phase, the top electrodes of the first capacitors do not receive the first input signal in the hold phase, all bottom electrodes of the first capacitors receive a first group of reference signals through the first set of switches in the hold phase, and the first capacitors provide a first sample voltage on the top electrodes of the first capacitors by charge redistribution in the hold phase; a second input switch configured to be turn on according to the second input switch control signal in the sample phase and thereby transmit the second input signal, and to be turned off according to the second input switch control signal in the hold phase; a second set of switches configured to operate according to the second set of switch control signals; and a second capacitor array including second capacitors coupled to the second input switch and the second set of switches, wherein top electrodes of the second capacitors receive the second input signal through the second input switch in the sample phase, all bottom electrode(s) of at least a part of the second capacitors receive(s) the first input signal through the second set of switches in the sample phase, the top electrodes of the second capacitors do not receive the second input signal in the hold phase, all bottom electrodes of the second capacitors receive a second group of reference signals through the second set of switches in the hold phase, and the second capacitors provide a second sample voltage on the top electrodes of the second capacitors by charge redistribution in the hold phase.

2. The sample and hold circuit of claim 1, wherein the first capacitors are composed of the at least a part of the first capacitors and a remaining part of the first capacitors; all bottom electrode(s) of the remaining part of the first capacitors receive(s) a corresponding part of the first group of reference signals through the first set of switches in the sample phase; the second capacitors are composed of the at least a part of the second capacitors and a remaining part of the second capacitors; all bottom electrode(s) of the remaining part of the second capacitors receive(s) a corresponding part of the second group of reference signals through the second set of switches in the sample phase.

3. The sample and hold circuit of claim 2, wherein capacitance of the at least a part of the first capacitors is not less than capacitance of the remaining part of the first capacitors, and capacitance of the at least a part of the second capacitors is not less than capacitance of the remaining part of the second capacitors.

4. The sample and hold circuit of claim 1, wherein the first input signal and the second input signal are a pair of differential signals.

5. The sample and hold circuit of claim 1, wherein the first input signal is a signal voltage varying with time, and the second input signal is a constant voltage.

6. A sample and hold method performed with a sample and hold circuit, the method comprising: receiving a first input signal with top electrodes of first capacitors in a sample phase, and receiving a second input signal with all bottom electrode(s) of at least a part of the first capacitors in the sample phase; stopping receiving the first input signal with the top electrodes of the first capacitors in a hold phase, receiving a first group of reference signals with all bottom electrodes of the first capacitors in the hold phase, and providing a first sample voltage on the top electrodes of the first capacitors by charge redistribution in the hold phase; receiving the second input signal with top electrodes of second capacitors in the sample phase, and receiving the first input signal with all bottom electrode(s) of at least a part of the second capacitors in the sample phase; and stopping receiving the second input signal with the top electrodes of the second capacitors in the hold phase, receiving a second group of reference signals with all bottom electrodes of the second capacitors in the hold phase, and providing a second sample voltage on the top electrodes of the second capacitors by charge redistribution in the hold phase.

7. The sample and hold method of claim 6, wherein the first capacitors are composed of the at least a part of the first capacitors and a remaining part of the first capacitors; the second capacitors are composed of the at least a part of the second capacitors and a remaining part of the second capacitors; and the sample and hold method further comprises: receiving a corresponding part of the first group of reference signals with all bottom electrode(s) of the remaining part of the first capacitors in the sample phase; and receiving a corresponding part of the second group of reference signals with all bottom electrode(s) of the remaining part of the second capacitors in the sample phase.

8. The sample and hold method of claim 7, wherein capacitance of the at least a part of the first capacitors is not less than capacitance of the remaining part of the first capacitors, and capacitance of the at least a part of the second capacitors is not less than capacitance of the remaining part of the second capacitors.

9. The sample and hold method of claim 6, wherein the first input signal and the second input signal are a pair of differential signals.

10. The sample and hold method of claim 6, wherein the first input signal is a signal voltage varying with time, and the second input signal is a constant voltage.

11. A sample and hold method performed with a sample and hold circuit, the method comprising: receiving a first input signal with top electrodes of first capacitors in a sample phase, and receiving a first reference signal with all bottom electrode(s) of at least a part of the first capacitors in the sample phase; stopping receiving the first input signal with the top electrodes of the first capacitors in a hold phase, receiving a first group of reference signals with all bottom electrodes of the first capacitors in the hold phase, and providing a first sample voltage on the top electrodes of the first capacitors by charge redistribution in the hold phase; receiving a second input signal with top electrodes of second capacitors in the sample phase, and receiving a second reference signal with all bottom electrode(s) of at least a part of the second capacitors in the sample phase, wherein the second reference signal is different from the first reference signal; and stopping receiving the second input signal with the top electrodes of the second capacitors in the hold phase, receiving a second group of reference signals with all bottom electrodes of the second capacitors in the hold phase, and providing a second sample voltage on the top electrodes of the second capacitors by charge redistribution in the hold phase.

12. The sample and hold method of claim 11, wherein the first capacitors are composed of the at least a part of the first capacitors and a remaining part of the first capacitors; the second capacitors are composed of the at least a part of the second capacitors and a remaining part of the second capacitors; and the sample and hold method further comprises: receiving a corresponding part of the first group of reference signals with all bottom electrode(s) of the remaining part of the first capacitors in the sample phase; and receiving a corresponding part of the second group of reference signals with all bottom electrode(s) of the remaining part of the second capacitors in the sample phase.

13. The sample and hold method of claim 12, wherein capacitance of the at least a part of the first capacitors is not less than capacitance of the remaining part of the first capacitors, and capacitance of the at least a part of the second capacitors is not less than capacitance of the remaining part of the second capacitors.

14. The sample and hold method of claim 11, wherein the first input signal and the second input signal are a pair of differential signals.

15. The sample and hold method of claim 11, wherein the first input signal is a signal voltage varying with time, and the second input signal is a constant voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1 shows an embodiment of the sample and hold circuit of the present disclosure.

[0011] FIG. 2 shows the sample and hold circuit of FIG. 1 in the sample phase.

[0012] FIG. 3 shows the sample and hold circuit of FIG. 1 in the hold phase.

[0013] FIG. 4A shows another embodiment of the sample and hold circuit of the present disclosure.

[0014] FIG. 4B shows a modification of the embodiment of FIG. 4A.

[0015] FIG. 5 shows an embodiment of the sample and hold method of the present disclosure.

[0016] FIG. 6 shows another embodiment of the sample and hold method of the present disclosure.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] The present disclosure provides a sample and hold circuit and method capable of amplifying an input signal in a cost-effective way.

[0018] FIG. 1 shows an embodiment of the sample and hold circuit of the present disclosure. FIG. 2 shows the sample and hold circuit 100 of FIG. 1 in a sample phase. FIG. 3 shows the sample and hold circuit 100 in a hold phase. The sample and hold circuit 100 of FIG. 1 is applied to a successive-approximation register analog-to-digital converter (SAR ADC); however, it can be applied to other kinds of ADCs or circuits, if practicable. The sample and hold circuit 100 of FIG. 1 includes a control circuit 110, a first input switch 120, a first set of switches 130, a first capacitor array 140, a second input switch 150, a second set of switches 160, and a second capacitor array 170. These circuits are described in detail in the following paragraphs.

[0019] Please refer to FIGS. 1˜3. The control circuit 110 is configured to generate a first input switch control signal S.sub.1 and a first set of switch control signals S.sub.SET1, and to generate a second input switch control signal S.sub.2 and a second set of switch control signals S.sub.SET2. In this embodiment, the first and second input switch control signals S.sub.1, S.sub.2 are the same and used for controlling the operations of the first input switch 120 and the second input switch 150. The first set of switch control signal S.sub.SET1 is the same as the second set of switch control signals S.sub.SET2 in the sample and hold phases; however, in a comparison phase of the SAR ADC, the first and second sets of switch control signals S.sub.SET1, S.sub.SET2 are different due to the comparison between the voltage of the first capacitor array 140 and the voltage of the second capacitor array 170. Since the SAR ADC and the comparison phase thereof are beyond the scope of the present disclosure, they are not described in detail in this specification.

[0020] Please refer to FIGS. 1˜3. The first input switch 120 is configured to be turn on according to the first input switch control signal S.sub.1 in the sample phase and thereby transmit a first input signal V.sub.IP to the first capacitor array 140; and the first input switch 120 is configured to be turned off according to the first input switch control signal S.sub.1 in the hold phase and thereby stop transmitting the first input signal V.sub.IP to the first capacitor array 140. The second input switch 150 is configured to be turn on according to the second input switch control signal S.sub.2 in the sample phase and thereby transmit a second input signal V.sub.IN to the second capacitor array 170; and the second input switch 150 is configured to be turned off according to the second input switch control signal S.sub.2 in the hold phase and thereby stop transmitting the second input signal V.sub.IN to the second capacitor array 170. The first set of switches 130 is configured to operate according to the first set of switch control signals S.sub.SET1; similarly, the second set of switches 160 is configured to operate according to the second set of switch control signals S.sub.SET2.

[0021] Please refer to FIGS. 1˜3. The first capacitor array 140 includes first capacitors (C.sub.1_1, C.sub.1_2, C.sub.1_3, . . . , C.sub.1_(N-1), C.sub.1_N) coupled to the first input switch 120 and the first set of switches 130. In the sample phase, the top electrodes of the first capacitors receive the first input signal V.sub.IP through the first input switch 120, and all bottom electrode(s) of at least a part of the first capacitors (e.g., C.sub.1_1 in FIG. 2) receive(s) “the second input signal V.sub.IN” through the first set of switches 130; in the hold phase, the top electrodes of the first capacitors do not receive the first input signal V.sub.IP, and the bottom electrodes of the first capacitors receive a first group of reference signals REF.sub.SET1 through the first set of switches 130. In an exemplary implementation, the first group of reference signals REF.sub.SET1 is determined by the control circuit 110, and is composed of M reference voltage(s) V.sub.R and K ground voltages GND, wherein M, K are correlated with the first set of switch control signals S.sub.SET1. The first capacitors provide a first sample voltage V.sub.XP on the top electrodes of the first capacitors by charge redistribution in the hold phase.

[0022] Similarly, the second capacitor array 170 includes second capacitors (C.sub.2_1, C.sub.2_2, C.sub.2_3, . . . , C.sub.2_(N-1), C.sub.2_N) coupled to the second input switch 150 and the second set of switches 160. In the sample phase, the top electrodes of the second capacitors receive the second input signal V.sub.IN through the second input switch 150, and all bottom electrode(s) of at least a part of the first capacitors (e.g., C.sub.2_1 in FIG. 2) receive(s) “the first input signal V.sub.IP” through the second set of switches 160; in the hold phase, the top electrodes of the second capacitors do not receive the second input signal V.sub.IN, and the bottom electrodes of the second capacitors receive a second group of reference signals REF.sub.SET2 through the second set of switches 160. In an exemplary implementation, the second group of reference signals REF.sub.SET2 is determined by the control circuit 110, and is composed of P reference voltage(s) V.sub.R and Q ground voltages GND, wherein P, Q are correlated with the second set of switch control signals S.sub.SET2. The second capacitors provide a second sample voltage V.sub.XN on the top electrodes of the second capacitors by charge redistribution in the hold phase. It should be noted that the first and second groups of reference signals REF.sub.SET1, REF.sub.SET2 are determined according to the demand for implementation and can be realized with a known/self-developed technique, and this is beyond the scope of the present disclosure.

[0023] Please refer to FIGS. 1˜3. An example of the afore-mentioned first and second input signals V.sub.IP, V.sub.IN is a pair of differential signals, and thus the first and second input signals V.sub.IP, V.sub.IN are complementary. Since the top electrode(s) and the bottom electrode(s) of the at least a part of the first capacitors (e.g., C.sub.1_1 in FIG. 2) receive the first input signal V.sub.IP and the second input signal V.sub.IN in the sample phase respectively, the signal strength of a signal sampled by the at least a part of the first capacitors is two times the signal strength of the first input signal V.sub.IP (i.e., V.sub.IP−V.sub.IN=V.sub.IP+V.sub.IP=2V.sub.IP) when the common-mode voltage is the ground voltage, and this achieves the effect of signal amplification. Similarly, since the top electrode(s) and the bottom electrode(s) of the at least a part of the second capacitors (e.g., C.sub.2_1 in FIG. 2) receive the second input signal V.sub.IN and the first input signal Yip in the sample phase respectively, the signal strength of a signal sampled by the at least a part of the second capacitors is two times the signal strength of the second input signal V.sub.IN (i.e., V.sub.IN−V.sub.IP=V.sub.IN+V.sub.IN=2V.sub.IN) when the common-mode voltage is the ground voltage, and this achieves the effect of signal amplification.

[0024] Please refer to FIGS. 2˜3. The first capacitors are composed of the aforementioned at least a part of the first capacitors (e.g., C.sub.1_1 in FIG. 2) and a remaining part of the first capacitors (e.g., C.sub.1_2, C.sub.1_3, . . . , C.sub.1_(N-1), and C.sub.1_N in FIGS. 2˜3); all the bottom electrode(s) of the remaining part of the first capacitors receive(s) a corresponding part of the first group of reference signals REF.sub.SET1 through the first set of switches 130 in the sample phase. Similarly, the second capacitors are composed of the at least a part of the second capacitors (e.g., C.sub.2_1 in FIG. 2) and a remaining part of the second capacitors (e.g., C.sub.2_2, C.sub.2_3, . . . , C.sub.2_(N-1), and C.sub.2_N in FIGS. 2˜3); all the bottom electrode(s) of the remaining part of the second capacitors receive(s) a corresponding part of the second group of reference signals REF.sub.SET2 through the second set of switches 160 in the sample phase. It should be noted that the capacitance of each of the first/second capacitors is determined according to the demand for implementation. For example, the capacitance of the at least a part of the first/second capacitors (e.g., C.sub.1_1 or C.sub.2_1 in FIG. 2) is not less than the capacitance of the remaining part of the first/second capacitors (e.g., C.sub.1_2, C.sub.1_3, . . . , C.sub.1_(N-1), and C.sub.1_N in FIG. 2˜3, or C.sub.2_2, C.sub.2_3, . . . , C.sub.2_(N-1), and C.sub.2_N in FIGS. 2˜3). For another example, the capacitance of each of the first/second capacitors is designed according to the requirements of an SAR ADC.

[0025] Please refer to FIGS. 1˜3. In an exemplary implementation, the first input signal V.sub.IP is equivalent to (V.sub.CM+dV) and the second input signal YIN is equivalent to (V.sub.CM−dV), wherein “V.sub.CM” is a common-mode voltage and “dV” is a signal voltage. The ratio of the capacitance of the at least a part of the first capacitors (e.g., C.sub.1_1 in FIG. 2) to the capacitance of the remaining part of the first capacitors (e.g., C.sub.1_2, C.sub.1_3, . . . , C.sub.1_(N-1), and C.sub.1_N in FIGS. 2˜3 in FIGS. 2˜3) is

[00001]$\frac{x\times C_U}{y\times C_U}=\frac{x}{y},$

[0026] wherein C.sub.U denotes a unit of capacitance. In the sample phase, all the bottom electrode(s) of the remaining part of the first capacitors receive(s) a reference voltage V.sub.R, and thus the charge stored in the first capacitors can be measured with the following equation (1):

Q=(xC.sub.U)(V.sub.IP−V.sub.IN)+(yC.sub.U)(V.sub.IP−V.sub.R)=(xC.sub.U)(2dV)+(yC.sub.U)(V.sub.CM+dV−V.sub.R)=(xC.sub.U)(2dV)+(yC.sub.U)V.sub.CM+(yC.sub.U)dV−(yC.sub.U)V.sub.R=(2xC.sub.U+yC.sub.U)dV+(yC.sub.U)(V.sub.CM−V.sub.R)   eq. (1)

In the hold phase, the voltage at the top electrodes of the first capacitors is the aforementioned first sample voltage V.sub.XP, the bottom electrode(s) of the at least a part of the first capacitors receive(s) a ground voltage GND, and the bottom electrode(s) of the remaining part of the first capacitors receive(s) the reference voltage V.sub.R. Accordingly, the charge stored in the first capacitors in the hold phase can be measured with the following equation (2):

Q=(xC.sub.U)(V.sub.XP−0)+(yC.sub.U)(V.sub.XP−V.sub.R)=(x+y)C.sub.UV.sub.XP−yC.sub.UV.sub.R  eq. (2)

According to the law of charge conservation, eq. (1) should be equal to eq. (2). Accordingly, the first sample voltage V.sub.XP can be expressed with the following equation:

[00002]$\begin{array}{cc}{V}_{\mathrm{XP}}=\frac{\left(2x+y\right)\mathrm{dV}+y\left(V_{\mathrm{CM}}-V_R\right)}{x+y}+\frac{y}{x+y}{V}_R& \mathrm{eq}.\left(3\right)\end{array}$

If the aforementioned ratio

[00003]$\frac{x}{y}$

is equal to 1 (i.e., x=y), the first sample voltage V.sub.XP can be expressed with the following equation:

[00004]$\begin{array}{cc}{V}_{\mathrm{XP}}=\frac{\left(2+1\right)\mathrm{dV}+\left(V_{\mathrm{CM}}-V_R\right)}{2}+0.5V_R=1.5\mathrm{dV}+0.5V_{\mathrm{CM}}& \mathrm{eq}.\left(4\right)\end{array}$

Assuming that the common-mode voltage is 0.5V and the reference voltage V.sub.R is 1.1V, the first sample voltage V.sub.XP in eq. (4) will be

[00005]$“\frac{\left(2+1\right)\mathrm{dV}+\left(0.5V-1.1V\right)}{2}+0.5\times 1.1V=1.5\mathrm{dV}-0.3V+0.55V=1.5\mathrm{dV}+0.25V=1.5\mathrm{dV}+0.25V”.$

Compared with the first sample voltage V.sub.XP in eq. (4), the first sample voltage obtained with a prior art is lower. For example, according to a prior art in the similar circumstance (i.e., V.sub.IP=V.sub.CM+dV; x=y; V.sub.CM=0.5V; V.sub.R=1.1V), the bottom electrode(s) of the at least a part of the first capacitors receive(s) the reference voltage V.sub.R instead of the second input signal V.sub.IN in the sample phase, and the charge stored in the first capacitors is Q.sub.1=(xC.sub.U)(V.sub.IP−V.sub.R)+(yC.sub.U)(V.sub.IP−V.sub.R)=(x+y)×C.sub.U×(V.sub.IP−V.sub.R); the bottom electrode(s) of the at least a part of the first capacitors receive(s) the ground voltage GND and the bottom electrode(s) of the remaining part of the first capacitors receive(s) the reference voltage V.sub.R in the hold phase, and the charge stored in the first capacitors is Q.sub.2=(xC.sub.U)(V.sub.XP−0) (yC.sub.U)(V.sub.XP−V.sub.R)=(x+y)C.sub.UV.sub.XP−yC.sub.UV.sub.R; since Q.sub.1 is equal to Q.sub.2 under the law of charge conservation, the first sample voltage of the prior art is “dV−0.05V”. In light of the above, the first sample voltage V.sub.XP of the present invention (e.g., 1.5 dV+0.25V) is higher than the first sample voltage of the prior art (e.g., dV−0.05V), which proves the effect of signal amplification of the present invention significant.

[0027] Since those having ordinary skill in the art can appreciate how to derive the second sample voltage V.sub.XN according the description of the calculation of the first sample voltage V.sub.XP, repeated and redundant description is omitted here.

[0028] FIG. 4A shows another embodiment of the sample and hold circuit of the present disclosure. In comparison with the embodiment of FIG. 1, the bottom electrodes of all the first/second capacitors in the first/second capacitor array 410/420 receive the second/first input signal V.sub.IN/V.sub.IP in the sample phase, and therefore the first/second capacitor array 410/420 can store more charge; consequently, the effect of signal amplification can be improved further. FIG. 4B shows a modification of the embodiment of FIG. 4A. Compared with FIG. 4A, the bottom electrodes of the first/second capacitor array 410/420 of FIG. 4B receive the second/first input signal V.sub.IN/V.sub.IP through the same terminal instead of separate terminals.

[0029] In an alternative embodiment, the first input signal Yip is a signal voltage and the second input signal V.sub.IN is a constant voltage, wherein the signal voltage usually varies with time. In an alternative embodiment, the first input signal Yip and the second input signal V.sub.IN are complementary signals of a pair of differential signals, the bottom electrode(s) of the at least a part of the first/second capacitors receive(s) a first/second reference signal in the sample phase, and the first reference signal is different from the second reference signal. For example, the first/second reference signal is X times the second/first input signal, wherein “X” is a positive integer.

[0030] FIG. 5 shows an embodiment of the sample and hold method of the present disclosure, including the following steps: [0031] S510: receiving a first input signal with top electrodes of first capacitors in a sample phase, and receiving a second input signal with all bottom electrode(s) of at least a part of the first capacitors in the sample phase; [0032] S520: stopping receiving the first input signal with the top electrodes of the first capacitors in a hold phase, and receiving a first group of reference signals with all bottom electrodes of the first capacitors in the hold phase, and providing a first sample voltage on the top electrodes of the first capacitors by charge redistribution in the hold phase; [0033] S530: receiving the second input signal with top electrodes of second capacitors in the sample phase, and receiving the first input signal with all bottom electrode(s) of at least a part of the second capacitors in the sample phase; and [0034] S540: stopping receiving the second input signal with the top electrodes of the second capacitors in the hold phase, and receiving a second group of reference signals with all bottom electrodes of the second capacitors in the hold phase, and providing a second sample voltage on the top electrodes of the second capacitors by charge redistribution in the hold phase.

[0035] FIG. 6 shows an embodiment of the sample and hold method of the present disclosure, including the following steps: [0036] S610: receiving a first input signal with top electrodes of first capacitors in a sample phase, and receiving a first reference signal with all bottom electrode(s) of at least a part of the first capacitors in the sample phase; [0037] S620: stopping receiving the first input signal with the top electrodes of the first capacitors in a hold phase, and receiving a first group of reference signals with all bottom electrodes of the first capacitors in the hold phase, and providing a first sample voltage on the top electrodes of the first capacitors by charge redistribution in the hold phase; [0038] S630: receiving a second input signal with top electrodes of second capacitors in the sample phase, and receiving a second reference signal with all bottom electrode(s) of at least a part of the second capacitors in the sample phase, wherein the second reference signal is different from the first reference signal; and [0039] S640: stopping receiving the second input signal with the top electrodes of the second capacitors in the hold phase, and receiving a second group of reference signals with all bottom electrodes of the second capacitors in the hold phase, and providing a second sample voltage on the top electrodes of the second capacitors by charge redistribution in the hold phase.

[0040] Since those of ordinary skill in the art can appreciate the detail and the modification of the embodiments of FIGS. 5˜6 by referring to the disclosure of the embodiments of FIGS. 1˜4, which implies that some or all of the features of the embodiments of FIGS. 1˜4 can be applied to the embodiments of FIGS. 5˜6 in a logical way, repeated and redundant description is omitted here. It should be noted that the steps in FIG. 5/6 are not limited to a specific order, if practicable.

[0041] It should be noted that people of ordinary skill in the art can selectively use some or all of the features of any embodiment in this specification or selectively use some or all of the features of multiple embodiments in this specification to implement the present invention as long as such implementation is practicable; in other words, the present invention can be carried out flexibly in accordance with the present disclosure.

[0042] To sum up, the sample and hold circuit and method of the present disclosure can amplify an input signal in a cost-effective way.

[0043] The aforementioned descriptions represent merely the preferred embodiments of the present invention, without any intention to limit the scope of the present invention thereto. Various equivalent changes, alterations, or modifications based on the claims of the present invention are all consequently viewed as being embraced by the scope of the present invention.