CALIBRATION DEVICE

Abstract

A calibration device includes a signal generator and a processor. The signal generator is configured to provide an input signal to a filter circuit, wherein the filter circuit has a real time constant and is configured to receive the input signal to output an output signal. The processor is configured to calculate a real gain according to the output signal and the input signal, compare the real gain with a target gain to obtain a comparison result and determine whether to adjust the real time constant of the filter circuit according to the comparison result. The present disclosure also provides a calibration method.

Claims

1. A calibration device, comprising: a signal generator configured to provide an input signal to a filter circuit, wherein the filter circuit has a real time constant and is configured to receive the input signal to output an output signal; and a processor configured to calculate a real gain according to the output signal and the input signal, compare the real gain with a target gain to obtain a comparison result and determine whether to adjust the real time constant of the filter circuit according to the comparison result.

2. The calibration device of claim 1, wherein when the comparison result shows that the real gain does not equal the target gain, the processor adjusts the real time constant of the filter circuit.

3. The calibration device of claim 2, wherein the processor adjusts the real time constant of the filter circuit, so as to adjust the real gain.

4. The calibration device of claim 2, wherein the processor adjusts the capacitance of at least one capacitor of the filter circuit or the resistance of at least one resistor of the filter circuit through a digital algorithm, so as to adjust the real time constant of the filter circuit.

5. The calibration device of claim 4, wherein the digital algorithm is a binary search algorithm.

6. The calibration device of claim 1, wherein when the comparison result shows that the real gain equals the target gain, the processor does not adjust the real time constant of the filter circuit.

7. The calibration device of claim 6, wherein the filter circuit is designed to have a predetermined time constant and a predetermined center frequency and has the target gain at the predetermined center frequency; when the comparison result shows that the real gain equals the target gain, the real time constant of the filter circuit equals the predetermined time constant.

8. The calibration device of claim 7, wherein a frequency of the input signal equals the predetermined center frequency of the filter circuit.

9. The calibration device of claim 1, wherein the filter circuit is a complex band-pass filter; the input signal comprises a first differential input signal and a second differential input signal with a 90 degrees difference in phase.

10. The calibration device of claim 1, wherein the signal generator comprises a crystal oscillator and a low-pass filter.

11. A calibration method, comprising: providing an input signal to a filter circuit, wherein the filter circuit has a real time constant; receiving an output signal outputted by the filter circuit; calculating a real gain according to the output signal and the input signal; comparing the real gain with a target gain to obtain a comparison result; and determining whether to adjust the real time constant of the filter circuit according to the comparison result.

12. The calibration method of claim 11, wherein the step of determining whether to adjust the real time constant of the filter circuit according to the comparison result comprises: when the comparison result shows that the real gain does not equal the target gain, adjusting the real time constant of the filter circuit.

13. The calibration method of claim 12, wherein the real time constant of the filter circuit is adjusted, so as to adjust the real gain.

14. The calibration method of claim 12, wherein the step of adjusting the real time constant of the filter circuit comprises: adjusting the capacitance of at least one capacitor of the filter circuit or the resistance of at least one resistor of the filter circuit through a digital algorithm.

15. The calibration method of claim 14, wherein the digital algorithm is a binary search algorithm.

16. The calibration method of claim 11, wherein the step of determining whether to adjust the real time constant of the filter circuit according to the comparison result comprises: when the comparison result shows that the real gain equals the target gain, not adjusting the real time constant of the filter circuit.

17. The calibration method of claim 16, wherein the filter circuit is designed to have a predetermined time constant and a predetermined center frequency and has the target gain at the predetermined center frequency; when the comparison result shows that the real gain equals the target gain, the real time constant of the filter circuit equals the predetermined time constant.

18. The calibration method of claim 17, wherein a frequency of the input signal equals the predetermined center frequency of the filter circuit.

19. The calibration method of claim 11, wherein the filter circuit is a complex band-pass filter.

20. The calibration method of claim 19, wherein the input signal comprises a first differential input signal and a second differential input signal with a 90 degrees difference in phase.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] FIG. 1 is a block diagram of a calibration device depicted according to some embodiments of the present disclosure;

[0008] FIG. 2A is a schematic diagram of the frequency response of a filter circuit, which is affected by a manufacturing process variation, depicted according to some embodiments of the present disclosure;

[0009] FIG. 2B is a schematic diagram of the frequency response of the filter circuit, which is affected by a manufacturing process variation, after calibration depicted according to some embodiments of the present disclosure;

[0010] FIG. 3 is a schematic diagram of the frequency response of another filter circuit, which is affected by a manufacturing process variation, depicted according to some embodiments of the present disclosure;

[0011] FIG. 4 is a schematic diagram of a filter circuit depicted according to some embodiments of the present disclosure; and

[0012] FIG. 5 is a flow diagram of a calibration method depicted according to some embodiments of the present disclosure.

DETAILED DESCRIPTION

[0013] The embodiments are described in detail below with reference to the appended drawings to better understand the aspects of the present disclosure. However, the provided embodiments are not intended to limit the scope of the disclosure, and the description of the structural operation is not intended to limit the order in which they are performed. Any device that has been recombined by components and produces an equivalent function is within the scope covered by the disclosure.

[0014] The terms used in the entire specification and the scope of the patent application, unless otherwise specified, generally have the ordinary meaning of each term used in the field, the content disclosed herein, and the particular content.

[0015] The terms “coupled” or “connected” as used herein may mean that two or more elements are directly in physical or electrical contact, or are indirectly in physical or electrical contact with each other. It can also mean that two or more elements interact with each other.

[0016] Referring to FIG. 1, an embodiment of the present disclosure relates to a calibration device 100. The calibration device 100 includes a signal generator 102 and a processor 104 and is configured to calibrate a filter circuit 10 which is affected by a manufacturing process variation.

[0017] In the present embodiment, the filter circuit 10 can be a band-pass filter and is designed to have a predetermined center frequency f.sub.0 and a predetermined time constant τ.sub.0 corresponding to the predetermined center frequency f.sub.0. However, there is the difference between the time constant of the filter circuit and the originally designed value by the effect of the manufacturing process variation, so that the bandwidth and the center frequency of the filter circuit 10 are also differed from the originally designed values. For example, the filter circuit 10, which is affected by the manufacturing process variation, has a real time constant τ.sub.1 different from the predetermined time constant τ.sub.0 and a real center frequency f.sub.1 different from the predetermined center frequency f.sub.0.

[0018] In structure, the signal generator 102 is coupled to the filter circuit 10. The processor 104 is coupled to the signal generator 102 and the filter circuit 10. In the present embodiment, the signal generator 102 can include a crystal oscillator (not shown) and a low-pass filter (not shown), and the processor 104 can be a central processing unit or a calculator chip.

[0019] For better understanding the present application, the operation of the calibration device 100 would be discussed in the following paragraphs with reference made to the accompanying drawings. As shown in FIG. 1, the signal generator 102 provides an input signal V.sub.IN to the filter circuit 10 according to a command (not shown) from the processor 104. A frequency of the input signal V.sub.IN equals the predetermined center frequency f.sub.0, which is originally designed, of the filter circuit 10.

[0020] The filter circuit 10 receives the input signal V.sub.IN, so as to output an output signal V.sub.OUT to the processor 104. The processor 104 receives the output signal V.sub.OUT and calculates a real gain gm.sub.r according to the output signal V.sub.OUT and the input signal V.sub.IN. Specifically, the processor 104 divides the output signal V.sub.OUT by the input signal V.sub.IN to generate a ratio and uses the absolute value of the ratio as the real gain gm.sub.r.

[0021] In the present embodiment, the filter circuit 10 has a target gain gm.sub.0 at the predetermined center frequency f.sub.0 which is originally designed. It is understood that the target gain gm0 is the maximum gain that the filter circuit 10 should have at the predetermined center frequency f.sub.0 which is originally designed. In an example of practical application, the gain that the filter circuit 10 is designed to have at 300 MHz (that is, the predetermined center frequency f.sub.0) is 1.5 (that is, the target gain gm.sub.0). That is to say, when the frequency of the input signal V.sub.IN is 300 MHz, the strength of the output signal V.sub.OUT at 300 MHz should be 1.5 times of those of the input signal V.sub.IN ideally.

[0022] However, the filter circuit 10 which is affected by the manufacturing process variation has the real center frequency f.sub.1 different from the predetermined center frequency f.sub.0. That is to say, the maximum gain of the filter circuit 10 is altered to be at the real center frequency f.sub.1. If the input signal V.sub.IN having the predetermined center frequency f.sub.0 is inputted to the filter circuit 10, the real gain gm.sub.r calculated by the processor 104 would not be the maximum gain, which is originally designed, of the filter circuit 10. In the above-described example of practical application, the strength of the output signal V.sub.OUT at 300 MHz would fail to be 1.5 times of those of the input signal V.sub.IN. In other words, the real gain gm.sub.r is smaller than 1.5 (that is, the target gain gm.sub.0).

[0023] After the real gain gm.sub.r is calculated, the processor 104 is configured to compare the real gain gm.sub.r and the target gain gm.sub.0, so as to obtain a comparison result. In the ideal condition, the processor 104 obtains a result that the real gain gm.sub.r at the predetermined center frequency f0 equals the target gain gm.sub.0 by comparing the real gain gm.sub.r and the target gain gm.sub.0. However, if the filter circuit 10 is affected by the manufacturing process variation, the processor 104 would obtain a result that the real gain gm.sub.r at the predetermined center frequency f0 is not equal to the target gain gm.sub.0 by comparing the real gain gm.sub.r and the target gain gm.sub.0.

[0024] Accordingly, the processor 104 is further configured to determine whether to adjust the time constant of the filter circuit 10 according to the comparison result, so as to calibrate the frequency response of the filter circuit 10 to be the originally designed values.

[0025] Specifically, referring to FIG. 2A, in the present embodiment, the frequency response (shown as the broken lines) of the filter circuit 10 is affected by the manufacturing process variation, so that the real center frequency f.sub.1 is lower than the predetermined center frequency f.sub.0. As shown in FIG. 2A, the processor 104 compares the real gain gm.sub.r with the target gain gm.sub.0 and obtains the result that the real gain gm.sub.r is smaller than the target gain gm.sub.0. In the above-described example of practical application, the real center frequency f.sub.1 can be 100 MHz that is lower than 300 MHz, and the real gain gm.sub.r can be 0.75 that is smaller than 1.5. When the real gain gm.sub.r is smaller than the target gain gm.sub.0, the processor 104 is configured to adjust the capacitance of at least one capacitor (not shown) of the filter circuit 10 (or the resistance of at least one resistor (not shown) of the filter circuit 10) to adjust the real time constant τ.sub.1 of the filter circuit 10, so as to change the real center frequency f.sub.1 and the real gain gm.sub.r of the filter circuit 10.

[0026] After multiple comparisons and adjustments, the real gain gm.sub.r would gradually approach the target gain gm.sub.0. For example, the processor 104 can digitally adjust the capacitance of the at least one capacitor from 64 farads to 32, 16, 8 and 4 farads in order. As the capacitance of the at least one capacitor is gradually decreased, the real center frequency f.sub.1 and the real gain gm.sub.r of the filter circuit 10 are gradually increased. In the above-described example of practical application, as the capacitance of the at least one capacitor is gradually decreased, the real center frequency f.sub.1 can be gradually increased from 100 MHz to 300 MHz, and the real gain gm.sub.r at the predetermined center frequency f.sub.0 can be gradually increased from 0.75 to 1.5.

[0027] Referring to FIG. 2B then, when the processor 104 compares the real gain gm.sub.r with the target gain gm.sub.0 and obtains the result that the real gain gm.sub.r equals the target gain gm.sub.0, the processor 104 no longer adjusts the real time constant τ.sub.1 of the filter circuit 10. The real time constant τ.sub.1 and the real center frequency f.sub.1 of the filter circuit 10 being calibrated would equal the predetermined time constant τ.sub.0 and the predetermined center frequency f.sub.0 which are originally designed. In the above-described example of practical application, after the filter circuit 10 is calibrated, the real center frequency f.sub.1 can be 300 MHz, and the real gain gm.sub.r at the predetermined center frequency f.sub.0 can be 1.5. It is worth noting that the capacitance of the at least one capacitor has the value that is required for the filter circuit 10 affected by the manufacturing process variation.

[0028] Referring to FIG. 3, in other some embodiments, the frequency response (shown as the broken lines) of the filter circuit 10 is affected by the manufacturing process variation, so that the real center frequency f.sub.1 is higher than the predetermined center frequency f.sub.0. The processor 104 compares the real gain gm.sub.r with the target gain gm.sub.0 and still obtains the result that the real gain gm.sub.r is smaller than the target gain gm.sub.0. In the above-described example of practical application, the real center frequency f.sub.1 can be 500 MHz that is higher than 300 MHz, and the real gain gm.sub.r can be 0.75 that is smaller than 1.5. Similarly, the processor 104 can digitally and gradually increase the capacitance of the at least one capacitor (for example, adjusts from 4 farads to 8, 16, 32 and 64 farads in order). Accordingly, the real center frequency f.sub.1 of the filter circuit 10 is gradually decreased, and the real gain gm.sub.r of the filter circuit 10 is gradually increased. In the above-described example of practical application, as the capacitance of the at least one capacitor is gradually increased, the real center frequency f.sub.1 are gradually decreased from 500 MHz to 300 MHz, and the real gain gm.sub.r at the predetermined center frequency f.sub.0 is gradually increased from 0.75 to 1.5. Then, when the processor 104 obtains the result that the real gain gm.sub.r equals the target gain gm.sub.0 (as shown in FIG. 2B), the processor 104 no longer adjusts the real time constant τ.sub.1 of the filter circuit 10. The capacitance of the at least one capacitor has the value that is required for the filter circuit 10 affected by the manufacturing process variation.

[0029] In other some embodiments, the processor 104 can adjust the capacitance of the at least one capacitor by a digital algorithm (e.g. binary search algorithm).

[0030] Referring to FIG. 4, in other some embodiments, the filter circuit 10 can be a complex band-pass filter and includes a plurality of amplifiers A, a plurality of resistors R and a plurality of capacitors C. In the filter circuit 10 as shown in FIG. 4, the input signal V.sub.IN generated by the signal generator 102 includes a first differential input signal (including a first input signal I.sub.in.sup.+ and a second input signal I.sub.in.sup.−) and a second differential input signal (including a third input signal Q.sub.in.sup.+ and a fourth input signal Q.sub.in.sup.−˜), wherein the first differential input signal and the second differential input signal have a 90 degrees difference in phase. In addition, the output signal V.sub.OUT outputted by the filter circuit 10 includes a first differential output signal (including a first output signal I.sub.out.sup.+ and a second output signal I.sub.out.sup.−) and a second differential output signal (including a third output signal Q.sub.out.sup.+ and a fourth output signal Q.sub.out.sup.−). The description that the calibration device 100 calibrates the filter circuit 10 as shown in FIG. 4 is similar to those of the above-described embodiments and therefore is omitted.

[0031] Referring to FIG. 5, FIG. 5 depicts a flow diagram of the calibration method 200 in accordance with one embodiment of the present disclosure. The calibration method 200 can be executed by the calibration device 100 as shown in FIG. 1.

[0032] In the step S210, the input signal V.sub.IN is provided by the signal generator 102 to the filter circuit 10 affected by the manufacturing process variation, wherein the filter circuit 10 has a real time constant τ.sub.1. In the step S220, the output signal V.sub.OUT outputted by the filter circuit 10 is received by the processor 104. In the step S230, the real gain gm.sub.r is calculated by the processor 104 according to the input signal V.sub.IN and the output signal V.sub.OUT.

[0033] In the steps S240-S260, the real gain gm.sub.r and the target gain gm.sub.0 (that is, the maximum gain that the filter circuit 10 should have at the predetermined center frequency f.sub.0 which is originally designed) are compared to obtain a comparison result, so as to determine whether to adjust the real time constant τ.sub.1 of the filter circuit 10 according to the comparison result. Specifically, in the step S240, the real gain gm.sub.r is compared with the target gain gm.sub.0 to determine whether the real gain gm.sub.r equals the target gain gm.sub.0. If the comparison result shows “no”, the step S250 is executed so as to adjust the real time constant τ.sub.1 of the filter circuit 10.

[0034] After the real time constant τ.sub.1 of the filter circuit 10 is adjusted, the procedure returns to the step S210. The input signal V.sub.IN is provided to the filter circuit 10 which has been adjusted, so as to execute the steps S220-S240 again. In brief, if the result that the real gain gm.sub.r does not equal the target gain gm.sub.0 is obtained in the step S240, the step S250 is executed to adjust the real time constant τ.sub.1 of the filter circuit 10, and the steps S210-S240 are executed again.

[0035] If the comparison result in the step S240 shows “yes”, the step S260 is executed to not adjust the real time constant τ.sub.1 of the filter circuit 10 (at this time, the real time constant τ.sub.1 equals the predetermined time constant τ.sub.0, which is originally designed, of the filter circuit 10). Accordingly, the calibration method 200 is ended.

[0036] In sum, the calibration device 100 and the calibration method 200 of the present disclosure adjust the filter circuit 10 by comparing the real gain gm.sub.r of the filter circuit 10 with the target gain gm.sub.0 directly, so as to compensate a variety of components (e.g. resistor, capacitor, operation amplifier) of the filter circuit 10 for the deviations generated by the manufacturing process variation. In such way, the filter circuit 10 can be calibrated to have the originally designed values (that is, the predetermined center frequency f.sub.0, the predetermined time constant τ.sub.0 and the target gain gm.sub.0), so as to facilitate the demodulation of signals.

[0037] Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein. It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims.