METHOD AND APPARATUS TO USE EMBEDDED PATTERNS AND S-PARAMETERS OF A SMALL PHASED ARRAY TO BUILD LARGE PHASED ARRAYS

Abstract

To model a phased array antenna having a target array of antenna elements, a small array of antenna elements is selected that has fewer antenna elements than the target array. For each antenna element of the small array of antenna elements, far field patterns are captured for a plurality of signal frequencies. S-parameters for the small array of antenna elements are captured for the plurality of signal frequencies. The far field patterns captured for the antenna elements of the small array are mapped to antenna elements of the target array of antenna elements. The S-parameters captured for the small array are mapped to the target array.

Claims

1. A method for manufacturing a phased array antenna, comprising: designing a proposed phased array antenna having a target array of antenna elements; modeling the proposed phased array antenna, including: selecting a small array of antenna elements wherein the small array has fewer antenna elements than the target array, for each antenna element of the small array of antenna elements, capturing far field patterns for a plurality of signal frequencies, capturing S-parameters for the small array of antenna elements for the plurality of signal frequencies, where each antenna element in the small array is regarded as a port when capturing the S-parameters for the small array, mapping the far field patterns captured for the antenna elements of the small array to antenna elements of the target array of antenna elements, and mapping the S-parameters captured for the small array to the target array, where each antenna element in the target array is regarded as a port when mapping the S-parameters to the target array; and upon obtaining satisfactory results from modeling the proposed phased array antenna, physically building the proposed phased array antenna.

2. A method as in claim 1 wherein mapping the far field patterns captured for the antenna elements of the small array to antenna elements of the target array of antenna elements includes: mapping far field patterns for corner antenna elements of the small array directly to corresponding corner antenna elements of the target array; and mapping far field patterns of the antenna elements along outside edges of the small array to antenna elements along corresponding outside edges of the target array, including: along each edge starting from corners of the edge, mapping far field patterns for each antenna element of the edge of the small array only once into a corresponding antenna element of the corresponding edge of the target array, except for a middle antenna element of the edge of the small array which is mapped into all remaining antenna elements of the corresponding edge of the target array.

3. A method as in claim 1 wherein mapping the far field patterns captured for the antenna elements of the small array to antenna elements of the target array of antenna elements includes: mapping far field patterns for corner antenna elements of the small array directly to corresponding corner antenna elements of the target array; mapping far field patterns of the antenna elements along outside edges of the small array to antenna elements along corresponding outside edges of the target array, including: along each edge of the target array, starting from corners of the edge, mapping far field patterns for each antenna element of the edge of the small array only once into a corresponding antenna element of a corresponding edge of the target array, except for a middle antenna element of the edge of the small array which is mapped into all remaining antenna elements of the corresponding edge of the target array; and mapping far field patterns of the antenna elements in rows of the small array to antenna elements in rows of the target array, including: along each row of the target array, mapping far field patterns for each antenna element of the row of the small array only once into a corresponding antenna element of the corresponding row of the target array, except for a middle antenna element of the row of the small array which is mapped into all remaining antenna elements of the corresponding row of the target array, wherein each row of the target array corresponds to a row of the small array when end row antenna elements from the small array have already been mapped into row end antenna elements of the corresponding target array.

4. A method as in claim 1 wherein mapping the far field patterns captured for the antenna elements of the small array to antenna elements of the target array of antenna elements includes: mapping far field patterns for corner antenna elements of the small array directly to corresponding corner antenna elements of the target array; mapping far field patterns of the antenna elements along outside edges of the small array to antenna elements along corresponding outside edges of the target array, including: along each edge of the target array, starting from corners of the edge, mapping far field patterns for each antenna element of the edge of the small array only once into a corresponding antenna element of a corresponding edge of the target array, except for a middle antenna element of the edge of the small array which is mapped into all remaining antenna elements of the corresponding edge of the target array; and mapping far field patterns of the antenna elements in columns of the small array to antenna elements in columns of the target array, including: along each column of the target array, mapping far field patterns for each antenna element of the column of the small array only once into a corresponding antenna element of the corresponding column of the target array, except for a middle antenna element of the column of the small array which is mapped into all remaining antenna elements of the corresponding column of the target array, wherein each column of the target array corresponds to a column of the small array when end column antenna elements from the small array have already been mapped into column end antenna elements of the corresponding target array.

5. A method as in claim 1 wherein mapping the S-parameters captured for the small array to the target array includes: for each port of the target array, laying the small array over the target array so that the port of the target array is aligned with a corresponding port of the small array and performing the following; copying two-port S-parameters for the corresponding port (as a first port for the two-port S-parameter) of the small array and each of the ports (as a second port for the two-port S-parameter) of the small array as S-parameters for the target array where the small array overlays the target array, and using a zero or another minimal value for two-port S-parameter values for the corresponding port (as a first port for the two-port S-parameter) and each of the ports (as a second port for the two-port S-parameter) of the target array where the small array does not overlay the target array.

6. A method as in claim 5 wherein the port of the target array is aligned with the corresponding port of the small array in accordance with the following: aligning corner ports of the small array directly to corresponding corner ports of the target array; and aligning ports along outside edges of the small array to ports along corresponding outside edges of the target array, including: along each edge starting from corners of the edge, aligning each port of the edge of the small array only once into a corresponding port of the corresponding edge of the target array, except for a middle port of the edge of the small array which is aligned into all remaining ports of the corresponding edge of the target array.

7. A method as in claim 5 wherein the port of the target array is aligned with the corresponding port of the small array in accordance with the following: aligning corner ports of the small array directly to corresponding corner ports of the target array; aligning ports along outside edges of the small array to ports along corresponding outside edges of the target array, including: along each edge starting from corners of the edge, aligning each port of the edge of the small array only once into a corresponding port of the corresponding edge of the target array, except for a middle port of the edge of the small array which is aligned into all remaining ports of the corresponding edge of the target array; and aligning ports in rows of the small array to ports in corresponding rows of the target array, including: along each row of the target array, aligning each port of the row of the small array only once into a corresponding port of the corresponding row of the target array, except for a middle port of the row of the small array which is aligned into all remaining ports of the corresponding row of the target array, wherein each row of the target array corresponds to a row of the small array when end row ports from the small array have already been mapped into row end ports of the corresponding target array.

8. A method as in claim 5 wherein the port of the target array is aligned with the corresponding port of the small array in accordance with the following: aligning corner ports of the small array directly to corresponding corner ports of the target array; aligning ports along outside edges of the small array to ports along corresponding outside edges of the target array, including: along each edge starting from corners of the edge, aligning each port of the edge of the small array only once into a corresponding port of the corresponding edge of the target array, except for a middle port of the edge of the small array which is aligned into all remaining ports of the corresponding edge of the target array; and aligning ports in columns of the small array to ports in corresponding columns of the target array, including: along each column of the target array, aligning each port of the column of the small array only once into a corresponding port of the corresponding column of the target array, except for a middle port of the column of the small array which is mapped into all remaining ports of the corresponding column of the target array, wherein each column of the target array corresponds to a column of the small array when end column ports from the small array have already been mapped into column end ports of the corresponding target array.

9. A method as in claim 5 wherein each port of the target array is aligned with the corresponding port of the small array so that a middle of the small array is aligned over the port and if any of the ports of the small array are located outside edges of the target array, a location of the small array is shifted until the small array is completely within the large array.

10. A method as in claim 1 wherein the small array has an odd number of rows and an odd number of columns.

11. A method for modeling a phased array antenna having a target array of antenna elements, comprising: selecting a small array of antenna elements wherein the small array has fewer antenna elements than the target array; for each antenna element of the small array of antenna elements, capturing far field patterns for a plurality of signal frequencies; capturing S-parameters for the small array of antenna elements for the plurality of signal frequencies, where each antenna element in the small array is regarded as a port when capturing the S-parameters for the small array; mapping the far field patterns captured for the antenna elements of the small array to antenna elements of the target array of antenna elements; and mapping the S-parameters captured for the small array to the target array, where each antenna element in the target array is regarded as a port when mapping the S-parameters to the target array.

12. A method as in claim 11 wherein mapping the far field patterns captured for the antenna elements of the small array to antenna elements of the target array of antenna elements includes: mapping far field patterns for corner antenna elements of the small array directly to corresponding corner antenna elements of the target array; mapping far field patterns of the antenna elements along outside edges of the small array to antenna elements along corresponding outside edges of the target array, including: along each edge starting from corners of the edge, mapping far field patterns for each antenna element of the edge of the small array only once into a corresponding antenna element of the corresponding edge of the target array, except for a middle antenna element of the edge of the small array which is mapped into all remaining antenna elements of the corresponding edge of the target array.

13. A method as in claim 11 wherein mapping the far field patterns captured for the antenna elements of the small array to antenna elements of the target array of antenna elements includes: mapping far field patterns for corner antenna elements of the small array directly to corresponding corner antenna elements of the target array; mapping far field patterns of the antenna elements along outside edges of the small array to antenna elements along corresponding outside edges of the target array, including: along each edge of the target array, starting from corners of the edge, mapping far field patterns for each antenna element of the edge of the small array only once into a corresponding antenna element of a corresponding edge of the target array, except for a middle antenna element of the edge of the small array which is mapped into all remaining antenna elements of the corresponding edge of the target array; and mapping far field patterns of the antenna elements in rows of the small array to antenna elements in rows of the target array, including: along each row of the target array, mapping far field patterns for each antenna element of the row of the small array only once into a corresponding antenna element of the corresponding row of the target array, except for a middle antenna element of the row of the small array which is mapped into all remaining antenna elements of the corresponding row of the target array, wherein each row of the target array corresponds to a row of the small array when end row antenna elements from the small array have already been mapped into row end antenna elements of the corresponding target array.

14. A method as in claim 11 wherein mapping the far field patterns captured for the antenna elements of the small array to antenna elements of the target array of antenna elements includes: mapping far field patterns for corner antenna elements of the small array directly to corresponding corner antenna elements of the target array; mapping far field patterns of the antenna elements along outside edges of the small array to antenna elements along corresponding outside edges of the target array, including: along each edge of the target array, starting from corners of the edge, mapping far field patterns for each antenna element of the edge of the small array only once into a corresponding antenna element of a corresponding edge of the target array, except for a middle antenna element of the edge of the small array which is mapped into all remaining antenna elements of the corresponding edge of the target array; and mapping far field patterns of the antenna elements in columns of the small array to antenna elements in columns of the target array, including: along each column of the target array, mapping far field patterns for each antenna element of the column of the small array only once into a corresponding antenna element of the corresponding column of the target array, except for a middle antenna element of the column of the small array which is mapped into all remaining antenna elements of the corresponding column of the target array, wherein each column of the target array corresponds to a column of the small array when end column antenna elements from the small array have already been mapped into column end antenna elements of the corresponding target array.

15. A method as in claim 11 wherein mapping the S-parameters captured for the small array to the target array includes: for each port of the target array, laying the small array over the target array so that the port of the target array is aligned with a corresponding port of the small array and performing the following; copying two-port S-parameters for the corresponding port (as a first port for the two-port S-parameter) of the small array and each of the ports (as a second port for the two-port S-parameter) of the small array as S-parameters for the target array where the small array overlays the target array, and using a zero or another minimal value for two-port S-parameter values for the corresponding port, (as a first port for the two-port S-parameter) and each of the ports (as a second port for the two-port S-parameter) of the target array where the small array does not overlay the target array.

16. A method as in claim 15 wherein the port of the target array is aligned with the corresponding port of the small array in accordance with the following: aligning corner ports of the small array directly to corresponding corner ports of the target array; aligning ports along outside edges of the small array to ports along corresponding outside edges of the target array, including: along each edge starting from corners of the edge, aligning each port of the edge of the small array only once into a corresponding port of the corresponding edge of the target array, except for a middle port of the edge of the small array which is aligned into all remaining ports of the corresponding edge of the target array.

17. A method as in claim 15 wherein the port of the target array is aligned with the corresponding port of the small array in accordance with the following: aligning corner ports of the small array directly to corresponding corner ports of the target array; aligning ports along outside edges of the small array to ports along corresponding outside edges of the target array, including: along each edge starting from corners of the edge, aligning each port of the edge of the small array only once into a corresponding port of the corresponding edge of the target array, except for a middle port of the edge of the small array which is aligned into all remaining ports of the corresponding edge of the target array; and aligning ports in rows of the small array to ports in corresponding rows of the target array, including: along each row of the target array, aligning each port of the row of the small array only once into a corresponding port of the corresponding row of the target array, except for a middle port of the row of the small array which is aligned into all remaining ports of the corresponding row of the target array, wherein each row of the target array corresponds to a row of the small array when end row ports from the small array have already been mapped into row end ports of the corresponding target array.

18. A method as in claim 15 wherein the port of the target array is aligned with the corresponding port of the small array in accordance with the following: aligning corner ports of the small array directly to corresponding corner ports of the target array; aligning ports along outside edges of the small array to ports along corresponding outside edges of the target array, including: along each edge starting from corners of the edge, aligning each port of the edge of the small array only once into a corresponding port of the corresponding edge of the target array, except for a middle port of the edge of the small array which is aligned into all remaining ports of the corresponding edge of the target array; and aligning ports in columns of the small array to ports in corresponding columns of the target array, including: along each column of the target array, aligning each port of the column of the small array only once into a corresponding port of the corresponding column of the target array, except for a middle port of the column of the small array which is mapped into all remaining ports of the corresponding column of the target array, wherein each column of the target array corresponds to a column of the small array when end column ports from the small array have already been mapped into column end ports of the corresponding target array.

19. A method as in claim 15 wherein each port of the target array is aligned with the corresponding port of the small array so that a middle of the small array is aligned over the port and if any of the ports of the small array are located outside edges of the target array, a location of the small array is shifted until the small array is completely within the large array.

20. A method as in claim 11 wherein the small array has an odd number of rows and an odd number of columns.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] FIG. 1 is a simplified block diagram of a phased array antenna.

[0005] FIG. 2 is a flowchart illustrating a simplified manufacturing process, from design to production, of a phased array antenna.

[0006] FIG. 3 shows a simplified pattern of a phased array antenna to be manufactured.

[0007] FIG. 4 shows a pattern for a reduced-sized phased array antenna used to model performance of the phased array antenna shown in FIG. 3.

[0008] FIG. 5 is a flowchart illustrating a process utilized to model the phased array antenna shown in FIG. 3 based on an extrapolation of the modeling the phased array antenna shown in FIG. 4.

[0009] FIG. 6 shows a simplified pattern of a phased array antenna that illustrates the process shown in FIG. 5.

[0010] FIG. 7, FIG. 8 and FIG. 9 show highlighted sections illustrating selected ports of a phased array antenna to illustrate the process shown in FIG. 5

DETAILED DESCRIPTION

[0011] FIG. 1 is a simplified block diagram of a phased array antenna 10. Phased array antenna 10 is composed of an 8×8 array of antenna elements. In FIG. 1 the antenna elements are separated into four antenna tiles, each with a 4×4 array of antenna elements. For example, an antenna tile 11 has a 4×4 array of antenna elements 16. An antenna tile 12 has a 4×4 array of antenna elements 17. An antenna tile 13 has a 4×4 array of antenna elements 18. An antenna tile 14 has a 4×4 array of antenna elements 19.

[0012] While phased array antenna 10 has four antenna tiles of 16 antenna elements, phased array antennas can include hundreds or thousands or more antenna elements divided into any number of antenna tiles. Further, while FIG. 1 shows square antenna elements arranged on square tiles, antenna elements and antenna tiles can have any shape and any size depending on the antenna characteristics desired for a particular application. The small number, simple shapes and simple arrangements of antenna elements are shown in FIG. 1 to aid in describing operations that increase exponentially in complexity with the increasing number of antenna elements. This simplification of size and arrangement of phased array antenna 10 in FIG. 1 allows a full explanation of the principles of operation that can be applied by a person of ordinary skill of the art to phased array antennas of any size and shape.

[0013] FIG. 2 is a flowchart illustrating a simplified manufacturing process, from design to production, of phased array antenna 10. In a block 21 the process starts. In a block 22, phase array antenna 10 is designed. In a block 23, the design for phase array 10 is modeled and tested. A software tool such as Pathwave EM Design (EMPro) software is typically used in the modeling. Design and testing is typically an interactive process where after modeling, design changes are made and modeling is performed on the revised design. Eventually the projected performance of the design is sufficiently satisfactory to move onto prototyping for further testing. Block 24 represents the decision point where after modeling a design is approved for prototyping or where further design revisions are sought.

[0014] Fabrication block 25 represents the point where a prototype is built and tested. This can be an iterative process in that if the prototype does not perform satisfactorily further design revisions are required. Block 26 represents the decision point where after fabrication, a prototype is approved for manufacturing or where further design revisions are sought. Since fabrication is significantly more expensive than modeling, costs are effectively reduced where modeling can most accurately predict performance of prototypes thereby avoiding redesigning after the initial fabrication block 25, or at least minimizing the times the product must be prototyped.

[0015] When a prototype performs satisfactorily, in a block 27, the design is released for manufacture, and the product is manufactured and placed into service.

[0016] FIG. 3 shows an 8×8 array pattern 30 used in the modeling of phased array antenna 10. The antenna elements in array pattern 30 are numbered from 1 to 64.

[0017] FIG. 4 shows a 5×5 array 40 also used in the modeling of phased array antenna 10. The antenna elements in array pattern 40 are numbered from 1 to 25.

[0018] FIG. 5 is a flowchart illustrating a process utilized to model the phased array antenna 10 using the array pattern shown in FIG. 3 based on an extrapolation of the modeling of phased array antenna 40 shown in FIG. 4.

[0019] In a block 50, the process starts. In a block 51, for a phased array antenna of M rows and N columns arranged as an M×N array, where M and N are any integer number, a smaller phased array antenna of size m rows by n columns (where m and n are odd integers) arranged as an m×n array is constructed and simulated in an electromagnetic (EM) simulator. Each antenna element can be of any size or shape. A commercially available EM simulator such as Pathwave EM Design (EMPro) software can be used to simulate the performance of the phased array simulator.

[0020] For the example illustrated by FIG. 3 and FIG. 4, the phased array antenna is 8×8 and the smaller phased array antenna is 5×5. This is a simplified example, as the phased array antenna to be modeled can typically be 64×64 or larger which may require too many calculations and too much data to be directly modeled by a commercially available EM simulator.

[0021] In a block 52, the far field embedded patterns of all the m*n antenna elements are captured into individual files at all the desired frequencies. An embedded pattern of an element is one where only that element is excited while all other elements are terminated in a 50 ohm impedance. The locations of the antenna elements are also captured as X, Y, Z coordinates.

[0022] For the example illustrated by FIG. 3 and FIG. 4, this means that the far field patterns at all desired frequencies are captured for each of the twenty-five antenna elements of array 40. The locations of the antenna elements in twenty-five element array 40 are also captured as X, Y, Z coordinates.

[0023] Input to the EM simulator will typically include geometry of the antenna elements, arrangement of the antenna elements, spacing between the antenna elements, and properties of the materials from which the antenna elements are composed. The outputs from the EM simulator defining the far field patterns include, for example, energy distribution, noise, gain efficiency throughout three dimensional space and so on.

[0024] In a block 53, the S-parameters are captured from the EM simulator for the m×n array. Each antenna element of the m×n array is treated as a port for the purpose of calculating the S-parameters. The matrix of S-parameters will have (m*n)*(m*n)S-parameter values. For 5×5 array 40, for example, the matrix of S-parameters will have (5*5)*(5*5)=625 S-parameter values.

[0025] In a block 54, the far field patterns captured for the antenna elements of the small array are mapped to the antenna elements of the target array, as described below. Before the start of the mapping any additional phase included into the captured embedded pattern of each element is removed. After completion of the mapping the phase dependent on the location of the element pattern in the target array is added back while computing the overall target array far field pattern.

[0026] The far field patterns captured for the antenna elements at the four corners of the small array are mapped to the corner antenna elements of the target array.

[0027] The four outside edges of the small array are mapped to the four outside edges of the target array. For the mapping, starting from the corners, each of the far field pattern files for antenna elements along each edge of the small array is mapped only once into antenna elements along a corresponding edge of the target array, except for the far field pattern file for the middle antenna element of each edge of the small array, which is repeatedly mapped to all the remaining middle antenna elements of the corresponding edge of the target array.

[0028] Once far field patterns from antenna elements of the four outside edges of the small array are mapped to antenna elements of the four outside edges of the target array, antenna elements at the ends of each row of the target array will already have far field patterns from the small array mapped into them. For the remaining antenna elements in each row of the target array, the row of the small array that has the same far field pattern files at the ends of the row is used to map far field patterns files into the remaining antenna elements of the corresponding row of the target array.

[0029] For the mapping, starting from the ends of the row, each of the far field pattern files for the row for the small array is mapped only once into the corresponding row of the target array, except for the far field pattern file for the middle antenna element of the row, which is repeatedly mapped to all the remaining middle antenna elements of the corresponding row of the target array.

[0030] Instead of rows, columns can be used. Each column of the target array will have far field pattern files mapped from the small antenna for each of the ends of the column. For each column of the target array, the column of the small array that has the same far field pattern files at the ends of the column is used to map far field patterns files to that corresponding column of the target array. For the mapping, starting from the ends of the column, each of the far field pattern files for the column for the small array is mapped only once into the target array, except for the far field pattern file for the middle antenna element of the column of the small array, which is repeatedly mapped to all the remaining middle antenna elements of the column of the target array.

[0031] FIG. 6 represents the results of performing this mapping of the far field patterns captured for the antenna elements of small array 40 into the antenna elements of target array 60.

[0032] The far field patterns captured for the antenna elements at the four corners of small array 40 are mapped to the four corner antenna elements of target array 60. As shown in FIG. 60, array corners 1, 5, 21 and 25 of small array 40 have been mapped into the corners of target array 60.

[0033] The four outside edges of small array 40 are mapped to the four outside edges of target array 60. For the mapping, starting from the corners, each of the far field pattern files for small array 40 is mapped only once into target array 60, except for the far field pattern file for the middle antenna element of the edge, which is repeatedly mapped to all the remaining middle antenna elements of target array 60. As shown in FIG. 60, the top edge (1, 2, 3, 4, 5) of small array 40 has been mapped as (1, 2, 3, 3, 3, 3, 4, 5) into the antenna elements at the top of edge of target array 60. The left edge (1, 6, 11, 16, 21) of small array 40 has been mapped as (1, 6, 11, 11, 11, 11, 16, 21) into the antenna elements on the left of edge of target array 60. And so on.

[0034] Now each row of target array 60 will have far field pattern files mapped from the small antenna for each of the ends of the row. For each row of target array 60, the row of small array 40 that has the same far field pattern files at the ends of the row is used to map far field patterns files to that row of target array 60. For the mapping, starting from the ends of the row, each of the far field pattern files for the row for small array 40 is mapped only once into target array 60, except for the far field pattern file for the middle antenna element of the row, which is repeatedly mapped to all the remaining middle antenna elements of the row of target array 60. For example, as shown in in FIG. 60, the row (6, 7, 8, 9, 10) of small array 40 has been mapped as (6, 7, 8, 8, 8, 8, 9, 10) in target array 60. Likewise, the row (16, 17, 18, 19, 20) of small array 40 has been mapped as (16, 17, 18, 18, 18, 18, 19, 20) in target array 60. The row (11, 12, 13, 14, 15) of small array 40 has been mapped into several rows in target array 60 as (11, 12, 13, 13, 13, 13, 14, 15).

[0035] Likewise, for each column of target array 60, the column of small array 40 that has the same far field pattern files at the ends of the column to a column of target array 60. For the mapping, starting from the ends of the column, each of the far field pattern files for the column for small array 40 is mapped only once into target array 60, except for the far field pattern file for the middle antenna element of the column, which is repeatedly mapped to all the remaining middle antenna elements of the column of target array 60. For example, as shown in in FIG. 60, the column (2, 7, 12, 17, 22) of small array 40 has been mapped as (2, 7, 12, 12, 12, 12, 17, 22) in target array 60. Likewise, the column (4, 9, 14, 19, 24) of small array 40 has been mapped as (4, 9, 14, 14, 14, 14, 19, 24) in target array 60. The column (3, 8, 13, 18, 23) of small array 40 has been mapped into several columns in target array 60 as (3, 8, 13, 13, 13, 13, 18, 23).

[0036] In a block 55, S-parameters of the small array are mapped to the target array. For the calculation of S-parameters each antenna element is regarded as a port. In the mapping, the matrix of S-parameters saved in block 53 is mapped onto the larger array. For each port of the target array, the small array is first laid over the target array so that the port of the target array is aligned with a corresponding port of the small array. Then two-port S-parameters for the corresponding port (as a first port for the two-port S-parameter) of the small array and each of the ports (as a second port for the two-port S-parameter) of the small array are copied as S-parameters for the target array where the small array overlays the target array. Where the small array does not overlay the target array a zero or another minimal value issued for two-port S-parameter values for the corresponding port (as a first port for the two-port S-parameter) and each of the ports (as a second port for the two-port S-parameter) of the target array where the small array does not overlay the target array.

[0037] The alignment of each port of the target array with a corresponding port of the small array is performed to make sure each port of the target array uses values from the port of the small array that has the most similar surrounding ports. To arrive at the correct alignment, for each selected port of the target array, the small array is aligned so that the middle port of the small array is aligned over the selected port and then if any of the ports of the small array is located outside the boundaries of the target array, a location of the small array is shifted until the small array is completely within the large array.

[0038] As a result of using the above methodology, the corner ports of the small array are aligned directly to corresponding corner ports of the target array.

[0039] Also, ports along outside edges of the small array are aligned to ports along corresponding outside edges of the target array so that along each edge starting from corners of the edge, each port of the edge of the small array is aligned only once into a corresponding port of the corresponding edge of the target array, except for a middle port of the edge of the small array which is aligned into all remaining ports of the corresponding edge of the target array.

[0040] Likewise, along each row of the target array, each port of the row of the small array is aligned only once into a corresponding port of the corresponding row of the target array, except for a middle port of the row of the small array which is aligned into all remaining ports of the corresponding row of the target array, [0041] wherein each row of the target array corresponds to a row of the small array when end row ports from the small array have already been mapped into row end ports of the corresponding target array.

[0042] Also, along each column of the target array, each port of the column of the small array is aligned only once into a corresponding port of the corresponding column of the target array, except for a middle port of the column of the small array which is aligned into all remaining ports of the corresponding column of the target array, wherein each column of the target array corresponds to a column of the small array when end column ports from the small array have already been mapped into column end ports of the corresponding target array.

[0043] For the example using 8×8 array 30 shown in FIG. 3 as the target array and 5×5 array 40 shown in FIG. 4 as the small array, FIG. 6 gives the port of 5×5 array 40 that is to be arrayed with each port of 8×8 array 30.

[0044] For example, port 1 of 8×8 array 30 is aligned with port 1 of 5×5 array 40, as shown by the array in FIG. 6. Likewise, port 2 of 8×8 array 30 is aligned with port 2 of 5×5 array 40, as shown by the array in FIG. 6. Likewise, port 3 of 8×8 array 30 is aligned with port 3 of 5×5 array 40, as shown by the array in FIG. 6. Likewise, port 4 of 8×8 array 30 is aligned with port 3 of 5×5 array 40, as shown by the array in FIG. 6. Likewise, port 5 of 8×8 array 30 is aligned with port 3 of 5×5 array 40, as shown by the array in FIG. 6. Likewise, port 9 of 8×8 array 30 is aligned with port 6 of 5×5 array 40, as shown by the array in FIG. 6. Likewise, port 10 of 8×8 array 30 is aligned with port 7 of 5×5 array 40, as shown by the array in FIG. 6. Likewise, port 27 of 8×8 array 30 is aligned with port 13 of 5×5 array 40, as shown by the array in FIG. 6. And so on.

[0045] In FIG. 7, box 71 highlights where 5×5 array 40 overlays 8×8 array 30 for port 1 of 8×8 array 30. In FIG. 7 the locations of element/ports of 5×5 array 40 are numbered using parenthesis as (1), (2), . . . , (25) while the locations of element/ports of 8×8 array 30 are numbered without parenthesis as 1, 2, . . . , 64.

[0046] For port 1 of 5×5 array 40 there are twenty-five S-parameters: (1,1), (1,2), (1,3) . . . (1,25). For port 1 of 8×8 array 30 there are sixty-four S-parameters: (1,1), (1,2), (1,3) . . . (1,64). Where ports of 5×5 array 40 overlap the ports of 8×8 array 30, the corresponding S-parameters of 5×5 array 40 are used for the ports of 8×8 array 30. Thus, S-parameters for ports (1,1) . . . (1,5) of 5×5 array 40 are used respectively as S-parameters for ports (1,1) . . . (1,5) of 8×8 array 30. The S-parameters for ports (1,6) . . . (1,10) of 5×5 array 40 are used respectively as S-parameters for ports (1,9) . . . (1,13) of 8×8 array 30. The S-parameters for ports (1,11) . . . (1,15) of 5×5 array 40 are used respectively as S-parameters for ports (1,17) . . . (1,21) of 8×8 array 30. The S-parameters for ports (1,16) . . . (1,20) of 5×5 array 40 are used respectively as S-parameters for ports (1,25) . . . (1,29) of 8×8 array 30. The S-parameters for ports (1,21) . . . (1,25) of 5×5 array 40 are used respectively as S-parameters for ports (1,33) . . . (1,37) of 8×8 array 30. All the other parameters for port 1 of 8×8 array 30 are assigned the value of zero or some other minimal value.

[0047] In FIG. 8, box 81 highlights where 5×5 array 40 overlays 8×8 array 30 for port 25 of 8×8 array 30. Port 11 of 5×5 array 40 is aligned with port 25 of 8×8 array 30. Where ports of 5×5 array 40 overlap the ports of 8×8 array 30, the corresponding S-parameter 5×5 array 40 are copied to the ports of 8×8 array 30. Thus, S-parameters for ports (11,1) . . . (11,5) of 5×5 array 40 are used respectively as S-parameters for ports (25,9) . . . (25,13) of 8×8 array 30. The S-parameters for ports (11,6) . . . (11,10) of 5×5 array 40 are used respectively as S-parameters for ports (25,17) . . . (25,21) of 8×8 array 30. The S-parameters for ports (11,11) . . . (11,15) of 5×5 array 40 are used respectively as S-parameters for ports (25,25) . . . (25,29) of 8×8 array 30. The S-parameters for ports (11,16) . . . (11,20) of 5×5 array 40 are used respectively as S-parameters for ports (25,33) . . . (25,37) of 8×8 array 30. The S-parameters for ports (11,21) . . . (11,25) of 5×5 array 40 are used respectively as S-parameters for ports (25,41) . . . (25,45) of 8×8 array 30. All the other parameters for port 25 of 8×8 array 30 are assigned the value of zero or some other minimal value.

[0048] In FIG. 9, box 91 highlights where 5×5 array 40 overlays 8×8 array 30 for port 28 of 8×8 array 30. Port 13 of 5×5 array 40 is aligned with port 28 of 8×8 array 30. Where ports of 5×5 array 40 overlap the ports of 8×8 array 30, the corresponding S-parameter 5×5 array 40 are copied to the ports of 8×8 array 30. Thus, S-parameters for ports (13,1) . . . (13,5) of 5×5 array 40 are used respectively as S-parameters for ports (28,10) . . . (28,14) of 8×8 array 30. The S-parameters for ports (13,6) . . . (13,10) of 5×5 array 40 are used respectively as S-parameters for ports (28,18) . . . (28,22) of 8×8 array 30. The S-parameters for ports (13,11) . . . (13,15) of 5×5 array 40 are used respectively as S-parameters for ports (28,26) . . . (28,30) of 8×8 array 30. The S-parameters for ports (13,16) . . . (13,20) of 5×5 array 40 are used respectively as S-parameters for ports (28,34) . . . (28,38) of 8×8 array 30. The S-parameters for ports (13,21) . . . (13,25) of 5×5 array 40 are used respectively as S-parameters for ports (28,42) . . . (28,46) of 8×8 array 30. All the other parameters for port 25 of 8×8 array 30 are assigned the value of zero or some other minimal value.

[0049] While the foregoing written description of the invention enables one of ordinary skill to make and use what is considered presently to be the best mode thereof, those of ordinary skill will understand and appreciate the existence of variations, combinations, and equivalents of the specific embodiment, method, and examples herein. The invention should therefore not be limited by the above described embodiment, method, and examples, but by all embodiments and methods within the scope and spirit of the invention as claimed.