3D INTEGRATED CHARGE-COUPLED DEVICE MEMORY AND METHOD OF FABRICATING THE SAME

Abstract

A charge-coupled device (CCD) memory is provided. In one aspect, the CCD memory is 3D integrated. The CCD memory can include a gate stack with a plurality of gate layers and spacer layers alternatingly arranged one on the other, and a plurality of semiconductor-based channels extending in the stack. The channels may be formed from a semiconductor oxide material. The CCD memory can include dielectric layers, wherein each dielectric layer is arranged between one of the channels and at least one of the gate layers. Each channel of the CCD memory can form, in combination with the gate layers and at least one of the dielectric layers, a string of charge storage capacitors, and each string of charge storage capacitors can be operable as a CCD register. The CCD memory can also include a readout layer, which can include a plurality of readout stages configured to individually readout stored charge from each of the CCD registers.

Claims

1. A three-dimensional integrated charge-coupled device (CCD) memory comprising: a gate stack comprising a plurality of gate layers and spacer layers alternatingly arranged one on the other along a first direction, a plurality of semiconductor-based channels extending in the gate stack, and a plurality of dielectric layers, each dielectric layer being arranged between one of the semiconductor-based channels and at least one of the gate layers; and a readout layer, wherein the gate stack is arranged on the readout layer, wherein each semiconductor-based channel forms, in combination with the gate layers and at least one of the dielectric layers, a string of charge storage capacitors, wherein each string of charge storage capacitors is operable as a CCD register, and wherein the readout layer comprises a plurality of readout stages configured to individually readout stored charge from each of the CCD registers.

2. The CCD memory according to claim 1, wherein at least one semiconductor-based channel is made of a semiconductor oxide material.

3. The CCD memory according to claim 2, wherein the semiconductor oxide material comprises at least one of: indium gallium zinc oxide (IGZO), indium tin oxide (ITO), and indium zinc oxide (IZO).

4. The CCD memory according to claim 1, wherein at least one semiconductor-based channel is made of a silicon-based semiconductor material or III-V semiconductor material.

5. The CCD memory according to claim 1, wherein each CCD register is connected to one of the readout stages, which is configured to readout stored charge from the connected CCD register.

6. The CCD memory according to claim 1, wherein each CCD register is connected to a write stage configured to push charge into the CCD register.

7. The CCD memory according to claim 6, wherein the readout stage and the write stage of the CCD register are connected to different ends of the semiconductor-based channel that is associated with the CCD register.

8. The CCD memory according to claim 6, wherein the readout stage and the write stage of the CCD register are integrated with each other and are connected to one end of the semiconductor-based channel that is associated with the CCD register.

9. The CCD memory according to claim 1, wherein at least a part of each semiconductor-based channel extends along the first direction and/or extends perpendicular to parallel surfaces of the gate layers.

10. The CCD memory according to claim 1, wherein at least one semiconductor-based channel is straight in the stack.

11. The CCD memory according to claim 1, wherein at least one semiconductor-based channel has a bend in the stack.

12. The CCD memory according to claim 11, wherein the at least one semiconductor-based channel has a V-shape or a U-shape.

13. The CCD memory according to claim 1, wherein at least one semiconductor-based channel is a macaroni-type channel.

14. The CCD memory according to claim 1, wherein each gate layer surrounds one or more of the semiconductor-based channels.

15. The CCD memory according to claim 1, wherein the gate stack further comprises an input transfer-gate layer and an output transfer-gate layer, which sandwich the gate layers and the spacer layers of the gate stack in the first direction; wherein the input transfer-gate layer and the output transfer-gate layer respectively comprise a plurality of transfer-gates configured to access the CCD registers; wherein the output transfer-gate layer of the gate stack is formed on the readout layer; and wherein the transfer gates of the output transfer-gate layer are connected to the readout stages of the readout layer.

16. A method of fabricating a three-dimensional integrated charge-coupled device (CCD) memory comprising: providing a readout layer; providing a gate stack on the readout layer, the gate stack including a plurality of gate layers and spacer layers alternatingly arranged one on the other along a first direction; creating holes extending in the stack; providing dielectric material in the holes to form a plurality of dielectric layers; and providing semiconductor material in the holes to form a plurality of semiconductor-based channels, wherein each dielectric layer being arranged between one of the semiconductor-based channels and at least one of the gate layers, wherein each semiconductor-based channel forms, in combination with the gate layers and at least one of the dielectric layers, a string of charge storage capacitors, wherein each string of charge storage capacitors is operable as a CCD register, and wherein the readout layer comprises a plurality of readout stages configured to individually readout stored charge from each of the CCD registers.

17. The method according to claim 16, wherein at least one semiconductor-based channel is made of a semiconductor oxide material.

18. The method according to claim 17, wherein the semiconductor oxide material comprises at least one of: indium gallium zinc oxide (IGZO), indium tin oxide (ITO), and indium zinc oxide (IZO).

19. The method according to claim 16, wherein at least one semiconductor-based channel is made of a silicon-based semiconductor material or III-V semiconductor material.

20. The method according to claim 16, further comprising connecting each CCD register to one of the readout stages, which is configured to readout stored charge from the connected CCD register.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The above-described aspects and implementations are explained in the following description of embodiments with respect to the enclosed drawings:

[0035] FIG. 1 shows a CCD memory according to an embodiment of the disclosed technology.

[0036] FIG. 2 shows a CCD memory according to an embodiment of the disclosed technology.

[0037] FIGS. 3A, 3B, 3C, and 3D show various possible CCD registers of a CCD memory according to embodiments of the disclosed technology.

[0038] FIGS. 4A, 4B, 4C, and 4D show measurement data for measuring the retention time of a CCD register of a CCD memory according to embodiments of the disclosed technology with a semiconductor oxide based channel.

[0039] FIG. 5 shows retention time results of the measurements shown in FIGS. 4A-4D.

DETAILED DESCRIPTION OF CERTAIN ILLUSTRATIVE EMBODIMENTS

[0040] FIG. 1 shows a CCD memory 10 according to a non-limiting embodiment of the disclosed technology. The CCD memory 10 may serve as a SCM. The CCD memory 10 is three-dimensional (3D) and an integrated device. The CCD memory 10 may be fabricated in a CMOS compatible process flow.

[0041] The 3D integrated CCD memory 10 includes a gate stack 11. The gate stack 11 includes a plurality of gate layers 12 and spacer layers 13, which are alternatingly arranged one on the other along a first direction 14. The first direction 14 is thus a stacking direction of the layers 12/13 of the gate stack 11, and may be a growth direction if the gate layers 12 and the spacer layers 13 are, respectively, formed by a growth technique like epitaxy, chemical vapor deposition, or the like.

[0042] The gate stack 11 may begin with a first spacer layer 13, on which a first gate layer 12 is formed, on which a second spacer layer 13 is formed, on which a second gate layer 12 is formed, and so on. Also the last-formed layer of the gate stack 11 may be a spacer layer 13. Accordingly, there may be more spacer layers 13 than gate layers 12 in the gate stack 11. However, the number of the gate layers 12 may also be equal to the number of spacer layers 13 in the gate stack 11.

[0043] The gate layers 12 may each include at least one of the following materials: copper (Cu), aluminum (Al), titanium (Ti), tungsten (W), nickel (Ni), gold (Au), titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), niobium nitride (NbN), ruthenium tantalum (RuTa), cobalt (Co), tantalum (Ta), molybdenum (Mo), palladium (Pd), platinum (Pt), ruthenium (Ru), iridium (Ir), and silver (Ag). The spacer layers 11 may each include at least one of the following materials: silicon dioxide (SiO.sub.2), silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), aluminum oxide (Al.sub.2O.sub.3), aluminum nitride (AlN), magnesium oxide (MgO), and carbides.

[0044] The CCD memory 10 further includes a plurality of semiconductor-based channels 15, which extend in the stack 11. That is, each channel 15 extends in the gate stack 11. Thereby, one or more channels 15 may extend straight in the gate stack 11 (as shown in FIG. 1, for example, along the first direction 14). Alternatively or additionally, one or more channels 15 may extend with a bend in the gate stack 11. For example, they may have a U-shape. Multiple channels 15 of the plurality of semiconductor-based channels 15 may extend in parallel in the gate stack 11 (for example, as shown in FIG. 1). Each channel 15 may pass the gate layers 12 of the stack 11—for example, the gate layers 12 may be arranged next to the channel 15—or may go through the gate layers 12 of the stack 11—for example, the gate layers 12 may surround the channel 15. Each gate layer 12 can surround one or more of the semiconductor-based channels 15.

[0045] The one or more channels 15 may each be made of a semiconductor oxide material. For example, at least one semiconductor-based channel 15 may be made of one or more semiconductor oxide materials. The semiconductor oxide material(s) that may be used to form the channels 15 can include at least one of indium gallium zinc oxide (IGZO), indium tin oxide (ITO), and indium zinc oxide (IZO). The semiconductor oxide material(s) that may be used to form the channels 15 can additionally or alternatively include at least one of indium oxide (InO), indium tin zinc oxide (InSnZnO), cadmium oxide (CdO), gallium oxygen (GaO), tin oxide (SnO), zinc oxide (ZnO), zinc tin oxide (ZnSnO), aluminum indium zinc tin oxide (AlInZnSnO), magnesium indium gallium zinc oxide (MgInGaZnO), and tungsten indium oxide (WInO). At least one of the channels 15 may further be made of a silicon-based semiconductor material or of an III-V semiconductor material. For example, possible semiconductor materials that may be used to form the channels include silicon (Si), silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), gallium arsenide phosphide (GaAsP), indium arsenide (InAs), indium antimonide (InSb), and indium phosphide (InP).

[0046] The CCD memory 10 further includes a plurality of dielectric layers 16, wherein each dielectric layer 16 is arranged between one of the semiconductor-based channels 15 and at least one of the gate layers 12. Each dielectric layer 16 can be arranged parallel to one channel 15, or can surround one channel 15. Thereby, the dielectric layer 16 can isolate the one channel 15 from each of the gate layers 12. As mentioned before, the gate layers 12 can be arranged next to the semiconductor-based channel 15 or can surround the semiconductor-based channel—for example, with the dielectric layer 16 in between in each case.

[0047] The gate electrode layers 12, the dielectric layer(s) 16, and the semiconductor-based channel 15 may be arranged in a GAA vertical channel structure, wherein the dielectric layer 16 is wrapped completely around the channel 15, and the gate layers 12 are wrapped completely around the dielectric layer 16 and the channel 15. Further, the spacer layers 13 may also be wrapped completely around the dielectric layer 16 and the channel 15. The dielectric material of the dielectric layer 16 may include at least one of the following materials: aluminum oxide (Al.sub.2O.sub.3), silicon oxide (SiO.sub.2), silicon nitride (SiN), and a low-k material.

[0048] Each semiconductor-based channel 15 can be formed by creating (for example, etching or drilling) a hole into the gate stack 11, forming the dielectric layer(s) 16 inside the hole, and then filling the hole with the semiconductor-based material. Each semiconductor-based channel 15 may thereby extend along the first direction 14 and/or may extend perpendicular to the parallel surfaces of the gate layers 12 arranged one above another (with the spacer layers 13 in between) along the first direction 14.

[0049] In this embodiment, each semiconductor-based channel 15 forms, in combination with the gate layers 12 and at least one of the dielectric layers 16, a string of charge storage capacitors 18. The charge storage capacitors are connected in series to form the string. Each string of charge storage capacitors 18 is operable as a CCD register of the CCD memory 10. Each charge storage capacitor may be a MOS capacitor.

[0050] The CCD memory 10 further includes a readout layer 17. As shown in FIG. 1, the gate stack 11 is arranged on the readout layer 17. For instance, the first layer of the gate stack 11— for example, a spacer layer 13—may be formed on the readout layer 17. The readout layer 17 includes a plurality of readout stages 19, which is configured to individually readout stored charge from each of the CCD registers. For example, each CCD register may be connected to one of the readout stages 19 that is configured to readout stored charge from the connected CCD register.

[0051] FIG. 2 shows a non-limiting embodiment of the CCD memory 10, which can build on the embodiment shown in FIG. 1. Same elements in FIG. 1 and FIG. 2 are labelled with the same reference signs, and may be implemented in the same manner.

[0052] The CCD memory 10 is shown in FIG. 2 along an x-direction (left side drawing) and along a y-direction (right side drawing), wherein the first direction 14 is the z-direction, and wherein x, y and z are directions/axes of a Cartesian coordinate system.

[0053] The CCD memory 10 may include a plurality of bit lines 22, which may run in parallel, and corresponding bit line contacts 23 (for example, tungsten (W)). The left side drawing of FIG. 2 shows the CCD memory 10 along an x-direction that is along the bit lines 22 (notably, in some instances the bit lines could also run perpendicular to the x-direction), and the right side drawing of FIG. 2 shows the CCD memory 10 along a y-direction that is along the gate layers 12, which may be connected to gate contacts 25 (for example, made of tungsten), and via these gate contacts 25 further to a top interconnect 24 (for example, made of copper (Cu) and/or aluminum (Al)). The gate contacts 25 may be arranged in a staircase configuration. Via these gate contacts 25, the gates of the charge storage capacitors 18—that are formed by the gate layers 12, dielectric layers 16, and channels 15—can be controlled.

[0054] The gate stack 11 further includes an input transfer-gate layer 26 and an output transfer-gate layer 27, which sandwich the gate layers 12 and the spacer layers 13 of the gate stack 11 in the first direction 14. The input transfer-gate layer 26 and the output transfer-gate layer 27 may respectively include a plurality of transfer-gates configured to access the CCD registers 20. By controlling these transfer gates, bit lines and the charge storage capacitor gates, charges can be stored into the CCD register 20.

[0055] The output transfer-gate layer 27 may be arranged on the readout layer 17, and the transfer gates of the output transfer-gate layer 27 may be connected to the readout stages 19 of the readout layer 17. The readout layer 17 contains the readout stages 19 and may contain write stages 31 (which will be discussed below in more detail with respect to FIGS. 3A-3D). Each readout stage 19 and each write stage 31 may be connected to one CCD register 20. Each CCD register 20 is formed by one string of charge storage capacitors 18, wherein each capacitor 18 is formed by the channel 15, at least one dielectric layer 16, and the gate layers 12 of the gate stack 11. Each write stage 31 may be an electronic circuit configured to push/place charge into the CCD register 20. Each readout stage 19 may be a small electronic circuit used to detect tiny charges coming out of each CCD register 20 and translating them into voltage signals.

[0056] The readout layer 17 may further contain additional electronic circuitry (not shown), for instance, any electronic circuitry that may be needed or beneficial to operate the CCD memory 10. This may include electronic circuitry to operate clock signals for controlling the gates of the charge storage capacitors 18. This may also include other types of control circuits for various functions, such as data input/output, buffering, coordinating, or the like.

[0057] Each readout stage 19 and/or write stage 31 may be connected to a bit line 22. There may be different types of bit lines 22. A first type of bit lines 22 is typically running on top the gate stack 11 as depicted in FIG. 2. These bit lines 22 may be to the input of the CCD registers 20 and may be used to write data into the CCD register 20. A second type of bit lines 22 may be used to read the data out of the CCD registers 20 and may be situated at the bottom of the stack 11. These bit lines 22 may be not directly connected to the CCD register 20 outputs, but may be connected to the outputs of the readout stages 19. Since the CCD registers 20 are 3D bundles of channels 15, the readout stages 19 may be 2D arrays. The second type of bit lines 22 may run across this array to read out one single row of readout stages 19 at the same time. This second type of bit lines 22 is not indicated in FIG. 2.

[0058] The transfer gates of the input transfer-gate layer 26 may be connected to the write stages 31. Using the write stages 31, the readout stages 19, the transfer gates, and the charge storage capacitor's gates formed by the gate layers 12, the CCD register 20 can be operated.

[0059] It can also be seen in FIG. 2 that the CCD memory 10 may include more than one gate stack 11. For instance, in the left side of FIG. 2 two gate stacks 11 are illustrated. The two gate stacks 11 are separated by block separators 21, which may be made of tungsten. Multiple gate stacks 11 may be connected to the same bit line(s) 22.

[0060] FIGS. 3A-3D shows various examples of how the CCD registers 20 of the CCD memory 10 of FIG. 1 or FIG. 2 could be formed. As shown in FIGS. 3A-3D, each CCD register 20 includes a semiconductor-based channel 15, which is connected to a readout stage 19 and a write stage 31 (connection shown is only schematic). Other elements of the CCD registers 20, particularly the stack 11 and dielectric layers 16 are not shown in FIGS. 3A-3D.

[0061] As shown in FIG. 3A—similar to what is shown in FIG. 1 and FIG. 2 as examples—at least one or all semiconductor-based channels 15 may be straight in the gate stack 11. Further, a readout stage 19 and a write stage 31 associated with this CCD register 20 may be connected to different ends of the semiconductor-based channel 15 of the CCD register 20.

[0062] Alternatively, as shown in FIG. 3B, the readout stage 19 and the write stage 31 of the CCD register 20 may also be formed integrated with each other or connected to each other. In this case, they may be connected to the same end of the semiconductor-based channel 15 of the CCD register 20.

[0063] Alternatively, as shown in FIG. 3C, at least one or all semiconductor-based channels 15 may have a bend in the stack 11. For example, they can have a V-shape or U-shape (as illustrated in FIG. 3C) in the gate stack 11. In this case, the readout stage 19 and the write stage 31 of the CCD register 20 are connected to different ends of the semiconductor-based channel 15 that is associated with the CCD register 20.

[0064] As shown in FIGS. 3A-3C, at least one or all semiconductor channels 15 may be full channels. These may, for example, be formed by first creating a memory channel hole in the gate stack 11, then forming the dielectric layer(s) 16 on the wall surfaces of the hole, and then filling the remaining hole with the semiconductor-based material for the channel 15. Alternatively, as shown in FIG. 3D, at least one or all semiconductor-based channels 15 may be a macaroni-type channel. In this case, the channel 15 may be a macaroni channel that is filled with a dielectric material, which is surrounded by the semiconductor-based channel material and the dielectric layer 16, respectively.

[0065] The CCD memory 10 according to the disclosed technology may be usable as a SCM. In some implementations, this is based on the presumption that it is possible to give up the byte-addressability of, for instance, DRAM. In some implementations, a high storage density of the CCD memory 10 can be achieved by its 3D integration, as it is shown in FIG. 1 or FIG. 2. The 3D integration of the CCD memory 10 may be similar to that of a 3D NAND so as to allow for the high integration density. One possible implementation is by usage of poly-silicon and/or epitaxially grown channels 15.

[0066] Further, the use of a semiconductor oxide material for the channels 15 can increase significantly the retention time of the CCD memory 10. For instance, the use of an IGZO materials in the CCD memory 10 can allow for sufficient retention time. This can allow for a SCM that meets both the required retention time and low cost.

[0067] In this respect, IGZO-based CCD registers have already been realized successfully in a 300 mm fabrication process, and measurements have been performed, which confirm the operation with long retention times. The measurement results are shown in FIGS. 4A-4D and FIG. 5.

[0068] FIGS. 4A-4D shows an output level voltage (a voltage at a readout stage 19) over time for different retention time measurements, which have different numbers of wait cycles. In particular, as shown in FIG. 4C, for all the shown measurements, in the beginning all gate voltages related to a particular CCD register 20 were set low. Then, 500 flush cycles were carried out to get rid of any pre-existing charge(s) in the CCD register 20 by just moving them out of the CCD registers 20. After that, 142 cycles of injecting charge(s) into and moving the charge(s) through the CCD register 20 were carried out. This was followed by the respective wait cycles, which numbers zero in FIG. 4A and which were the most in FIG. 4D. Then, the previously injected charge(s) were readout (if still stored), which results in the characteristic drop of the output level voltage at the readout stage 19 associated with the CCD register 20 (visible in the figures). This was followed by further readout cycles, which did not result in the read out of any more charge(s) from the CCD register 20 (as can be seen, the output level voltage is again higher).

[0069] FIG. 5 summarizes the results of these measurements with different numbers of wait cycles. In particular, FIG. 5 shows a signal level in dependence of the retention time (which corresponds to the number of wait cycles). It can be seen that up to a retention time of about 32 seconds, the signal level remains strong, and thus indicates that the stored charges in the CCD register 20 are still captured over this time period.

[0070] In summary, embodiments of the disclosed technology provide a new kind of SCM based on a CCD memory, for example CCD memory 10, which is of low cost (high integration density), high speed, and shows a long retention time in various implementations.

[0071] In the above, the disclosed technology has mainly been described with reference to a limited number of examples. However, as is readily appreciated by a person skilled in the art, other examples than the ones disclosed above are equally possible within the scope of the disclosed technology.