Voltage clamp circuit for use in power converter

Abstract

A voltage clamp circuit comprises an input portion arranged to receive an input voltage at an input terminal. The input portion comprises a clamp diode having an anode connected to the input terminal. A first terminal of a switching element is connected to a cathode of the clamp diode and a control terminal of the switching element is connected to a reference node (Vref). A resonant tank portion comprises an inductor and a capacitor connected in series at a resonance node (Vres). The resonance node is connected to a second terminal of the switching element. The capacitor is connected between the resonance node and the first terminal of the switching element. The inductor is connected between the resonance node and an output terminal of the voltage clamp. When a voltage at the first terminal of the switching element is greater than a threshold value the switching element is turned on.

Claims

1. A voltage clamp circuit comprising: an input portion arranged to receive an input voltage at an input terminal, said input portion comprising a clamp diode having an anode thereof connected to the input terminal; a switching element having a first terminal, a second terminal, and a control terminal, wherein the first terminal is connected to a cathode of the clamp diode, and wherein the control terminal is connected to a reference node; and a resonant tank portion comprising an inductor and a capacitor connected in series at a resonance node, said resonance node being further connected to the second terminal of the switching element, wherein the capacitor is connected between the resonance node and the first terminal of the switching element, and wherein the inductor is connected between the resonance node and an output terminal of the voltage clamp; wherein the switching element is arranged such that when a voltage at the first terminal of the switching element is greater than a threshold value determined by a reference voltage at the reference node, the switching element is turned on such that a conductive path is formed between the first and second terminals of the switching element; wherein the resonant tank further comprises first and second resonant tank diodes, wherein the inductor is connected between a cathode of the first resonant tank diode and an anode of the second resonant tank diode.

2. The voltage clamp circuit as claimed in claim 1, wherein the cathode of the first resonant tank diode is connected to the resonant node.

3. The voltage clamp circuit as claimed in claim 2, wherein a cathode of the second resonant tank diode is connected to the output terminal of the voltage clamp circuit.

4. The voltage clamp circuit as claimed in claim 3, wherein an anode of the first resonant tank diode is connected to an output return terminal of the voltage clamp circuit.

5. The voltage clamp circuit as claimed in claim 1, further comprising a reference portion arranged to generate the reference voltage at the reference node.

6. The voltage clamp circuit as claimed in claim 5, wherein the reference portion comprises a resistor and a zener diode arranged in series such that a first terminal of the resistor is connected to the cathode of the clamp diode, a second terminal of the resistor is connected to a cathode of the zener diode at the reference node such that the capacitor is connected to the reference node via the zener diode, the anode of said zener diode being connected to said capacitor.

7. The voltage clamp circuit as claimed in claim 1, wherein the switching element comprises a transistor.

8. The voltage clamp circuit of claim 7, wherein the transistor is a BJT transistor.

9. The voltage clamp circuit of claim 8, wherein the BJT transistor is a pnp BJT transistor, arranged such that: the first terminal of the switching element is a collector terminal of the pnp BJT; the second terminal of the switching element is an emitter terminal of the pnp BJT; and the control terminal of the switching element is a base terminal of the pnp BJT.

10. The voltage clamp circuit as claimed in claim 1, comprising one or more further input portions each arranged to receive a respective further input voltage at a respective input terminal, each of said further input portions comprising a respective clamp diode having an anode thereof connected to the respective input terminal, wherein a cathode of each of the further clamp diodes is connected the first terminal of the switching element.

11. A power converter comprising: an input stage arranged to receive a supply voltage; an output stage arranged to produce a regulated voltage derived from the supply voltage; a transformer having a primary winding connected to the input stage, and a secondary winding connected to the output stage; and a voltage clamp connected across the transformer, said voltage clamp comprising: an input portion arranged to receive an input voltage at an input terminal, said input portion comprising a clamp diode having an anode thereof connected to the input terminal; a switching element having a first terminal, a second terminal, and a control terminal, wherein the first terminal is connected to a cathode of the clamp diode, and wherein the control terminal is connected to a reference node; and a resonant tank portion comprising an inductor and a capacitor connected in series at a resonance node, said resonance node being further connected to the second terminal of the switching element, wherein the capacitor is connected between the resonance node and the first terminal of the switching element, and wherein the inductor is connected between the resonance node and an output terminal of the voltage clamp; wherein the switching element is arranged such that when a voltage at the first terminal of the switching element is greater than a threshold value determined by a reference voltage at the reference node, the switching element is turned on such that a conductive path is formed between the first and second terminals of the switching element; wherein the resonant tank further comprises first and second resonant tank diodes, wherein the inductor is connected between a cathode of the first resonant tank diode and an anode of the second resonant tank diode.

12. The power converter as claimed in claim 11, wherein the voltage clamp comprises a second input portion arranged to receive a second input voltage at a second input terminal, said second input portion comprising a second clamp diode having an anode thereof connected to the second input terminal, wherein a cathode of the second clamp diode is connected the first terminal of the switching element, wherein said voltage clamp is arranged such that: the input terminal of the first input portion is connected to a first terminal of the secondary winding, and the input terminal of the second input portion is connected to a second terminal of the secondary winding; or the input terminal of the first input portion is connected to a first terminal of the primary winding, and the input terminal of the second input portion is connected to a second terminal of the primary winding.

13. The power converter as claimed in claim 11, wherein the output stage comprises first and second output stage diodes, wherein a cathode of the first output stage diode is connected to the first terminal of the secondary winding, and wherein a cathode of the second output stage diode is connected to the second terminal of the secondary winding.

14. The power converter as claimed in claim 11, wherein the input stage comprises an inverter arrangement comprising first, second, third, and fourth transistors arranged such that: the first and second transistors are connected in series across the supply voltage; and the third and fourth transistors are connected in series across the supply voltage, wherein the third and fourth transistors are connected in parallel to the first and second transistors; wherein the first terminal of the primary winding is connected between the first and second transistors; wherein the second terminal of the primary winding is connected between the third and fourth transistors.

15. The power converter as claimed in claim 11, wherein the input stage comprises: first and second transistors connected in series across the supply voltage; an arrangement of a capacitor and an inductor connected in series, wherein said arrangement is connected between the first terminal of the primary winding and a node between the first and second transistors.

16. The power converter as claimed in claim 11, wherein the input stage comprises: a first transistor connected between a supply voltage return and the first terminal of the primary winding of the transformer; and a second transistor connected between the supply voltage return and the second terminal of the primary winding of the transformer; wherein the supply voltage is connected to a centre-tap of the primary winding of the transformer.

17. A voltage clamp circuit comprising: an input portion arranged to receive an input voltage at an input terminal, said input portion comprising a clamp diode having an anode thereof connected to the input terminal; a switching element having a first terminal, a second terminal, and a control terminal, wherein the first terminal is connected to a cathode of the clamp diode, and wherein the control terminal is connected to a reference node; and a resonant tank portion comprising an inductor and a capacitor connected in series at a resonance node, said resonance node being further connected to the second terminal of the switching element, wherein the capacitor is connected between the resonance node and the first terminal of the switching element, and wherein the inductor is connected between the resonance node and an output terminal of the voltage clamp; wherein the switching element is arranged such that when a voltage at the first terminal of the switching element is greater than a threshold value determined by a reference voltage at the reference node, the switching element is turned on such that a conductive path is formed between the first and second terminals of the switching element; and one or more further input portions each arranged to receive a respective further input voltage at a respective input terminal, each of said further input portions comprising a respective clamp diode having an anode thereof connected to the respective input terminal, wherein a cathode of each of the further clamp diodes is connected the first terminal of the switching element.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Certain examples of the present disclosure will now be described with reference to the accompanying drawings, in which:

(2) FIG. 1 is a circuit diagram of a prior art power converter that utilises a full bridge converter topology;

(3) FIG. 2 is a graph that illustrates the issues caused by parasitic inductances associated with the prior art power converter of FIG. 1;

(4) FIG. 3 is a block diagram of a voltage clamp in accordance with an example of the present disclosure;

(5) FIG. 4 is a circuit diagram of a voltage clamp in accordance with an example of the present disclosure;

(6) FIG. 5 is a circuit diagram of a full bridge converter that utilises the voltage clamp of FIG. 4 in accordance with an example of the present disclosure;

(7) FIGS. 6A and 6B are graphs that illustrate operation of the full bridge converter of FIG. 5;

(8) FIG. 7 is a graph that further illustrates operation of the full bridge converter of FIG. 5;

(9) FIG. 8 is a circuit diagram of an LLC resonant converter that utilises the voltage clamp of FIG. 4 in accordance with an example of the present disclosure;

(10) FIG. 9 is a circuit diagram of a voltage clamp in accordance with an example of the present disclosure; and

(11) FIG. 10 is a circuit diagram of a push-pull converter that utilises the voltage clamp of FIG. 4 in accordance with an example of the present disclosure.

DETAILED DESCRIPTION

(12) FIG. 1 is a circuit diagram of a prior art power converter 2 that utilises a full bridge converter topology.

(13) The input stage comprises an inverter arrangement comprising first, second, third, and fourth transistors Q1, Q2, Q3, Q4. The first transistor Q1 and the second transistor Q2 are connected in series across the supply voltage, i.e. between the supply voltage 28 VDC and the supply voltage return 28 VDC_Rtn (i.e. ground). Similarly, the third transistor Q3 and the fourth transistor Q4 are connected in series across the supply voltage, in parallel to the first and second transistors Q1, Q2.

(14) The first terminal of the primary winding of the transformer T1 is connected between the first and second transistors Q1, Q2. The second terminal of the primary winding of the transformer T1 is connected between the third and fourth transistors Q3, Q4.

(15) As can be seen in FIG. 1, the secondary winding of the transformer T1 has an associated parasitic and leakage inductance, which is shown on the circuit diagram as a pair of inductors Leak_S1 and Leak_S2. These inductors Leak_S1 and Leak_S2 are effectively in series with the output rectifier diodes D1 and D2.

(16) The output stage comprise first and second output rectifier diodes D1, D2. The cathode of the first output rectifier diode D1 is connected to the first terminal of the secondary winding of the transformer T1, and the cathode of the second output rectifier diode D2 is connected to the second terminal of the secondary winding of the transformer T1. The respective anodes of these diodes D1, D2 are connected together at an output return OP_RTN terminal of the power converter 2.

(17) The secondary winding is centre-tapped such that an output terminal OP_+VE of the output stage is connected to a centre-tap terminal of the secondary winding of the transformer T1. Specifically, the output terminal of the output stage is connected to the centre-tap terminal of the secondary winding via an output stage inductor L1.

(18) The output stage also comprises a decoupling capacitor C2 that is connected across the output terminal and an output return terminal, i.e. across the output of the power converter 2 between OP_+VE and OP_RTN.

(19) The energy stored in parasitic and leakage inductances Leak_S1, Leak_S2 causes increase in the peak reverse voltage of D1 and D2, as shown in FIG. 2, which is a graph that illustrates the issues caused by parasitic inductances Leak_S1, Leak_S2 associated with the prior art power converter of FIG. 1.

(20) As can be seen in FIG. 2, on positive transitions of the voltages Vrec1, Vrec2 at the terminals of the secondary winding of the transformer T1 (i.e. at the cathodes of the output rectifier diodes D1, D2), these voltages Vrec1, Vrec2 undergo significant ‘spikes’, where the resulting peak values D1 Vpk, D2 Vpk are significantly greater than the typical operating values of these voltages Vrec1, Vrec2 when they are active (i.e. when they are ‘high’ or at their ‘non-zero’ value).

(21) The peak voltage can be significantly higher than the typical operating voltage, requiring the selection of a non-optimal device rating for the output rectifier diodes D1, D2. In other words, issues arising from voltage spikes are mitigated by increased the device rating of e.g. the output rectifier diodes D1 and D2.

(22) FIG. 3 is a block diagram of a ‘lossless active’ voltage clamp 100 in accordance with an example of the present disclosure. The voltage clamp 100 comprises an input portion 102, a switching element 104, a reference portion 106, and a resonant tank portion 108. It should be noted that while the capacitor (described in further detail below) is shown within the ‘input portion’ 102, in function it forms part of the resonant tank portion 108 as shown in the more detailed circuit diagram of FIG. 4, and thus is shown in a dashed box in FIG. 3.

(23) FIG. 4 is a circuit diagram of a voltage clamp in accordance with an example of the present disclosure.

(24) As can be seen in FIG. 4, the input portion 102 of the voltage clamp 100 includes a number of inputs. A first input takes a first input voltage Vrec1 at a first input terminal and passes it through a clamp diode D3. A second input takes a second input voltage Vrec2 at a second input terminal and passes it through a second clamp diode D4. There may be a number of further inputs by employing a number ‘n’ of clamp input rectifier inputs if required, as illustrated by the additional terminal arranged to receive the nth input voltage Vrec_n and pass it through a further clamp diode Dn.

(25) The anodes of each of the clamp diodes D3, D4, Dn are connected to the respective input terminals, while their cathodes are connected together at a node that supplies a clamp voltage Vclamp to the switching element 104 as outlined below. The clamp diodes D3, D4, Dn act to ‘clamp’ the voltages Vrec1, Vrec2 . . . Vrec_n to a relatively fixed level Vclamp.

(26) The switching element 104 in this example is a pnp BJT transistor Q5, arranged such that its emitter terminal is connected to the cathodes of the clamp diodes D3, D4, Dn. The collector terminal of the transistor Q5 is connected to a resonant node and produces a resonant voltage Vres at that node. The operation of this switching element 104 is explained in further detail below. In effect, the emitter terminal is an ‘input terminal’ of the switching element 104, the collector terminal is an ‘output terminal’ of the switching element 104, and the base terminal is a ‘control terminal’ of the switching element 104. The transistor Q5 has an associated gain (i.e. it acts as an amplifier), and those skilled in the art will appreciate that the value of the gain depends on the choice of transistor device.

(27) The reference portion 106 includes a resistor R1 and a zener diode D5 connected in series at a reference node, with the zener diode D5 in reverse bias. The resistor R1 is connected between the base and emitter terminals of the BJT transistor Q5, where one terminal of the resistor R1 is connected to the emitter terminal of Q5 and the cathodes of the clamp diodes D3, D4, Dn, while the other terminal of the resistor R1 is connected to the base terminal of the transistor Q5 and to the cathode of the zener diode D5. The anode of the zener diode D5 is connected to the output return terminal OP_RTN of the voltage clamp 100.

(28) The reference portion 106 acts to produce a relatively stable reference voltage Vref at the base terminal of the transistor Q5, where the reference voltage Vref is generated from the clamp voltage Vclamp, and its value is determined by the reverse breakdown voltage of the zener diode D5.

(29) The resonant tank portion 106 is constructed from an inductor L2, a capacitor C2, and a pair of resonant tank diodes D6, D7. The inductor L2 is connected between the cathode of the first resonant tank diode D6 and the anode of the second resonant tank diode D7. The cathode of the first resonant tank diode D6 is connected to the collector terminal of the transistor Q5 of the switching element 104. The cathode of the second resonant tank diode D7 is connected to the output terminal OP_+VE of the voltage clamp 100. The anode of the first resonant tank diode D6 is connected to the output return terminal OP_RTN of the voltage clamp 100.

(30) The capacitor C2 is connected between the anode of the first resonant tank diode D6 (and thus one terminal of the capacitor C2 is connected to the output return terminal OP_RTN of the voltage clamp 100) and the cathodes of the clamp diodes D3, D4, Dn (and thus the other terminal of the capacitor C2 is connected to the emitter terminal of the transistor Q5). The inductor L2 and capacitor C2 work together as an LC resonator.

(31) It can be seen, therefore, that the voltage clamp 100 can take multiple inputs, and provides a clamped output voltage across the capacitor C2, recycling the stored energy to the output terminal OP_+IVE, OP_RTN of the voltage clamp 100. The principles of the voltage clamp described herein can be extended to recycle parasitic inductance energy for multiple output converters, by employing a number ‘n’ of clamp input rectifier inputs if required.

(32) As outlined below with reference to FIGS. 9 and 10, the voltage clamp may also be applied to primary-side circuits (i.e. connected to the primary winding of the transformer) to control peak switch voltages, recycling energy to the input source.

(33) FIG. 5 shows a possible application of the voltage clamp 100 of FIG. 4 in accordance with an example of the present disclosure. Specifically, FIG. 5 shows a power converter that utilises a full bridge topology, similar to that of FIG. 1. However, unlike the power converter 2 of FIG. 1, in the power converter of FIG. 5, the input portion 102 is connected to the cathodes of the full bridge rectifier diodes D1 and D2, as shown by the leads labelled Vrec1 and Vrec2, which are input to the inputs of the voltage clamp 100 as described above.

(34) In the converter 200 of FIG. 5, the input stage 202 comprises a first transistor Q1 and a second transistor Q2 connected in series across the supply voltage, i.e. between 28 VDC and 28 VDC_Rtn. Similarly, a third transistor Q3 and a fourth transistor Q4 are also connected in series across the supply voltage, in parallel to the first and second transistors Q1, Q2.

(35) Proper switching of the transistors Q1-4 gives rise to AC voltages Va, Vb at respective nodes between the first and second transistors Q1, Q2 and the third and fourth transistors Q4, where the first of these voltages Va is supplied to one terminal of the primary winding of the transformer T1 and the second of these voltages Vb is supplied to the other terminal of the primary winding of the transformer T1. The full bridge rectifier operation and the associated transistor switching requirements are known in the art per se.

(36) The switching element 104 is self-driven by the resonant action of the clamp capacitor C2 and the resonant inductor L2 in the resonant tank portion 108. The operation of the resonant tank portion 108 that provides this resonant action is described in further detail with respect to FIGS. 6A, 6B, and 7 below.

(37) The lossless active voltage clamp 100 is arranged to recycle energy from the parasitic and leakage inductances Leak_S1, Leak_S2 at the secondary side of the transformer T1 to a load connected to the converter output OP_+VE.

(38) FIGS. 6A and 6B are graphs that illustrates operation of the full bridge converter 200 of FIG. 5. As can be seen in FIG. 6A, the voltage clamp 100 acts to limit the full bridge rectifier diode peak reverse voltage, i.e. the voltages Vrec1 and Vrec2, by the steady state level of Vclamp. While there is some initial ripple on the positive transitions of these voltages Vrec1 and Vrec2, the magnitude of the ‘overshoot’ is significantly reduced compared to the overshoot associated with prior art arrangements, as described above with reference to FIG. 2.

(39) The resonant tank behaviour can be seen in FIG. 6B, though this is described in greater detail with reference to FIG. 7. When one of the input voltages Vrec2 undergoes a positive transition, it is clamped by the steady state level of Vclamp. The resonant voltage Vres at the output of the transistor Q5 (i.e. of the switching element 104) to pulse high as the transistor Q5 begins to conduct.

(40) This change in the resonant voltage Vres causes the inductor L2 to begin charging, where the current i_L2 through the inductor L2 rises linearly throughout the charging cycle. As the inductor L2 charges, the current i_D7 through the second resonant tank diode D7 also rises throughout the charging cycle of the inductor L2.

(41) As the voltage Vrec2 reaches its steady state, the resonant voltage Vres drops to zero, and the current i_L2 through the inductor L2 reduces linearly throughout the discharging cycle of the inductor L2. The current i_D7 through the second resonant tank diode D7 also reduces linearly throughout the discharge cycle of the inductor L2.

(42) During the discharging cycle of the inductor L2, the current i_D6 through the first resonant tank diode D6 initially rises until it is equal with the current i_D7 through the second resonant tank diode D7, at which point the current through both diodes D6, D7 reduces at the same rate.

(43) FIG. 7 is a graph that further illustrates operation of the full bridge converter 200 of FIG. 5. As outlined previously, the clamp input rectifiers D3 and D4 of the input portion 102 of the voltage clamp 100 are connected to the Vrec1 and Vrec2, i.e. to the cathodes of the full bridge rectifier diodes D1 and D2.

(44) Once steady state conditions are reached at to, the transistor Q5 is in its OFF state and the peak voltages of Vrec1 and Vrec2 are rectified by D3 and D4 respectively, clamped by the capacitor C2. The energy stored in the parasitic inductances Leak_S1, Leak_S2 begins to charge the capacitor C2 via the respective clamp diodes D3, D4. This charging of the capacitor C2 causes a small increase in the clamp voltage Vclamp, where this change is labelled ΔVclamp.

(45) At t1, the value of Vclamp exceeds the reference voltage Vref (by more than the threshold voltage of Q5) and the transistor Q5 switches to its ON state. Once the transistor Q5 is ON, this activates the resonant tank action of C2 and L2. The energy stored in the capacitor C2 begins to transfer to the inductor L2 and the to the output load, given that the second resonant tank diode D7 is forward biased and is clamped by the converter output voltage OP_+VE.

(46) The energy previously stored in the parasitic and inductances Leak_S1, Leak_S2 is exhausted by t2 and this energy has been transferred to the resonant tank, i.e. to the capacitor C2 and inductor L2. The energy stored in the capacitor C2 begins to transfer to the inductor L2, which causes the clamp voltage Vclamp to fall.

(47) Once Vclamp falls to the OFF threshold, Q5 switches to the OFF state.

(48) Additionally, the resonant voltage Vres at the output of the transistor Q5 begins to fall towards 28 VDC_Rtn.

(49) At t3, the transfer of the energy stored in the capacitor C2 (represented by ΔVclamp) is complete, which prevents any further discharge of the capacitor C2. The resonant voltage Vres at the output of the transistor Q5 is clamped to 28 VDC_Rtn and the first resonant tank diode D6 begins to conduct. The energy stored in the inductor L2 begins to discharge to the output via the tank diodes D6, D7.

(50) At t4, the resonant stored energy transfer cycle from parasitic and leakage inductances Leak_S1, Leak_S2 to the output is complete.

(51) FIG. 8 is a circuit diagram of an LLC resonant converter 300 that utilises the voltage clamp 100 of FIG. 4 in accordance with an example of the present disclosure.

(52) In the converter 300 of FIG. 8, the input stage 302 comprises a first transistor Q1 and a second transistor Q2 connected in series across the supply voltage, i.e. between 28 VDC and 28 VDC_Rtn. A capacitor C3 and an inductor L1 are connected in series such that the capacitor C3 and inductor L1 are connected between the first terminal of the primary winding of the transformer T1 and a node between the first and second transistors Q1, Q2.

(53) The capacitor C3, inductor L1, and primary winding of the transformer T1 together form an LLC resonator, such that proper switching of the transistors Q1, Q2 gives rise to an AC voltage Va at the node between the transistors Q1. The voltage Va is fed through the primary winding of the transformer T1, giving rise to the buck voltage Vbuck on the secondary side, and to the rectified voltages Vrec1, Vrec2 at the cathodes of the rectifier diodes D1, D2. The voltage clamp 100 of FIG. 4 is connected such that these rectified voltages Vrec1, Vrec2 are supplied to the input of the voltage clamp in the same manner described previously with reference to FIG. 5.

(54) As outlined previously, the voltage clamp may also be applied to primary side circuits. FIG. 9 is a circuit diagram of a voltage clamp 400 that may be applied to primary side circuits. It should be noted that this voltage clamp 400 has like components to those of the voltage clamp 100 of FIG. 4, however the voltages at the inputs and outputs of the voltage clamp 400 relate to primary-side voltages. Like reference numerals and labels indicate like components.

(55) An example of a primary-side application of the voltage clamp 400 of FIG. 9 is shown in FIG. 10, which is a circuit diagram of a push-pull converter 500 that utilises the voltage clamp 400 of FIG. 9 in accordance with an example of the present disclosure.

(56) In the push-pull converter 500 of FIG. 10, a first transistor Q1 is connected between the supply voltage return 28 VDC_Rtn and the first terminal of the primary winding of the transformer T1. A second transistor Q2 is connected between the supply voltage return 28 VDC_Rtn and the second terminal of the primary winding of the transformer T1.

(57) In this converter, the primary winding of the transformer T1 is centre-tapped, where the supply voltage 28 VDC is connected to a centre-tap of the primary winding of the transformer T1. Suitable control signals may be applied to the first and second transistors Q1, Q2 to provide push-pull operation in a manner known in the art per se.

(58) Here, the voltage clamp 400 of FIG. 9 is arranged such that the inputs of the voltage clamp 400 are connected to the voltages Va, Vb at the respective drain terminals of the transistors Q1, Q2. The outputs of the voltage clamp 400 are connected to the input terminals 28 VDC, 28 VDC_RTN of the push-pull converter 500.

(59) Thus it will be appreciated by those skilled in the art that examples of the present disclosure provide an improved, self-controlling voltage clamp that may limit excess voltages due to parasitic inductance within the power supply without requiring a dedicated controller.

(60) While specific examples of the disclosure have been described in detail, it will be appreciated by those skilled in the art that the examples described in detail are not limiting on the scope of the disclosure.