VOLTAGE REGULATOR COMPRISING A CHARGE PUMP CIRCUIT

Abstract

In embodiments, a voltage regulator has an input node to receive an input voltage and an output node. The voltage regulator has a charge pump circuit that receives a boosting control signal to boost the input voltage based on the boosting control signal. The voltage regulator further has a feedback regulation circuit configured to receive the output voltage and to provide a first operation control signal and a second operation control signal as a function of the output voltage; a phase control circuit configured to receive the first operation control signal and to provide the boosting control signal as a function of the first operation control signal; and a filter coupled to the output node, configured to receive the second operation control signal and configured to inject to or sink from the output node a charge that is a function of the second operation control signal.

Claims

1. A voltage regulator, comprising: a charge pump circuit coupled between an input node of the voltage regulator and an output node of the voltage regulator, the charge pump circuit configured to generate an output voltage at the output node based on a respective boosting control signal, the output voltage having a boosted value with respect to an input voltage received at the input node; a feedback regulation circuit configured to generate a first operation control signal and a second operation control signal as a function of the output voltage; a phase control circuit configured to generate a boosting control signal as a function of the first operation control signal; and a filter configured to inject to or sink from the output node a charge that is a function of the second operation control signal.

2. The voltage regulator of claim 1, wherein the filter comprises a capacitive element having a first terminal and a second terminal, the first terminal coupled to the output node, and the second terminal configured to receive the second operation control signal.

3. The voltage regulator of claim 1, wherein the feedback regulation circuit comprises an inverter configured to receive the first operation control signal and generate the second operation control signal.

4. The voltage regulator of claim 3, wherein the inverter is a first inverter, the feedback regulation circuit further comprising a second inverter configured to receive the second operation control signal and generate a third operation control signal, the filter comprising a capacitive element having a first terminal and a second terminal, the first terminal coupled to the output node, and the second terminal configured to receive the third operation control signal.

5. The voltage regulator of claim 4, wherein the first inverter has a first response time in generating the second operation control signal in response to a switching of the first operation control signal, and wherein the second inverter has a second response time in generating the third operation control signal in response to a switching of the second operation control signal, the second response time being greater than the first response time.

6. The voltage regulator of claim 1, wherein the feedback regulation circuit comprises a comparator configured to: compare the output voltage to a reference voltage; switch the first operation control signal to a first value in response to the output voltage being greater than the reference voltage; and switch the first operation control signal to a second value in response to the output voltage being less than the reference voltage.

7. The voltage regulator of claim 6, wherein the phase control circuit is configured to: disable a boosting of the input voltage by the charge pump circuit in response to the first operation control signal switching to the first value; and enable the boosting of the input voltage by the charge pump circuit in response to the first operation control signal switching to the second value.

8. The voltage regulator of claim 1, wherein the voltage regulator is a voltage regulator of a non-volatile memory.

9. The voltage regulator of claim 8, wherein the non-volatile memory is a phase-change memory.

10. A method, comprising: generating, by a charge pump circuit of a voltage regulator, an output voltage at an output node of the voltage regulator, the output voltage being a boosted value with respect to an input voltage received at an input node of the voltage regulator, the output voltage being based on a respective boosting control signal, the charge pump circuit coupled between the input node and the output node; generating, by a feedback regulation circuit of the voltage regulator, a first operation control signal and a second operation control signal as a function of the output voltage; generating, by a phase control circuit of the voltage regulator, a boosting control signal as a function of the first operation control signal; and injecting to or sinking from, by a filter of the voltage regulator, the output node a charge that is a function of the second operation control signal.

11. The method of claim 10, wherein generating the second operation control signal comprises inverting the first operation control signal to generate the second operation control signal.

12. The method of claim 10, wherein the filter comprises a first capacitive element, a first terminal of the first capacitive element coupled to the output node, the method further comprising receiving the second operation control signal at a second terminal of the first capacitive element.

13. The method of claim 12, wherein the filter comprises a second capacitive element, a first terminal of the second capacitive element coupled to the output node, the method further comprising: generating, by the feedback regulation circuit, a third operation control signal; and receiving, by a second terminal of the second capacitive element, the third operation control signal, the third operation control signal being an inverted signal with respect to the second operation control signal.

14. The method of claim 10, further comprising: comparing the output voltage to a reference voltage; switching the first operation control signal to a first value in response to the output voltage being greater than the reference voltage; and switching the first operation control signal to a second value in response to the output voltage being less than the reference voltage.

15. The method of claim 10, wherein the step of injecting to or sinking from the output node is performed faster than a step of providing, by the phase control circuit, the respective boosting control signal to the charge pump circuit.

16. A device comprising a non-volatile memory having a voltage regulator, the voltage regulator comprising: a charge pump circuit coupled between an input node of the voltage regulator and an output node of the voltage regulator, the charge pump circuit configured to generate an output voltage at the output node based on a respective boosting control signal, the output voltage having a boosted value with respect to an input voltage received at the input node; a feedback regulation circuit configured to generate a first operation control signal and a second operation control signal as a function of the output voltage; a phase control circuit configured to generate a boosting control signal as a function of the first operation control signal; and a filter configured to inject to or sink from the output node a charge that is a function of the second operation control signal.

17. The device of claim 16, wherein the filter comprises a capacitive element having a first terminal and a second terminal, the first terminal coupled to the output node, and the second terminal configured to receive the second operation control signal, and wherein the feedback regulation circuit comprises an inverter configured to receive the first operation control signal and generate the second operation control signal.

18. The device of claim 17, wherein the inverter is a first inverter, the feedback regulation circuit further comprising a second inverter configured to receive the second operation control signal and generate a third operation control signal, the filter comprising a capacitive element having a first terminal and a second terminal, the first terminal coupled to the output node, and the second terminal configured to receive the third operation control signal.

19. The device of claim 18, wherein the first inverter has a first response time in generating the second operation control signal in response to a switching of the first operation control signal, and wherein the second inverter has a second response time in generating the third operation control signal in response to a switching of the second operation control signal, the second response time being greater than the first response time.

20. The device of claim 16, wherein the feedback regulation circuit comprises a comparator configured to: compare the output voltage to a reference voltage; switch the first operation control signal to a first value in response to the output voltage being greater than the reference voltage; and switch the first operation control signal to a second value in response to the output voltage being less than the reference voltage, and wherein the phase control circuit is configured to: disable a boosting of the input voltage by the charge pump circuit in response to the first operation control signal switching to the first value, and enable the boosting of the input voltage by the charge pump circuit in response to the first operation control signal switching to the second value.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0029] For a better understanding of the present invention, non-limiting embodiments are now described, with reference to the attached drawings, wherein:

[0030] FIG. 1 shows a block diagram of a known voltage regulator including a charge pump circuit;

[0031] FIG. 2 shows a time diagram of waveforms of the voltage regulator of FIG. 1, in use;

[0032] FIG. 3 shows a block diagram of an embodiment of the present voltage regulator including a charge pump circuit;

[0033] FIG. 4 shows a circuit diagram of an exemplary embodiment of the charge pump circuit of FIG. 3;

[0034] FIG. 5 shows a time diagram of waveforms of the charge pump circuit of FIG. 4, in use;

[0035] FIG. 6 shows a block diagram of a different embodiment of the present voltage regulator;

[0036] FIG. 7 shows a block diagram of a non-volatile memory incorporating the present voltage regulator; and

[0037] FIG. 8 shows a circuit diagram of an embodiment of a comparator of the present voltage regulator.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0038] FIG. 3 shows a voltage regulation circuit or voltage regulator 50, including a charge pump circuit 52 connected between an input node 53, receiving an input voltage V.sub.IN, and an output node 54, providing an output voltage V.sub.OUT.

[0039] Voltage regulator 50 provides output voltage V.sub.OUT to a load, here a capacitive load 55 having a capacitance C.sub.L, coupled between output node 54 and a reference potential line (ground) 57.

[0040] The input voltage V.sub.IN is a low voltage, for example, included between 1V and 4 V, in particular of about 2.8 V, which may be an internal supply voltage (i.e., the logic supply voltage V.sub.DD of voltage regulator 50 or a different voltage generated by other circuit components, here not shown) coupled to the voltage regulator 50.

[0041] Charge pump circuit 52 may include one boosting stage connected between input node 53 and output node 54 or a plurality of boosting stages mutually connected in series or in parallel between the input node 53 and the output node 54.

[0042] The boosting stages are of a known type, for example, the boosting stages may each be a voltage doubler circuit or a different type of circuit, depending on the specific application.

[0043] Circuit pump circuit 52 receives one or more phase signals PHASES (also indicated hereinafter as boosting control signals) that control the selective activation and deactivation of the boosting stages to enable the selective and alternate transfer of charge accumulated in each boosting stage from one boosting stage to the next.

[0044] An exemplary embodiment of charge pump circuit 52 is shown in FIG. 4 and described in detail hereinafter.

[0045] Voltage regulator 50 provides an on-off regulation of charge pump circuit 52 to keep the output voltage V.sub.OUT equal to the desired output voltage, for example, included between 4 V and 6 V, here indicated as reference voltage V.sub.REF.

[0046] In embodiments, voltage regulator 50 includes a comparator 58, which receives output voltage V.sub.OUT and reference voltage V.sub.REF and provides an operation control signal, here indicated as stop signal STOP, and a phase control circuit 60 receiving the stop signal STOP and providing the phase signals PHASES. Comparator 58 provides the stop signal STOP in response to comparing output voltage V.sub.OUT and reference voltage V.sub.REF. In this embodiment, stop signal STOP is a square wave signal having a high logic value, here logic supply voltage V.sub.DD, and a low logic value, here 0 V. Comparator 58 switches the stop signal STOP to the high logic value when the output voltage V.sub.OUT becomes higher than the reference voltage V.sub.REF and switches the stop signal STOP to the low logic value when the output voltage V.sub.OUT becomes lower than the reference voltage V.sub.REF. In this embodiment, comparator 58 is biased by the logic supply voltage V.sub.DD.

[0047] Phase control circuit 60 includes an oscillator 63, which receives the stop signal STOP and provides a clock signal CLK, and a logic control circuit 65, which receives the clock signal CLK and provides the phase signal PHASES to the charge pump circuit 52.

[0048] While the stop signal STOP has a low logic value, the clock signal CLK switches between a low logic value (e.g., 0 V) and a high logic value (e.g., the logic supply voltage V.sub.DD) with a high frequency, for example, of the order of megahertz (e.g. of 150 MHz).

[0049] While the stop signal STOP has a high logic value, oscillator 63 stops switching the clock signal CLK between the respective high and low logic values. For example, when the stop signal STOP switches from the respective low logic value to the respective high logic value (i.e., on the rising edge of the stop signal STOP), oscillator 63 freezes the clock signal CLK to the current (or actual) value thereof.

[0050] Logic control circuit 65 provides the phase signals PHASES to the charge pump circuit 52. The number of the phase signals PHASES depends on the specific implementation of charge pump circuit 52, for example, on the number and specific configuration and type of the stages of charge pump circuit 52. By example only and described hereinafter, FIG. 5 shows examples of phase signals PHASES of the exemplary embodiment of charge pump circuit of FIG. 4.

[0051] According to an embodiment, logic control circuit 65 may include one or more level shifter circuits configured to adjust the high and low logic voltage values of the phase signals PHASES starting from the clock signal CLK. For example, level shifter circuits may be used if the input voltage V.sub.IN differs from the logic supply voltage V.sub.DD. In this case, as indicated by a dashed arrow in FIG. 3, logic control circuit 65 receives the input voltage V.sub.IN.

[0052] Voltage regulator 50 further includes a regulation capacitor 70 having a capacitance C.sub.B and having a first terminal 70A coupled to the output node 54 and a second terminal 70B receiving an inverted stop signal STOP_N.

[0053] The capacitance C.sub.B of regulation capacitor 70 is smaller than the load capacitance, for example, included between 1/30 and 1/10, in particular 1/20, of the capacitance C.sub.L of load 55. In embodiments, the ratio between the capacitance C.sub.B of the regulation capacitor 70 and the capacitance C.sub.L of the load 55 may be chosen depending on the ratio between ΔV and the logic supply voltage V.sub.DD, wherein ΔV is the desired voltage reduction of the ripple of the output voltage V.sub.OUT, in use, as discussed in detail hereinafter.

[0054] In embodiments, voltage regulator 50 further includes an inverter 75 receiving the stop signal STOP and providing the inverted stop signal STOP_N. In this embodiment, inverter 75 is biased at the logic supply voltage V.sub.DD; however, inverter 75 may be biased at a different voltage (e.g., the input voltage V.sub.IN).

[0055] Inverter 75 has a low response time, for example, of a few nanoseconds (e.g., included between 1 ns and 6 ns) with respect to a switch of the stop signal STOP.

[0056] In embodiments, in response to a switch of stop signal STOP from the respective low logic value to the respective high logic value, inverter 75 switches the inverted stop signal STOP_N from the respective high logic value to the respective low logic value in a short time interval, for example, of few nanoseconds, in particular included between 1 ns and 6 ns.

[0057] Similarly, in response to a switch of stop signal STOP from the respective high logic value to the respective low logic value, inverter 75 switches the inverted stop signal STOP_N from the respective low logic value to the respective high logic value in a short time interval, for example, of few nanoseconds, in particular included between 1 ns and 6 ns.

[0058] In practice, the response time of inverter 75 is lower than the time taken by phase control circuit 60 to react to a switch of the stop signal STOP (i.e., to start or stop the operation of the charge pump circuit 52).

[0059] In practice, inverter 75 and comparator 58 form a feedback regulation circuit 77, represented in FIG. 3 by a dashed line, configured to provide the stop signal STOP and the inverted stop signal STOP_N as a function of the output voltage V.sub.OUT, in particular as a function of the comparison between the output voltage V.sub.OUT and the reference voltage V.sub.REF.

[0060] By example only, FIG. 4 shows a detailed embodiment of charge pump circuit 52 having two boosting stages 80A, 80B, mutually coupled at an intermediate node 82 of charge pump circuit 52. Boosting stage 80A has an input node 83 that receives input voltage V.sub.IN and an output node directly connected to intermediate node 82. Boosting stage 80B has an input node directly connected to intermediate node 82 and an output node 84 providing output voltage V.sub.OUT.

[0061] Boosting stages 80A, 80B, here equal with each other, are each a voltage double circuit and are each formed by a respective first portion 85A, coupled between the respective input node 83, 82 and a respective stage intermediate node 86, and by a respective second portion 85B, coupled between the respective stage intermediate node 86 and the respective output node 82, 84.

[0062] First portion 85A of boosting stages 80A, 80B is formed by two pumping capacitors 87A, 87B having a first terminal coupled to input node 83, 82 of the respective boosting stage 80A, 80B through respective switches, here two MOSFET transistors 88. The first terminal of the pumping capacitors 87A, 87B is also coupled to the gate terminal of a respective MOSFET transistor 89 whose conduction terminals (source and drain) are connected to the input node 83, 82 of the respective boosting stage 80A, 80B and the stage intermediate node 86.

[0063] Second portion 85B of boosting stages 80A, 80B is formed by two pumping capacitors 90A, 90B having a first terminal coupled to the output node 82, 84 of the respective boosting stage 80A, 80B through respective switches, here two MOSFET transistors 91. The first terminal of the pumping capacitors 90A, 90B is also coupled to the gate terminal of a respective MOSFET transistor 92 whose conduction terminals (source and drain) are connected to the output node 82, 84 of the respective boosting stage 80A, 80B and the stage intermediate node 86.

[0064] Boosting stages 80A, 80B further have each two pass capacitors 93 having a first terminal coupled to the intermediate node 86 of the respective boosting stage 80A, 80B.

[0065] According to the example of FIG. 4, logic control circuit 65 provides a plurality of phase signals PHASES, including phase signals P1, P2, P1_N, P2_N, CKA, and CKB (of which an example is shown in FIG. 5) that are provided to boosting stage 80A and phase signals P1.sub.2, P2.sub.2, P1_N.sub.2, P2_N.sub.2, CKA.sub.2, and CKB.sub.2 that are provided to the boosting stage 80B.

[0066] In embodiments, phase signals P1 and P2 are provided to a second terminal of the pumping capacitor 87A and, respectively, to a second terminal of the pumping capacitor 87B. Phase signals P1_N and P2_N are complimentary (negated) with respect to phase signals P1 and, respectively, P2 and are provided to a second terminal of the pumping capacitor 90A and, respectively, to a second terminal of the pumping capacitor 90B. Phase signals CKA and CKB are negated one with respect to the other and are provided to the pass capacitors 87A, 87B, respectively. In this embodiment, phase signals P1.sub.2, P2.sub.2,P1_N.sub.2, P2_N.sub.2, CKA.sub.2, and CKB.sub.2 are equal to phase signals P1, P2, P1_N, P2_N, CKA, and CKB, respectively, and have a 90° phase shift thereto.

[0067] In use, voltage regulator 50 has an on-phase, where charge pump circuit 52 is active and enables accumulation and transfer of charges between input node 52 and output node 54, and an off-phase, where charge pump circuit 52 is deactivated and accumulation and transfer of charges between input node 52 and output node 54 are stopped. During the on-phase, output voltage your increases in time.

[0068] For example, with reference to the exemplary implementation of charge pump circuit 52 of FIG. 4, FIG. 5 shows a possible behavior in time of phase signals P1, P2, P1_N, P2_N, CKA, and CKB during the on-phase of the voltage regulator 50. In embodiments, phase signals P1, P2, P1_N, P2_N, CKA, and CKB oscillate, during the on-phase, between a respective high and a respective low logic value to enable sequential accumulation and transfer of charges between input node 52 and output node 54, through boosting stage 80A, 80B of circuit pump circuit 52.

[0069] During the off-phase, the phase signals PHASES have a constant value (i.e., do not oscillate), thereby deactivating the accumulation and transfer of charges through charge pump circuit 52. During the off-phase, the output voltage V.sub.OUT, decreases in time due to a current flowing through load 55 (i.e., from the output node 54 to the ground 57).

[0070] In voltage regulator 50, during the on-phase, when output voltage V.sub.OUT becomes higher than the reference voltage V.sub.REF, comparator 58 switches the stop signal STOP to the respective high value (i.e., logic supply voltage V.sub.DD).

[0071] Accordingly, inverter 75 switches inverted stop signal STOP_N to the respective low value. When inverted stop signal STOP_N switches from the high value (i.e., supply logic voltage V.sub.DD) to the low value (i.e., 0 V), a voltage change equal to the difference between the high value and the low value (i.e., equal to V.sub.DD) occurs at the second terminal 70B of regulation capacitor 70. Accordingly, regulation capacitor 70 sinks, from the output node 54, a charge equal to CC.sub.B.Math.V.sub.DD, thereby lowering the value of output voltage V.sub.OUT.

[0072] Therefore, even if phase control circuit 60 has a time delay before stopping the phase signals PHASES and deactivating charge pump circuit 52, the increase of output voltage V.sub.OUT that would occur during the time delay is, at least partially, compensated by charge CC.sub.B.Math.V.sub.DD sunk by regulation capacitor 70.

[0073] During the off-phase of voltage regulator 50, when output voltage V.sub.OUT decreases below reference voltage V.sub.REF, comparator 58 switches the stop signal STOP to the respective low value (i.e., 0 V). Accordingly, inverter 75 switches the inverted stop signal STOP_N to the respective high value (i.e., logic supply voltage V.sub.DD).

[0074] When inverted stop signal STOP_N switches from the low value (i.e., 0 V) to the low value (i.e., supply logic voltage V.sub.DD), a voltage change equal to the difference between the low value and the high value (i.e., equal to V.sub.DD) occurs at the second terminal 70B of regulation capacitor 70. Accordingly, regulation capacitor 70 injects to output node 54 a charge equal to CC.sub.B.Math.V.sub.DD, thereby increasing the value of output voltage V.

[0075] Therefore, even if phase control circuit 60 has a time delay before activating charge pump circuit 52, the decrease of output voltage your that would occur during the time delay is, at least partially, compensated by the charge CC.sub.B.Math.V.sub.DD injected by regulation capacitor 70 to output node 54.

[0076] In practice, regulation capacitor 70 acts as a filter that injects to or sinks from output node 54 an amount of charge that is a function of the inverted stop signal STOP_N.

[0077] For example, considering V.sub.DD=1 V and capacitance C.sub.B of regulation capacitor 70 to be 1/20 of load capacitor 55, a high-low (or low-high) switch of the stop signal STOP may change output voltage your by tens of millivolts.

[0078] It has been verified by Applicant that the peak-to-peak amplitude of the ripples of output voltage your of voltage regulator 50 may be reduced, for example, of about 40%, with respect to peak-to-peak amplitude V.sub.R of the ripples of output voltage your of the known voltage regulator 1 described with reference to FIGS. 1 and 2.

[0079] By tuning the absolute value of the high-low voltage difference of the inverted stop signal STOP_N and the value of the capacitance C.sub.B of regulation capacitor 70, for example, at the design stage or in use, it is possible to adjust the charges injected to and sunk from output node 54, thereby adjusting the correction amount of the peak-to-peak amplitude of the ripples of output voltage V.sub.OUT.

[0080] It is possible to reduce the ripples of output voltage V.sub.OUT, by keeping the capacitance C.sub.B of regulation capacitor 70 much smaller than the capacitance C.sub.L of capacitive load 55, which allows voltage regulator 50 to occupy a smaller die area resulting in lower manufacturing costs.

[0081] FIG. 6 shows a different embodiment of the present voltage regulator, indicated by 150. Voltage regulator 150 has a general structure similar to voltage regulator 50 of FIG. 2; therefore, elements in common are indicated by the same reference numerals and are not further described.

[0082] In embodiments, voltage regulator 150 includes charge pump circuit 52 coupled between input node 53 and output node 54; comparator 58 receiving the output voltage V.sub.OUT and providing the stop signal STOP; and phase control circuit 60 receiving the stop signal STOP and providing the phase signals PHASES. Voltage regulator 150 also includes the regulation capacitor 70, indicated as the first regulation capacitor 70, and the inverter 75, indicated as the first inverter 75. Voltage regulator 150 further includes a second regulation capacitor 153 and a second inverter 155. Second regulation capacitor 153 has a capacitance C.sub.B2 smaller than the capacitance C.sub.L of capacitive load 55, for example, included between 1/30 and 1/10 of the capacitance C.sub.L, in particular about 1/20 of the capacitance C.sub.L.

[0083] The second regulator capacitor 153 has a first terminal 153A coupled to the output node 54 and a second terminal 153B coupled to the output of the second inverter 155. Second inverter 155 receives the inverted stop signal STOP_N, here indicated as the first inverted stop signal STOP_N, from first inverter 75 and provides at the output a second inverted stop signal STOP_NN.

[0084] In practice, first inverter 75, comparator 58, and second inverter 175 form a feedback regulation circuit, here indicated by 177 and represented by a dashed line, configured to provide the stop signal STOP, the first inverted stop signal STOP_N and the second inverted stop signal STOP_NN as a function of the output voltage V.sub.OUT, in particular as a function of the comparison between the output voltage V.sub.OUT and the reference voltage V.sub.REF.

[0085] The second inverter 155 is biased by logic supply voltage V.sub.DD. In this embodiment, the high logic value of the second inverted stop signal STOP_NN is logic supply voltage V.sub.DD, and the low logic value of the second inverted stop signal STOP_NN is 0 V.

[0086] Second inverter 155 has a response time that is higher than the response time of first inverter 75, for example, at least ten times higher, for example of tens of nanoseconds, in particular included between 20 ns and 100 ns.

[0087] The response time of the second inverter 155 may be equal to or higher than the time taken by phase control circuit 60 to react to a switch of the stop signal STOP (i.e., to start or stop the operation of the charge pump circuit 52).

[0088] In embodiments, in response to a switch of the first inverted stop signal STOP_N from the respective low logic value to the respective high logic value, second inverter 155 switches the second inverted stop signal STOP_NN from the respective high logic value to the respective low logic value in a time interval of, for example, tens of nanoseconds, in particular included between 20 ns and 100 ns.

[0089] In response to a switch of the first inverted stop signal STOP_N from the respective high logic value to the respective low logic value, second inverter 155 switches the second inverted stop signal STOP_NN from the respective low logic value to the respective high logic value in a time interval of, for example, tens of nanoseconds, in particular included between 20 ns and 100 ns.

[0090] In practice, second inverter 155 has a low driving capability so that second terminal 153B of second regulation capacitor 153 is driven from a low logic value to a high logic value, and from a high logic value to the low logic value, with a slope that may last tens of nanoseconds (i.e., slower than the response time of the first inverter 75).

[0091] In use, similarly to what is described with reference to FIG. 3 for the first regulation capacitor 70, a switch in the stop signal STOP, and therefore in the second inverted stop signal STOP_NN, causes a charge equal to C.sub.B2.Math.V.sub.DD to be slowly sunk from or injected to output node 54 of voltage regulator 150.

[0092] In embodiments, when the stop signal STOP switches from the respective high to the respective low logic value, also the second stop inverted signal STOP_NN switches from the respective high to the respective low logic value, thereby sinking a charge C.sub.B2.Math.V.sub.DD from output node 54, limiting a voltage rising thereof. On the other hand, when the stop signal STOP switches from the respective low to the respective high logic value, also the second stop inverted signal STOP_NN switches from the respective low to the respective high logic value, thereby injecting a charge C.sub.B2.Math.V.sub.DD to output node 54; thus, helping to sustain the consumption from an external load (e.g., load 55). In practice, the second inverter 155 has a response time higher than the first inverter 75 allowing a further reduction to the ripples of output voltage V.sub.OUT, in particular, if voltage regulator 150 is coupled at the output to a low-current load.

[0093] The present voltage regulator may be incorporated into an electronic device to provide a stable voltage source within the electronic device.

[0094] For example, FIG. 7 shows a block diagram of a memory 200, including, by way of example, voltage regulator 50 of FIG. 3. However, memory 200 may include voltage regulator 150 of FIG. 6.

[0095] Memory 200 is a non-volatile memory of known type, in particular here a phase-change type of memory (PCM), which can be integrated within an electronic apparatus (e.g., a smartphone, laptop, camera, wearable device, etc., here not shown) and coupled thereto through a multiplexing bus 201.

[0096] Memory 200 includes a PCM memory array 202 having a plurality of memory cells arranged in a plurality of rows and columns; a row decoder 204 and a column decoder 206 configured to select, in use, a memory cell of the PCM memory array 202, from an address signal ADDRESS, on which to perform an operation (e.g., read or write); voltage regulators 208 coupled to the row decoder 204; an internal clock 210; a finite state machine (FSM) 211; a digital-to-analog converter, DAC, 212; several internal registers 214; and a sensing circuit 216 configured to read a state of an addressed memory cell.

[0097] FSM 211 controls the internal operations of the memory 200 (e.g., boot, write, read, etc.) and manages data reception and transmission through the multiplexing bus 201.

[0098] Memory 200 further includes a programming circuit 220, coupled to column decoder 206, FSM 211, and DAC 212. Programming circuit 220 is also coupled to output node 54 of voltage regulator 50 and receives therefrom output voltage V.sub.OUT.

[0099] Programming circuit 220 is configured to change the state (i.e., write operation) of an addressed memory cell of the PCM memory array 202. In embodiments, to change the state of a memory cell, programming circuit 220 uses a high voltage (i.e., the output voltage V.sub.OUT of the voltage regulator 50) to generate a high programming current.

[0100] Voltage regulators 50, 150 generate a more stable output voltage with respect to known voltage regulators (for example, the known voltage regulator 1 of FIG. 1), allowing programming circuit 220 to generate a stable programming current. Therefore, writing errors in memory 200 may be avoided. Therefore, memory 200 has high reliability.

[0101] It is clear that voltage regulators 50, 150 may be subject to modifications and variations without departing the scope of the present invention, as defined in the attached claims. For example, regulation capacitors 70, 153 may be formed by any electronic device behaving as a capacitive element, for example, a transistor (e.g., an NMOS transistor having the gate connected to output node 54 and having a source, a drain and a bulk mutually connected to each other and the output of inverters 75, 155. Moreover, capacitors 70, 153 may form a filter including other electric elements, here not shown, either passive or active, such as resistors, depending on the specific application.

[0102] For example, FIG. 8 shows a different embodiment of the comparator, here indicated by 258, of voltage regulators 50,150. Comparator 258 includes a voltage divider 260 coupled between output voltage V.sub.OUT and ground 57 and having a dividing node 261, and a comparator amplifier 263 having a first input at reference voltage V.sub.REF, a second input coupled to dividing node 261 and providing at the output the stop signal STOP.

[0103] The voltage divider 260 is formed by a first branch 260A, including here an RC parallel circuit and coupled between the output node 54 and the dividing node 261, and a second branch 260B, including here an RC parallel circuit and coupled between the dividing node 261 and the ground 57.

[0104] In practice, reference voltage V.sub.REF may be equal to output voltage V.sub.OUT or a function of output function V.sub.OUT, depending on the specific application.

[0105] The practical implementation of the described embodiments and variations is within the abilities of those skilled in the art based on the functional indications given hereabove.

[0106] Although the description has been described in detail, it should be understood that various changes, substitutions, and alterations may be made without departing from the spirit and scope of this disclosure as defined by the appended claims. The same elements are designated with the same reference numbers in the various figures. Moreover, the scope of the disclosure is not intended to be limited to the particular embodiments described herein, as one of ordinary skill in the art will readily appreciate from this disclosure that processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, may perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

[0107] The specification and drawings are, accordingly, to be regarded simply as an illustration of the disclosure as defined by the appended claims, and are contemplated to cover any and all modifications, variations, combinations, or equivalents that fall within the scope of the present disclosure.