SIGNAL DETECTOR CIRCUIT AND SIGNAL DETECTION METHOD

Abstract

A signal detector circuit includes a signal peak detector circuit, a reference voltage generation circuit, and a comparator circuit. The signal peak detector circuit is arranged to receive a plurality of differential voltage input signals, and generate a single-ended peak signal according to the plurality of differential voltage input signals. The reference voltage generation circuit is arranged to generate a single-ended reference voltage signal. The comparator circuit is arranged to receive the single-ended peak signal and the single-ended reference voltage signal, and compare the single-ended peak signal with the single-ended reference voltage signal to generate a signal detection result.

Claims

1. A signal detector circuit, comprising: a signal peak detector circuit, arranged to receive a plurality of differential voltage input signals, and generate a single-ended peak signal according to the plurality of differential voltage input signals; a reference voltage generation circuit, arranged to generate a single-ended reference voltage signal; and a comparator circuit, arranged to receive the single-ended peak signal and the single-ended reference voltage signal, and compare the single-ended peak signal with the single-ended reference voltage signal, to generate a signal detection result.

2. The signal detector circuit of claim 1, wherein the signal peak detector circuit samples and holds the plurality of differential voltage input signals to generate the single-ended peak signal.

3. The signal detector circuit of claim 2, wherein the plurality of differential voltage input signals comprises a first differential voltage input signal and a second differential voltage input signal, and the signal peak detector circuit comprises: a first switch circuit, having a first end and a second end, wherein the first end of the first switch circuit is arranged to receive the first differential voltage input signal, and the first switch circuit is conductive according to a first control signal, for transmitting the first differential voltage input signal to the second end of the first switch circuit; a second switch circuit, having a first end and a second end, wherein the first end of the second switch circuit is arranged to receive the second differential voltage input signal, and the second switch circuit is conductive according to a second control signal, for transmitting the second differential voltage input signal to the second end of the second switch circuit; and a capacitance, having a first end and a second end, and arranged to output the single-ended peak signal, wherein the first end of the capacitance is coupled to the second end of the first switch circuit and the second end of the second switch circuit, and the second end of the capacitance is coupled to a reference voltage.

4. The signal detector circuit of claim 3, wherein the first control signal is the second differential voltage input signal, and the second control signal is the first differential voltage input signal.

5. The signal detector circuit of claim 4, wherein when the first differential voltage input signal is a first level and the second differential voltage input signal is a second level that is lower than the first level, the first switch circuit is conductive and the second switch circuit is not conductive, and the single-ended peak signal is the first differential voltage input signal.

6. The signal detector circuit of claim 4, wherein when the first differential voltage input signal is a first level and the second differential voltage input signal is a second level that is higher than the first level, the first switch circuit is not conductive and the second switch circuit is conductive, and the single-ended peak signal is the second differential voltage input signal.

7. A signal detection method, comprising: receiving a plurality of differential voltage input signals; generating a single-ended peak signal according to the plurality of differential voltage input signals; generating a single-ended reference voltage signal; and comparing the single-ended peak signal with the single-ended reference voltage signal to generate a signal detection result.

8. The signal detection method of claim 7, wherein generating the single-ended peak signal according to the plurality of differential voltage input signals comprises: sampling and holding the plurality of differential voltage input signals to generate the single-ended peak signal.

9. The signal detection method of claim 8, wherein the plurality of differential voltage input signals comprises a first differential voltage input signal and a second differential voltage input signal, and sampling and holding the plurality of differential voltage input signals to generate the single-ended peak signal comprises: conducting a first switch circuit according to a first control signal, for transmitting the first differential voltage input signal to a first end of a capacitance; and conducting a second switch circuit according to a second control signal, for transmitting the second differential voltage input signal to the first end of the capacitance; wherein the capacitance is arranged to output the single-ended peak signal, and a second end of the capacitance is coupled to a reference voltage.

10. The signal detection method of claim 9, wherein the first control signal is the second differential voltage input signal and the control signal is the first differential voltage input signal.

11. The signal detection method of claim 10, wherein when the first differential voltage input signal is a first level and the second differential voltage input signal is a second level that is lower than the first level, the first switch circuit is conductive and the second switch circuit is not conductive, and the single-ended peak signal is the first differential voltage input signal.

12. The signal detection method of claim 10, wherein when the first differential voltage input signal is a first level and the second differential voltage input signal is a second level that is higher than the first level, the first switch circuit is not conductive and the second switch circuit is conductive, and the single-ended peak signal is the second differential voltage input signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIG. 1 is a diagram illustrating a high speed data processing architecture according to an embodiment of the present invention.

[0010] FIG. 2 is a diagram illustrating a signal detector circuit according to an embodiment of the present invention.

[0011] FIG. 3 is a diagram illustrating a signal peak detector circuit according to an embodiment of the present invention.

[0012] FIG. 4 is a diagram illustrating a single-ended peak signal generated by the signal peak detector circuit shown in FIG. 3 according to an embodiment of the present invention.

[0013] FIG. 5 is a diagram illustrating associated signals of the signal detector circuit shown in FIG. 2 according to an embodiment of the present invention.

[0014] FIG. 6 is a flow chart of a signal detection method according to an embodiment of the present invention.

DETAILED DESCRIPTION

[0015] FIG. 1 is a diagram illustrating a high speed data processing architecture 10 according to an embodiment of the present invention. As shown in FIG. 1, the high speed data processing architecture 10 may include a plurality of terminals 100 and 110, a signal detector circuit 120, and a high speed data processing circuit 130 (e.g. a high speed data amplifier and a clock data recovery (DCR) circuit), wherein the terminals 100 and 110 may be two terminal resistors, but the present invention is not limited thereto. A first end of the terminal 100 maybe coupled to a common mode voltage VCM, and a second end of the terminal 100 may be arranged to receive a differential voltage input signal A_P corresponding to high speed input data, wherein the common mode voltage VCM is the optimum common mode operating voltage of the high speed data processing circuit 130. A first end of the terminal 110 maybe coupled to the common mode voltage VCM, and a second end of the terminal 110 may be arranged to receive another differential voltage input signal A_N corresponding to the high speed input data. The signal detector circuit 120 may be coupled to the second end of the terminal 100 and the second end of the terminal 110, and may be arranged to receive the differential voltage input signals A_P and A_N, and determine whether the differential voltage input signals A_P and A_N are noise. The high speed data processing circuit 130 may be coupled to the second end of the terminal 100 and the second end of the terminal 110, and may be arranged to process valid data transmitted by the differential voltage input signals A_P and A_N.

[0016] FIG. 2 is a diagram illustrating a signal detector circuit 20 according to an embodiment of the present invention, wherein the signal detector circuit 120 shown in FIG. 1 may be implemented by the signal detector circuit 20 shown in FIG. 2. As shown in FIG. 2, the signal detector circuit 20 may include a signal peak detector circuit 200, a reference voltage generation circuit 210, and a comparator circuit 220. The signal peak detector circuit 200 may be arranged to receive the differential voltage input signals A_P and A_N, and sample and hold the differential voltage input signals A_P and A_N, to generate a single-ended peak signal PEAK. It should be noted that the signal peak detector circuit 200 only operates according to the differential voltage of the input signal (i.e. the differential voltage input signals A_P and A_N), and will not perform subsequent operations using the common mode voltage of the input signal. As a result, the signal peak detector circuit 200 utilizes architecture that does not operate according to the input common mode voltage, and an additional common mode voltage generation circuit is therefore not required for the signal detector circuit 20. In this way, the chip area occupied by the common mode voltage generation circuit can be saved, and parasitic capacitance generated by the common mode voltage generation circuit can be avoided. In addition, in order to reduce the parasitic capacitance of the input terminal, the signal peak detector circuit 200 adopts single-ended detection to generate the single-ended peak signal PEAK. In this way, compared with a signal detector circuit with architecture that operates according to the common mode voltage, the signal detector circuit 10 can reduce the parasitic capacitance of the input terminal by half. As a result, the signal quality of high speed data transmission can be improved.

[0017] The reference voltage generation circuit 210 may be arranged to generate a single-ended reference voltage signal REF. Since the signal peak detector circuit 200 utilizes architecture that does not operate according to the input common mode voltage, the reference voltage generation circuit 210 only needs to generate the single-ended reference voltage signal REF according to circuit design requirements, without considering the problem of common mode voltage variation between the single-ended reference voltage signal REF and the single-ended peak signal PEAK. The comparator circuit 220 has a positive end coupled to the signal peak detector circuit 200 and a negative end coupled to the reference voltage generation circuit 210, and may be arranged to receive the single-ended peak signal PEAK and the single-ended reference voltage signal REF, and compare the single-ended peak signal PEAK with the single-ended reference voltage signal REF to generate a signal detection result COMP, wherein it is determined whether the differential voltage input signals A_P and A_N are noise according to the signal detection result COMP.

[0018] FIG. 3 is a signal peak detector circuit 30 according to an embodiment of the present invention, wherein the signal peak detector circuit 200 shown in FIG. 2 may be implemented by the signal peak detector circuit 30 shown in FIG. 3. As shown in FIG. 3, the signal peak detector circuit 30 may include a switch circuit 300, a switch circuit 310, and a capacitance 320, wherein the switch circuits 300 and 310 may be implemented by active components (e.g. transistors). The switch circuit 300 has a first end and a second end, wherein the first end of the switch circuit 300 may be arranged to receive the differential voltage input signal A_P, and the switch circuit 300 may determine whether to be conductive according to the differential voltage input signal A_N, in order to transmit the differential voltage input signal A_P to the second end of the switch circuit 300. The switch circuit 310 has a first end and a second end, wherein the first end of the switch circuit 310 may be arranged to receive the differential voltage input signal A_N, and the switch circuit 310 may determine whether to be conductive according to the differential voltage input signal A_P, in order to transmit the differential voltage input signal A_N to the second end of the switch circuit 310. As a result, the differential voltage input signal A_P received by the switch circuit 300 further acts as a control signal of the switch circuit 310, and the differential voltage input signal A_N received by the switch circuit 310 further acts as a control signal of the switch circuit 300. The capacitance 320 has a first end and a second end, and may be arranged to output the single-ended peak signal PEAK, wherein the first end of the capacitance 320 may be coupled to the second end of the switch circuit 300 and the second end of the switch circuit 310, and the second end of the capacitance 320 may be coupled to a reference voltage (i.e. a ground voltage GND).

[0019] In this embodiment, when the differential voltage input signal A_P is a high level (labeled as “1”) and the differential voltage input signal A N is a low level (labeled as “0”) , the switch circuit 300 is conductive and the switch circuit 310 is not conductive, and the single-ended peak signal PEAK is the differential voltage input signal A_P at this point. When the differential voltage input signal A_P is the low level and the differential voltage input signal A_N is the high level, the switch circuit 300 is not conductive and the switch circuit 310 is conductive, and the single-ended peak signal PEAK is the differential voltage input signal A_N at this point. In this way, the signal peak detector circuit 30 may obtain the single-ended peak signal PEAK via sample and hold of the switch circuits 300 and 310.

[0020] FIG. 4 is a diagram illustrating the single-ended peak signal PEAK generated by the signal peak detector circuit 30 shown in FIG. 3 according to an embodiment of the present invention, wherein the horizontal axis of the diagram represents time, and the vertical axis of the diagram represents voltage. As shown in FIG. 4, when the differential voltage input signal A_P is the high level and the differential voltage input signal A_N is the low level, the single-ended peak signal PEAK is the differential voltage input signal A_P. When the differential voltage input signal A_P is the low level and the differential voltage input signal A_N is the high level, the single-ended peak signal PEAK is the differential voltage input signal A_N. For brevity, similar descriptions for this embodiment are not repeated in detail here.

[0021] FIG. 5 is a diagram illustrating associated signals of the signal detector circuit 20 shown in FIG. 2 according to an embodiment of the present invention, wherein the horizontal axis of the diagram represents time, and the vertical axis of the diagram represents voltage. As shown in FIG. 5, the single-ended peak signal PEAK is generated by signal-ended detection, and the single-ended reference voltage signal REF may be generated according to circuit design requirements. It is determined whether the differential voltage input signals A_P and A_N are noise according to the signal detection result COMP generated by the comparator circuit 220. For example, in response to the signal detection result COMP indicating that the voltage value of the single-ended peak signal PEAK is smaller than that of the single-ended reference voltage signal REF, the differential voltage input signals A_P and A_N will be determined as noise. Otherwise, in response to the signal detection result COMP indicating that the voltage value of the single-ended peak signal PEAK is not smaller than that of the single-ended reference voltage signal REF, the differential voltage input signals A_P and A_N will be determined as valid signals from other devices. For brevity, similar descriptions for this embodiment are not repeated in detail here.

[0022] FIG. 6 is a flow chart of a signal detection method according to an embodiment of the present invention. Provided that the result is substantially the same, the steps are not required to be executed in the exact order shown in FIG. 6. For example, the signal detection method shown in FIG. 6 may be employed by the signal detector signal 20 shown in FIG. 2, wherein the signal peak detector circuit 200 in the signal detector signal 20 is implemented by the signal peak detector circuit 30 shown in FIG. 3.

[0023] In Step S600, the signal peak detector circuit 30 receives the differential voltage input signals A_P and A_N.

[0024] In Step S602, the signal peak detector circuit 30 determines whether to conduct a switch circuit (e.g. the switch circuit 300) in the signal peak detector circuit 30 according to the differential voltage input signal A_N, in order to transmit the differential voltage input signal A_P to the first end of the capacitance 320 for acting as the single-ended peak signal PEAK.

[0025] In Step S604, the signal peak detector circuit 30 determines whether to conduct another switch circuit (e.g. the switch circuit 310) in the signal peak detector circuit 30 according to the differential voltage input signal A_P, in order to transmit the differential voltage input signal A_N to the first end of the capacitance 320 for acting as the single-ended peak signal PEAK.

[0026] In Step S606, the reference voltage generation circuit 210 generates the single-ended reference voltage signal REF.

[0027] In Step S608, the comparator circuit 220 compares the single-ended peak signal PEAK with the single-ended reference voltage signal REF to generate the signal detection result COMP.

[0028] Since a person skilled in the pertinent art can readily understand details of the steps after reading above paragraphs directed to the signal detector circuit 20 and the signal peak detector circuit 30, further description is omitted here for brevity.

[0029] In summary, since the signal detector circuit of the present invention utilizes architecture that does not operate according to the input common mode voltage, an additional common mode voltage generation circuit is not required, and a reference voltage generation circuit to make the common mode voltage of the differential reference voltage signal the same as that of the differential input signal is also not required. In this way, the signal detector circuit of the present invention can reduce the amount of parasitic capacitance affecting the high speed signal to maintain the signal quality of high speed data transmissions while reducing the chip area. In addition, the signal detector circuit of the present invention adopts single-ended detection. As a result, compared with a signal detector circuit with architecture related to the common mode voltage, the signal detector circuit of the present invention can reduce the parasitic capacitance of the input terminal by half.

[0030] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.