SIGMA DELTA ANALOG-TO-DIGITAL CONVERTER AND METHOD FOR ELIMINATING IDLE TONES OF SIGMA DELTA ANALOG-TO-DIGITAL CONVERTER

Abstract

A Sigma Delta analog-to-digital converter (ADC) and a method for eliminating idle tones of the Sigma Delta ADC are provided. The Sigma Delta ADC includes a loop filter, a quantizer, an adder and a digital-to-analog converter (DAC). The loop filter performs filtering on a difference between an analog input signal and an analog feedback signal to generate a filtered signal. The quantizer is coupled to the loop filter, and generates a digital output signal according to the filtered signal. The adder is coupled to the quantizer, and adds a digital dithering signal to the digital output signal to generate a digital feedback signal. The DAC is coupled to the loop filter, and generates the analog feedback signal according to the digital feedback signal.

Claims

1. A Sigma Delta analog-to-digital converter (ADC), comprising: a loop filter, configured to perform filtering on a difference between an analog input signal and an analog feedback signal to generate a filtered signal; a quantizer, coupled to the loop filter, configured to generate a digital output signal according to the filtered signal; an adder, coupled to the quantizer, configured to add a digital dithering signal to the digital output signal, to generate a digital feedback signal; and a digital-to-analog converter (DAC), coupled to the loop filter, configured to generate the analog feedback signal according to the digital feedback signal.

2. The Sigma Delta ADC of claim 1, wherein power of the digital dithering signal in a signal band is less than power of the digital dithering signal outside the signal band.

3. The Sigma Delta ADC of claim 1, wherein the digital dithering signal comprises an out-band tone signal outside a signal band of the Sigma Delta ADC.

4. The Sigma Delta ADC of claim 1, wherein the quantizer is an N-bit quantizer, the adder is an N-bit adder, and N is a positive integer.

5. The Sigma Delta ADC of claim 4, further comprising: a digital signal processing circuit, coupled to the adder, configured to process M-bit dithering data for generating N-bit dithering data to be the digital dithering signal, wherein M is a positive integer greater than N.

6. A method for eliminating idle tones of a Sigma Delta analog-to-digital converter (ADC), comprising: utilizing a loop filter of the Sigma Delta ADC to perform filtering on a difference between an analog input signal and an analog feedback signal to generate a filtered signal; utilizing a quantizer of the Sigma Delta ADC to generate a digital output signal according to the filtered signal; utilizing an adder of the Sigma Delta ADC to add a digital dithering signal to the digital output signal, to generate a digital feedback signal; and utilizing a digital-to-analog converter (DAC) of the Sigma Delta ADC to generate the analog feedback signal according to the digital feedback signal.

7. The method of claim 6, wherein power of the digital dithering signal in a signal band is less than power of the digital dithering signal outside the signal band.

8. The method of claim 6, wherein the digital dithering signal comprises an out-band tone signal outside a signal band of the Sigma Delta ADC.

9. The method of claim 6, wherein the quantizer is an N-bit quantizer, the adder is an N-bit adder, and N is a positive integer.

10. The method of claim 9, further comprising: utilizing a digital signal processing circuit to process M-bit dithering data for generating N-bit dithering data to be the digital dithering signal, wherein M is a positive integer greater than N.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1 is a diagram illustrating a Sigma Delta analog-to-digital converter (ADC) according to an embodiment of the present invention.

[0011] FIG. 2 is a working flow of a method for eliminating idle tones of a Sigma Delta ADC according to an embodiment of the present invention.

DETAILED DESCRIPTION

[0012] FIG. 1 is a diagram illustrating a Sigma Delta analog-to-digital converter (ADC) 10 according to an embodiment of the present invention. As shown in FIG. 1, the Sigma Delta ADC 10 may comprise a loop filter 110, a quantizer such as an N-bit quantizer 120, an adder such as an N-bit adder 130, and a digital-to-analog converter (DAC) 140, where N is a positive integer. In this embodiment, N may be a positive integer greater than one, and the Sigma Delta ADC 10 may further comprise a decoder 150 and a data weighted averaging (DWA) logic circuit 160. In some embodiments, N may be equal to one (e.g., utilizing a single-bit quantizer architecture), and the decoder 150 and the DWA logic circuit 160 may be omitted. Idle tones are more likely to occur in high specification (e.g., low noise) architecture, however, where implementation of such architecture typically adopts a multi-bit quantizer, rather than adopting a single-bit quantizer. Furthermore, in comparison with utilizing the multi-bit quantizer, quantization noise generated by utilizing the single-bit quantizer is higher, and is therefore less likely to introduce the idle tones. As the present invention focuses on improving architecture which has a risk of generating the idle tones, embodiments of the present invention illustrate the architecture utilizing the multi-bit quantizer, but the present invention is not limited thereto.

[0013] In this embodiment, the loop filter 110 may utilize a first input terminal thereof (which is labeled “+” in FIG. 1 for brevity) to receive an analog input signal Ain, and utilize a second input terminal thereof (which is labeled “-” in FIG. 1 for brevity) to receive an analog feedback signal Afb from the DAC 140, where the loop filter 110 may be configured to perform filtering on a difference between the analog input signal Ain and the analog feedback signal Afb to generate a filtered signal Aft. The N-bit quantizer 120 is coupled to the loop filter 110 in order to receive the filtered signal Aft, and may be configured to generate a digital output signal Dout according to the filtered signal Aft (e.g., outputting a corresponding digital code according to a voltage level of the filtered signal Aft). The N-bit adder 130 is coupled to the N-bit quantizer 120 in order to receive the digital output signal Dout, and may receive a digital dithering signal Dn from a digital signal processing (DSP) circuit 170, and add the digital dithering signal Dn to the digital output signal Dout for generating a digital feedback signal D1 (e.g., D1 = Dout + Dn). The DAC 140 is coupled to the loop filter 110, and may be configured to generate the analog feedback signal Afb according to the digital feedback signal D1. Different digital codes may respectively correspond to different feedback charges, currents or voltages, so the DAC 140 may output a corresponding feedback charge, current or voltage according to a digital code of the digital feedback signal D1.

[0014] The DAC 140 may comprise a plurality of DAC units (e.g., 2.sup.N DAC units). In this embodiment, the decoder 150 may perform a binary-to-thermometer conversion on the digital feedback signal D1, to convert the digital feedback signal D1 indicated by a binary code into a digital feedback signal D2 indicated by a thermometer code. In detail, the digital feedback signal D2 indicated by the thermometer code may comprise 2.sup.N bits, where the 2.sup.N bits correspond to the 2.sup.N DAC units, respectively. For example, the DAC 140 may control the 2.sup.N DAC units according to logic values of the 2.sup.N bits, respectively. In practice, feedback signals provided by the plurality of DAC units are not exactly identical. In order to prevent mismatch of the DAC units from introducing harmonic tones in a signal band, the DWA logic circuit 160 may perform logic operations on the digital feedback signal D2 to generate a digital feedback signal D2′, in order to make power of the harmonic tones introduced by component mismatch be uniformly dispersed over multiple frequencies (e.g., make respective DAC units substantially have the same frequency of usage). Those skilled in this art can understand detailed implementation of the decoder 150 and the DWA logic circuit 160 shown in FIG. 1 according to the above description, and related details are therefore omitted here for brevity.

[0015] In the embodiment of FIG. 1, the Sigma Delta ADC 10 operates under oversampling. For example, an operation frequency (e.g., a sampling rate of sampling the analog input signal Ain) of the Sigma Delta ADC 10 is two or more times the bandwidth of the signal band. As shown in FIG. 1, a signal path constituted by the loop filter 110, the N-bit quantizer 120, the N-bit adder 130, the decoder 150, the DWA logic circuit 160 and the DAC 140 forms a negative feedback loop. Under the operations of oversampling and negative feedback, the Sigma Delta ADC 10 may iteratively correct an error between the analog feedback signal Afb and the analog input signal Ain, to convert the analog input signal Ain into the digital output signal Dout. When the analog input signal Ain is extremely small or equal to zero (for example, the analog input signal Ain is fixed at a direct current (DC) voltage level), if the digital dithering signal is zero (e.g., the DSP circuit 170 is temporarily disabled), a value of the digital output signal Dout may be transmitted backwards without any change (i.e., the digital feedback signal D1 is equal to the digital output signal Dout), and the digital output signal Dout under this condition will be periodic. More particularly, when the fixed DC voltage level of the analog input signal Ain falls in a DC interval, the process of negative feedback may be periodic in a longer cycle, thereby generating low frequency tones (e.g., the idle tones mentioned above).

[0016] By comparison, when the DSP circuit 170 provides a non-zero digital dithering signal Dn to break a periodicity in the negative feedback (or shift this periodicity to high frequencies such as outside of the signal band), the occurrence of the idle tones in the signal band can be avoided. In order to prevent the digital dithering signal Dn from severely impacting a signal-to-noise ratio (SNR) of the Sigma Delta ADC 10, power of the digital dithering signal Dn in the signal band needs to be properly designed. In this embodiment, the DSP circuit 170 may generate the digital dithering signal Dn according to the dithering data Dm. For example, the dithering data Dm may be M-bit dithering data, and the DSP circuit 170 may process the M-bit dithering data for generating N-bit dithering data to be the digital dithering signal Dn, where M is a positive integer greater than N. In some embodiments, the dithering data Dm may be generated by a random number generator, and the DSP circuit 170 may perform M-bit-to-N-bit conversion on the dithering data Dm and make power of the digital dithering signal Dn in the signal band (which may be regarded as a noise level of the Sigma Delta ADC 10 in the signal band) be less than power of the digital dithering signal Dn outside the signal band (which may be regarded as a noise level of the Sigma Delta ADC 10 outside the signal band) via digital signal processing (e.g., Sigma Delta modulation or high pass filtering).

[0017] In some embodiments, the digital dithering signal Dn may comprise an out-band (e.g., out-of-band) tone signal outside the signal band. For example, the dithering data Dm may be a single tone signal with high resolution, where a frequency of this single tone signal is located outside the signal band. The DSP circuit 170 may utilize digital signal processing therein (e.g., Sigma Delta modulation) to suppress the power inside the signal band as much as possible during the M-bit-to-N-bit conversion, to guarantee that the noise level inside the signal band will not be greatly increased due to the digital dithering signal Dn.

[0018] As the dithering data Dm and the digital dithering signal Dn are obtained by processing in the digital domain, and the derived total power of the dithering data Dm may be precisely controlled by a higher number of bits (e.g., M bits), the power of the digital dithering signal Dn in respective bands (e.g., a total noise power of an overall system of the Sigma Delta ADC 10) can be precisely controlled, to ensure that the SNR of the Sigma Delta ADC 10 will not be severely impacted by the digital dithering signal Dn.

[0019] FIG. 2 is a working flow of a method for eliminating idle tones of a Sigma Delta ADC (e.g., the Sigma Delta ADC 10 shown in FIG. 1, where the circuit connection and signal transfer relationships mentioned in FIG. 2 may refer to the configuration illustrated in FIG. 1) according to an embodiment of the present invention. It should be noted that the working flow shown in FIG. 2 is for illustrative purposes only, and is not meant to be a limitation of the present invention. If the same result can be obtained, one or more steps may be added, deleted or modified in the working flow, and these steps do not have to be executed in the exact order shown in FIG. 2.

[0020] In Step S210, the Sigma Delta ADC may utilize a loop filter therein to perform filtering on a difference between an analog input signal and an analog feedback signal to generate a filtered signal.

[0021] In Step S220, the Sigma Delta ADC may utilize a quantizer therein to generate a digital output signal according to the filtered signal.

[0022] In Step S230, the Sigma Delta ADC may utilize an adder therein to add a digital dithering signal to the digital output signal, to generate a digital feedback signal.

[0023] In Step S240, the Sigma Delta ADC may utilize a DAC therein to generate the analog feedback signal according to the digital feedback signal.

[0024] To summarize, the embodiments of the present invention add the dithering signal in the digital domain of the Sigma Delta ADC 10, enabling the control related to the dithering signal to be performed in a digital manner. In comparison with adding a dithering signal in an analog domain of an overall system, such as the input terminal of the loop filter 110 or the input terminal of the N-bit quantizer 120, the embodiments of the present invention do not need to further design a high specification DAC for adding a dithering signal in the analog domain, and the present invention is less likely to sacrifice an input dynamic range of the overall system in order to add the dithering signal. In addition, the embodiments of the present invention can properly operate under various conditions of process variation. Thus, it is not necessary to perform additional modification in response to the process variation. The present invention can prevent the occurrence of the idle tones introducing no or less side effects, thereby solving the problem of the related art.

[0025] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.