ELECTRONIC CIRCUIT FOR TRIPLING FREQUENCY

Abstract

In an embodiment, a circuit for tripling frequency is configured to receive an input voltage (V.sub.in) having a sinusoidal shape and a base frequency. The circuit has a first and a second transistor pair that are cross-coupled, and a trans-characteristics f(V.sub.in) approximating a polynomial nominal trans-characteristic given by

[00001]$f\left(V_{in}\right)=\left(\frac{3}{A}{V}_{in}-\frac{4}{A^3}{V}_{in}^3\right)g_m$

where A represents an amplitude of the input voltage and g.sub.m is a transconductance of transistors of the first and second transistor pairs.

Claims

1. A frequency tripler circuit comprising: first, second, third and fourth input nodes; first and second output nodes; and first and second transistor pairs that are cross-coupled, wherein: the first transistor pair comprises first and second transistors having respective first and second conduction terminals and a respective control terminal, the second transistor pair comprises third and fourth transistors having respective first and second conduction terminals and a respective control terminal, the first conduction terminals of the first, second, third and fourth transistors are coupled together, the second conduction terminals of the first and fourth transistors are coupled together and to the first output node, the second conduction terminals of the second and third transistors are coupled together and to the second output node, the control terminal of the first transistor is coupled to the first input node and is configured to receive a first fraction of an input voltage decreased by an offset voltage, the control terminal of the second transistor is coupled to the second input node and is configured to receive a counter-phase of the first fraction of the input voltage decreased by the offset voltage, the control terminal of the third transistor is coupled to the third input node and is configured to receive a second fraction of the input voltage, the control terminal of the fourth transistor is coupled to the fourth input node and is configured to receive a counter-phase of the second fraction of the input voltage, the input voltage has a sinusoidal shape and a base frequency, and the first and second output nodes are configured to provide an output current having sinusoidal shape and an output frequency that is a triple of the base frequency.

2. The frequency tripler circuit of claim 1, wherein the first fraction is bigger than the second fraction.

3. The frequency tripler circuit of claim 2, wherein the first fraction is 0.5 and the second fraction is between 0.1 and 0.35.

4. The frequency tripler circuit of claim 2, wherein the offset voltage satisfies $\frac{2Vos}{\left(1-\alpha \right)}=\frac{\sqrt{3}}{2}A,$ wherein V.sub.OS represents the offset voltage, a represents the second fraction, and A represents an amplitude of the input voltage.

5. The frequency tripler circuit of claim 1, further comprising an envelope detector coupled to the first and second input nodes, the envelope detector configured to generate the offset voltage.

6. The frequency tripler circuit of claim 5, further comprising: an input transformer having a primary winding coupled between first and second input terminals and a secondary winding coupled between the first and second input nodes, the secondary winding having a central tap coupled to a first output of the envelope detector; and a divider network coupled between the first and second input nodes and having a central tap coupled to a second output of the envelope detector.

7. The frequency tripler circuit of claim 6, wherein the divider network comprises a first branch comprising first and second resistors and first and second capacitors.

8. The frequency tripler circuit of claim 7, wherein: the divider network comprises a second branch comprising a third capacitor coupled between the third and fourth input nodes; the first capacitor has a first terminal coupled to the first input node and a second terminal coupled to the first resistor and to the third input node; the second capacitor has a first terminal coupled to the second input node (23) and a second terminal coupled to the second resistor and to the fourth input node; and the first and second resistors are coupled together at the central tap of the divider network.

9. The frequency tripler circuit of claim 6, wherein the envelope detector comprises: an input differential pair coupled to the first and second input nodes; a first voltage generating network coupled between the input differential pair and the first output of the envelope detector; and a second voltage generating network coupled to the second output of the envelope detector.

10. The frequency tripler circuit of claim 1, further comprising: an input transformer having a primary winding coupled between first and second input terminals and a secondary winding coupled between the first and second input nodes, the secondary winding having a central tap; and a divider network coupled between the first and second input nodes, the divider network comprising: a first capacitor coupled between an intermediate node and the first input node, and a second capacitor coupled between the intermediate node and the second input node, wherein the offset voltage is based on a difference between a voltage at the central tap of the secondary winding of the input transformer and a voltage at the intermediate node.

11. The frequency tripler circuit of claim 1, further comprising an LC network coupled to the first and second transistor pairs, the LC network comprising a tail inductor and a shunt capacitor coupled in series.

12. The frequency tripler circuit of claim 1, wherein the first, second, third, and fourth transistors are bipolar transistors having the same emitter area.

13. The frequency tripler circuit of claim 1, further comprising a biasing current source coupled between the first conduction terminals of the first, second, third and fourth transistors and a reference terminal.

14. The frequency tripler circuit of claim 1, wherein the frequency tripler circuit has a trans-characteristic having a zero-crossing when a voltage at the first input node equal a voltage at the third input node.

15. The frequency tripler circuit of claim 1, further comprising an output transformer having a primary winding coupled between the first and second output nodes.

16. The frequency tripler circuit of claim 1, wherein: in a first mode of operation of the frequency tripler circuit, the first and second transistors are configured to be off, and the third and fourth transistors are configured to control the output current; in a second mode of operation of the frequency tripler circuit, the first and second transistors are configured to be on and subtract current from the first and second output nodes; and the frequency tripler circuit is configured to switch between the first and second modes of operation based on the input voltage.

17. A frequency tripler circuit comprising: first, second, third and fourth input nodes; first and second output nodes; first and second transistor pairs that are cross-coupled, wherein the first transistor pair comprises first and second transistors having respective first and second conduction terminals and a respective control terminal, wherein the second transistor pair comprises third and fourth transistors having respective first and second conduction terminals and a respective control terminal, wherein the first conduction terminals of the first, second, third and fourth transistors are coupled together, wherein the second conduction terminals of the first and fourth transistors are coupled together and to the first output node, wherein the second conduction terminals of the second and third transistors are coupled together and to the second output node, wherein the control terminal of the first transistor is coupled to the first input node, wherein the control terminal of the second transistor is coupled to the second input node, wherein the control terminal of the third transistor is coupled to the third input node, and wherein the control terminal of the fourth transistor is coupled to the fourth input node; and a voltage divider coupled between the first and second input nodes, the voltage divider comprising a first intermediate node coupled to the third input node, and a second intermediate node coupled to the fourth input node.

18. The frequency tripler circuit of claim 17, wherein the voltage divider comprises: a first capacitor coupled between the first input node and the first intermediate node; a first resistor coupled between the first intermediate node and a third intermediate node; a second resistor coupled between the third intermediate node and the second intermediate node; and a second capacitor coupled between the second intermediate node and the second input node.

19. The frequency tripler circuit of claim 18, wherein the voltage divider further comprises a third capacitor coupled between the first and second intermediate nodes.

20. The frequency tripler circuit of claim 17, further comprising an envelope detector having a first input capacitively coupled to the first input node, a second input capacitively couple to the second input node, and a first output coupled to a third intermediate node of the voltage divider.

21. The frequency tripler circuit of claim 20, wherein the envelope detector comprises: an input differential pair having fifth and sixth transistors having respective control terminals respectively coupled to the first and second inputs of the envelope detector; a first voltage generating network having an output coupled to the first output of the envelope detector; a second voltage generating network having an output coupled to a second output of the envelope detector, the second output of the envelope detector being coupled to the first and second input nodes; and an RC filter coupled between an output of the input differential pair and an input of the second voltage generating network.

22. The frequency tripler circuit of claim 21, wherein: the envelope detector further comprises a first current source coupled to the output of the input differential pair; the first voltage generating network comprises: a seventh transistor having a conduction path coupled to the first output of the envelope detector, an eighth transistor having a control terminal coupled to a control terminal of the seventh transistor, a ninth transistor having a conduction path coupled to the conduction path of the seventh transistor, a tenth transistor having a conduction pat coupled to a conduction of the eighth transistor and a control terminal coupled to a control terminal of the ninth transistor, and an eleventh transistor having a control terminal coupled to the conduction path of the eighth transistor and a conduction path coupled to the control terminals of the ninth and tenth transistors; and the second voltage generating network comprises: a twelfth transistor having a conduction path coupled to the second output of the envelope detector, a thirteenth transistor having a control terminal coupled to a control terminal of the twelfth transistor, a fourteenth transistor having a conduction path coupled to the conduction path of the twelfth transistor, a fifteenth transistor having a conduction path coupled a conduction path of the thirteenth transistor, and a control terminal coupled to a control terminal of the fourteenth transistor, and a sixteenth transistor having a control terminal coupled to the conduction path of the thirteenth transistor and a conduction path coupled to the control terminals of the fourteenth and fifteenth transistors.

23. The frequency tripler circuit of claim 22, wherein the fifth, sixth, seventh, eighth, eleventh, twelfth, thirteenth, and sixteenth transistors are bipolar transistors, and wherein the ninth, tenth, fourteenth, and fifteenth transistors are metal-oxide semiconductor field effect transistors (MOSFETs).

24. A method for tripling frequency, the method comprising: receiving an input voltage having a sinusoidal shape and a base frequency; and applying the input voltage to a tripler circuit comprising first and second transistor pairs that are cross-coupled, wherein the first transistor pair comprises a first and second transistors having respective first and second conduction terminals and a respective control terminal, wherein the second transistor pair comprises third and fourth transistors having respective first and second conduction terminals and a respective control terminal, wherein the first conduction terminal of the first, second, third and fourth transistors are coupled to a common node, wherein the second conduction terminal of the first and fourth transistors are coupled to a first output node, and wherein the second conduction terminal of the second and third transistors are coupled to a second output node, and wherein applying the input voltage to the tripler circuit comprises: applying a first fraction of the input voltage decreased by an offset voltage to the control terminal of the first transistor, applying a counter-phase of the first fraction of the input voltage decreased by the offset voltage to the control terminal of the second transistor, applying a second fraction of the input voltage to the control terminal of the third transistor, and applying a counter-phase of the second fraction of the input voltage to the control terminal of the fourth transistor; and generating an output current having sinusoidal shape and an output frequency that is a triple of the base frequency, wherein generating the output current comprises generating a first single-ended current at the first output node and generating a second single-ended current at the second output node.

25. The method of claim 24, wherein, in a first mode of operation of the tripler circuit, the first and second transistors are off and the first and second single-ended currents are governed by the third and fourth transistors, wherein, in a second mode of operation of the tripler circuit, the first and second transistors are on, the method further comprising selecting between the first and second modes of operation based on the input voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] For the understanding of the present invention, embodiments thereof are now described, purely as a non-limitative example, with reference to the drawings, wherein:

[0018] FIG. 1 shows a block diagram of the general structure of a frequency multiplier chain;

[0019] FIG. 2 is a circuit diagram of a known frequency multiplier;

[0020] FIGS. 3A and 3B are plots of quantities related to the circuit of FIG. 2;

[0021] FIG. 4 is a circuit diagram of a frequency tripler, according to an embodiment of the present invention;

[0022] FIG. 5 shows the plot of a desired trans-characteristic and the actual characteristic of the circuit of FIG. 4, according to an embodiment of the present invention;

[0023] FIG. 6 is a circuit diagram of a tripler device including the circuit of FIG. 4, according to an embodiment of the present invention;

[0024] FIG. 7 is a circuit diagram of an embodiment of a block of the tripler device of FIG. 6;

[0025] FIG. 8 shows plots of quantities related to the circuit of FIG. 4, according to an embodiment of the present invention; and

[0026] FIG. 9 shows comparative plots of the power spectrum obtained with the circuit of FIG. 4 and the circuit of FIG. 1.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0027] FIG. 4 shows a tripler circuit 20 that allows obtaining a high suppression of undesired harmonics, according to an embodiment of the present invention.

[0028] The tripler circuit 20 represents an implementation of an ideal transistor-based tripler circuit having a polynomial trans-characteristic f(V.sub.in) (later on also called ideal polynomial trans-characteristic) according to the following equation (1):

[00002]$\begin{array}{cc}f\left(V_{in}\right)=\left(\frac{3}{A}{V}_{in}-\frac{4}{A^3}{V}_{in}^3\right)g_m& \left(1\right)\end{array}$

where g.sub.m is the transconductance of the transistor in the tripler circuit (at a specific DC biasing condition).

[0029] In particular, as may be demonstrated with some calculation, the above ideal trans-characteristics allows a tripler circuit, receiving at its input a sinusoidal driving voltage:

V.sub.in=A sin(2πf.sub.0t)=A sin(ω.sub.0t)

having amplitude A and base frequency f.sub.o is able to generate an output current Io:

I.sub.o=f(V.sub.in)=g.sub.m sin(32πf.sub.0t)=g.sub.m sin(3ω.sub.0t)

having only the third harmonic (3f.sub.o).

[0030] FIG. 4 shows the structure of the tripler circuit 20 that has a trans-characteristics approximating the above polynomial trans-characteristics f(V.sub.in), as discussed later on.

[0031] In detail, with reference to FIG. 4, the tripler circuit 20 comprises a first and a second pair of transistors, cross-coupled to each other. In particular, the first pair of transistors comprises a first and a second transistor Q1, Q2, here of the bipolar NPN-type, and the second pair of transistors comprises a third and a fourth transistor Q3, Q4, here also of the bipolar NPN-type. Transistors Q1-Q4 have same parameters, in particular same emitter area.

[0032] In detail, the first and second transistors Q1, Q2 have emitter terminals coupled to each other and to a common node 21, base terminals coupled to a first and, respectively, a second input node 22, 23 and collector terminals coupled to a first and, respectively, a second output node 24, 25 supplying a first and, respectively, a second single-ended current Io− and Io+.

[0033] The third and fourth transistor Q3, Q4 have emitter terminals coupled to each other and to the common node 21, base terminals coupled to a third and, respectively, a fourth input node 27, 28, and collector terminals coupled to the second and, respectively, the first output node 25, 24.

[0034] A biasing current source 26, configured to generate bias current I.sub.b, is coupled between the common node 21 and ground.

[0035] The first and the second input nodes 22, 23 receive each a fraction equal to ½ of the input voltage V.sub.in, in counter-phase, both reduced by a DC voltage (offset voltage V.sub.os). The third and the fourth input nodes 27, 28 receive each an attenuation α/2 of the input voltage, in counter-phase, the attenuation α being selected so that, during operation, at low values of the input voltage V.sub.in and considering also the offset voltage V.sub.os, the first pair of transistors Q1, Q2 is still off, while the second pair of transistors Q3, Q4 are on, as discussed in detail below.

[0036] Specifically, the first input node 22 receives first voltage V1:

V1=V.sub.in/2−V.sub.os;

the second input node 23 receives voltage V2:

V2=−V.sub.in/2−V.sub.os;

the third input node 27 receives voltage V3:

V3=α.sub.Vin/2; and

the fourth input node 28 receives voltage V4:

V4=−αV.sub.in/2

where V.sub.os is the DC offset voltage and α is the attenuation, as indicated above.

[0037] The tripler circuit 20 of FIG. 4 operates as follows. As indicated above, at small values of the input voltage V.sub.in, the first and second transistors Q1, Q2 have low base-to-emitter biasing voltages and are off; thus the output currents I.sub.o+ and I.sub.o− are governed only by the third and fourth transistors Q3, Q4, approximating equation (1). When the value of the input voltage V.sub.in increases, the first and second transistors Q1, Q2 turn on, subtracting current from the output nodes 24, 25. In particular, after reaching their maximum amplitudes, the output differential current I.sub.o=I.sub.o+−I.sub.o+ reduces, reversing the slope of the trans-characteristic.

[0038] The trans-characteristic of the tripler circuit 20 of FIG. 4 is shown by curve A plotted in FIG. 5 with dotted line as normalized output current I.sub.on versus normalized input voltage V.sub.in/A. For reference, FIG. 5 shows also the ideal trans-characteristic (1) with continuous line B.

[0039] In particular, the normalized output current I.sub.on is the differential current I.sub.o+−I.sub.o+, normalized with respect to its maximum amplitude (equal to I.sub.b).

[0040] The values of attenuation α and offset voltage V.sub.os are selected so that the trans-characteristic of the tripler circuit 20 tracks the ideal polynomial trans-characteristic of equation (1), that is so that the trans-characteristic of the tripler circuit 20 is null at V.sub.in=0, then increases with a similar slope as the ideal polynomial trans-characteristic, then decreases again to zero and to negative values, following the ideal trans-characteristic. The opposite happens for negative values of V.sub.in.

[0041] In particular, the zero-crossings (besides of that at V.sub.in=0) of the trans-characteristic of the tripler circuit 20 occur when the voltage at the base terminal of the third transistor Q3 (at the third input node 27) equals the voltage at the base terminal of the first transistor Q1 (at the first input node 22) as well as when the voltage at the base terminal of the fourth transistor Q4 (at the fourth input node 28) equals the voltage at the base terminal of the second transistor Q2 (at the second input node 23), that is when condition (2) is satisfied:

[00003]$\begin{array}{cc}\pm \frac{V_{in}}{2}-V_{\mathrm{OS}}=\pm \alpha \frac{V_{in}}{2}.& \left(2\right)\end{array}$

[0042] The zero-crossings occur thus at the following values of the input voltage V.sub.in:

[00004]$\begin{array}{cc}{V}_{in}=\pm \frac{2V_{\mathrm{OS}}}{\left(1-\alpha \right)}.& \left(3\right)\end{array}$

[0043] On the other hand, the zero-crossings of the trans-characteristics (1) (besides of that at V.sub.in=0) occur at the following values of the input voltage V.sub.in:

[00005]$\begin{array}{cc}{V}_{in}=\pm \frac{\sqrt{3}}{2}A.& \left(4\right)\end{array}$

[0044] It follows that the trans-characteristic of the tripler circuit 20 and the ideal trans-characteristic have same zero-crossings when attenuation α and offset voltage V.sub.os satisfy the following condition:

[00006]$\begin{array}{cc}\frac{2V_{\mathrm{OS}}}{\left(1-\alpha \right)}=\frac{\sqrt{3}}{2}A.& \left(5\right)\end{array}$

[0045] Analysis of the derivatives of the ideal polynomial trans-characteristic (1) shows that its slope at the zero crossings at V.sub.in=±√{square root over (3)}A/2 is ±2 times that of the origin. Further circuit analysis proves that it is enough to design attenuation α=0.2 to have the slopes of the two trans-characteristics identical at zero crossings, such that the shape of the actual trans-characteristic of the tripler circuit 20 keeps as close as possible to the ideal one (see FIG. 5). However, circuit analysis proves that a value of attenuation a comprised in the range 0.1 to 0.35 allows the trans-characteristic of the tripler circuit 20 to suitably fit the plot of the ideal polynomial trans-characteristic (1). In fact, the spread of the value of attenuation α may be compensated through the offset voltage V.sub.os, as discussed below.

[0046] By fixing the value of attenuation α, the value of the offset voltage V.sub.os is obtained as a linear function of the amplitude A of the input voltage V.sub.in, based on condition (5).

[0047] In this case, also a non-optimal value of the attenuation α may be set, and the envelope detector operates as an open loop able to compensate and maintain the linear desired relationship of condition (5).

[0048] For example, FIG. 6 shows a tripler circuit, indicated by 30, comprising the tripler 20 of FIG. 5 and an envelope detector, according to an embodiment of the present invention.

[0049] In FIG. 6, an input transformer T1 has a primary winding 31 coupled between a first and a second circuit input 32, 33 and a secondary winding 35 coupled between the input nodes 22, 23 of the tripler circuit 20. The secondary winding 35 has a central tap 36 connected to a first output 37 of an envelope detector 38 and set at a first biasing voltage Vb1.

[0050] A voltage divider 40, of capacitive type, is coupled between the input nodes 22, 23 of the tripler circuit 20 and comprises a first branch 41 and a second branch 42.

[0051] The first branch 41 of the voltage divider 40 comprises a first capacitor 45, a first resistor 46, a second resistor 47 and a second capacitor 48 connected in series. The first and second capacitors 45, 48 have same capacitance C1; the first and second resistors 46, 47 have same resistance R.

[0052] The first branch 41 has a central tap between the first and second resistors 46, 47 coupled to a second output 50 of the envelope detector 38, which generates a second biasing voltage Vb2. The first branch 41 also has a first intermediate node 51 between the first capacitor 45 and the first resistor 46 and a second intermediate node 52 between the second resistor 47 and the second capacitor 48. The voltage difference Vb2-Vb1 forms the offset voltage V.sub.os of the tripler 20 of FIG. 5.

[0053] The second branch 42 of the voltage divider 40 comprises a third capacitor 54 coupled between the first and second intermediate nodes 51, 52. The third capacitor 54 has a capacitance C2. First and second intermediate nodes 51, 52 are also coupled to the third and, respectively, the fourth input node 27, 28 of the tripler circuit 20.

[0054] The first and second input nodes 22, 23 of the tripler circuit 20 are also coupled to a first, respectively a second input 55, 56 of the envelope detector 38 through respective capacitors 57, 58.

[0055] The tripler circuit 30 also comprises an output transformer T2 having a primary winding 61 coupled between the first and second output nods 24, 25 of the tripler 20 and a second winding 62 coupled between a first and second circuit outputs 64, 65; and an LC network 66 formed by a shunt capacitor 67 and a tail inductor 68 is coupled between the common node 21 of the tripler 20 and ground.

[0056] The first and second circuit outputs 64, 65 may be connected to an output buffer similar to the first buffer 4 of frequency multiplier system 1 of FIG. 1 and/or to a frequency multiplier such as the frequency doubler 5 of the frequency multiplier system 1 of FIG. 1.

[0057] In the tripler circuit 30 of FIG. 6, the first transformer T1 operates for line adaptation (as a balun transformer) and generates a differential signal (corresponding to input voltage V.sub.in of FIG. 4 and thus identified with the same reference) directly applied on the first and second input nodes 22, 23 of the tripler circuit 20 (and thus on the base terminals of the first and second transistors Q1, Q2). The differential signal V.sub.in is reduced by the attenuation α by the capacitive divider 40 and applied to the third and fourth input nodes 27, 28 of the tripler circuit 20 (and thus on the base terminals of the third and fourth transistors Q3, Q4).

[0058] The tail inductor 68 resonates with shunt equivalent capacitance existing at the common node 21 and the shunt capacitance 67 is sized sufficiently large to act as an AC-short at the operating frequency of common node 21, which is 2f.sub.o. In fact, LC network 66 allows the shunt parasitic capacitances at common node 21 to charge-discharge at high frequency using the current being exchanged with the tail inductor 68, hence not to lag behind the base voltages of the input transistors Q1-Q4 when operating at high input frequency.

[0059] FIG. 7 shows an exemplary implementation of envelope detector 38 generating the offset voltage V.sub.os that satisfies condition (5), according to an embodiment of the present invention.

[0060] In the specific implementation shown in FIG. 6, envelope detector 38 comprises an input differential pair 70 formed by a fifth and a sixth transistor Q5 and Q6 and driven by the input voltage V.sub.in. A current source 71, generating a second reference current 2I.sub.REF, twice the reference current I.sub.REF, is coupled to the emitter terminals of the fifth and sixth transistors Q5 and Q6 and to an averaging RC filter 72. The averaging filter RC 72 includes an averaging resistor 73 having resistance R.sub.E and is coupled to a first voltage generating network 75. First voltage generating network 75 comprises a first current generating branch 76 and a first current mirroring branch 77. First current generating branch 76 includes a first current source 80 generating reference current I.sub.REF and a transistor Q7; first current mirroring branch 77 includes a transistor Q8 that is base-coupled to transistor Q7 of the first current generating branch 76, has a collector terminal forming first output 37 of the envelope detector 38 and generates the first biasing voltage Vb1. A second voltage generating network 81, having the same basic structure of the first voltage generating network 75, has coupled transistors Q9 and Q10 and generates the second biasing voltage Vb2 at a collector of transistor Q9 coupled to the second output 50 of the envelope detector 38. The second voltage generating network 81 also includes a second current source 82 generating the reference current I.sub.REF.

[0061] A supply voltage V.sub.CC is applied to the collector terminals of the fifth and sixth transistors Q5 and Q6 and to supply nodes of the first and second voltage generating networks 75, 81. Supply voltage V.sub.CC is also applied to a central tap of the second transformer T2.

[0062] All transistors Q5-Q10 in the envelope detector 38 share a same bias voltage V.sub.CM. In this way, transistors Q5-Q6 (driven by |V.sub.in(t)|) and Q7, cause the voltage V.sub.RE on averaging resistor 73 to be equal to the average value of |V.sub.in(t)|. Since V.sub.in(t)=A sin(2πf.sub.ot), voltage on the averaging resistor 73 is V.sub.RE=(4/π)A and the current through it is IR.sub.E=(4/π)A/R.sub.E. MOSFET transistors M1, M2 in the first voltage generating network 75 mirror current I.sub.REF+I.sub.RE into a first output resistor 85 (coupled to the first output 37 of the envelope detector 38) with resistance R1, while MOSFET transistors M3, M4 in the second voltage generating network 81 mirror current I.sub.REF into a second output resistor 86 with resistance R2 (coupled to the second output 50 of the envelope detector 38). Thus:

Vb1=V.sub.CC−(I.sub.REF+IR.sub.E).Math.R1,

Vb2=V.sub.CC−I.sub.REF.Math.R2.

[0063] Assuming R1=R2,

V.sub.os=Vb2−Vb1=R1.Math.I.sub.RE=(4/π)(R1/R.sub.E)A.

[0064] The ratio R1/R.sub.E is designed such that V.sub.os satisfies condition (5), thus allowing to maintain good suppression of the fundamental frequency component independently from the amplitude of the input signal.

[0065] Measurements made by the Applicant confirm that the tripler circuit 20 suppresses almost completely the component at fundamental frequency f.sub.o in the output current I.sub.o. For example, FIG. 8 shows the plot of the output power P.sub.3fo measured at 3f.sub.o when the input power P.sub.in is swept at 12.5 GHz and the plot of the sum P.sub.sum of the output powers P.sub.fo (measured at f.sub.o) and P.sub.5fo (measured at 5f.sub.o) obtained with the frequency tripler 20. As may be seen, in the range −5 dBm to 10 dBm, the output power P.sub.3fo is higher than the sum power P.sub.sum of about 40 dBm in almost the entire input power range and in any case never lower than 36 dBm.

[0066] The improvement of the tripler circuit 20 with respect to a conventional tripler using class-C operating transistors is also visible from FIG. 9, showing the output spectrum obtainable with the present frequency tripler 20 (curve Tr1_3fo), the undesired output spectrum at f.sub.o obtainable with a conventional tripler using class-C operating transistors (curve Tr2_fo) and the undesired output spectrum at f.sub.o obtainable with the present frequency tripler 20 (curve Tr1_fo). As visible, curve Tr1_fo is 20 dB lower than curve Tr2_fo and 40 dB lower than curve Tr1_3fo.

[0067] Advantages of embodiments of the present invention are clear from the above. For example, it is underlined that, in some embodiments, the tripler circuit is advantageously able to suppress undesired fundamental and harmonics in a much better way than with conventional circuits.

[0068] In some embodiments, the tripler circuit advantageously operates at low power compared with conventional designs exploiting class-C transistors and filters.

[0069] Finally, it is clear that numerous variations and modifications may be made to the frequency tripling electronic circuit described and illustrated herein, all falling within the scope of the invention as defined in the attached claims.

[0070] For example, the bipolar transistors Q1-Q10 could be replaced by MOSFET transistors; the transistors may be made in any technology, such as silicon, gallium arsenide (GaAs), indium phosphide (InP), etc.; the structure of the envelope detector may be any other, provided it performs the functionalities depicted above, specifically it gets Vb2−Vb1=Vos satisfying relation (5).