Carrier with Downsized Through-Via

Abstract

In an embodiment a carrier includes a base substrate, at least one insulating layer, at least one inner wiring layer, at least one outer wiring layer and at least one through-via in the insulating layer extending through the insulating layer, wherein the base substrate and the insulating layer are formed from different materials, wherein the base substrate is formed for mechanically stabilizing the carrier and supports the insulating layer, wherein the inner wiring layer is arranged in a vertical direction at least in places between the base substrate and the insulating layer, wherein the outer wiring layer is spatially separated from the inner wiring layer at least in places by the insulating layer, and wherein the through-via electrically conductively connects the inner wiring layer to the outer wiring layer and has a lateral cross-section having a maximum lateral extent of at most 100 μm.

Claims

1.-18. (canceled)

19. A carrier comprising: a base substrate; at least one insulating layer; at least one inner wiring layer; at least one outer wiring layer; and at least one through-via in the insulating layer extending through the insulating layer, wherein the base substrate and the insulating layer are formed from different materials, wherein the base substrate is formed for mechanically stabilizing the carrier and supports the insulating layer, wherein the inner wiring layer is arranged in a vertical direction at least in places between the base substrate and the insulating layer, wherein the outer wiring layer is spatially separated from the inner wiring layer at least in places by the insulating layer, and wherein the through-via electrically conductively connects the inner wiring layer to the outer wiring layer and has a lateral cross-section having a maximum lateral extent of at most 100 μm.

20. The carrier according to claim 19, wherein the inner wiring layer is arranged on the base substrate and is structured in such a way that the insulating layer is directly adjacent to the base substrate in places and directly adjacent to the inner wiring layer in places.

21. The carrier according to claim 19, further comprising a through-via in the base substrate, wherein the through-via extends through the base substrate, is electrically conductive and has a larger lateral cross-section than the through-via in the insulating layer.

22. The carrier according to claim 21, further comprising a further wiring layer, wherein the inner wiring layer and the further wiring layer are arranged on opposite surfaces of the base substrate and are electrically conductively connected to one another via the through-via in the base substrate.

23. The carrier according to claim 22, further comprising a further insulating layer, a further outer wiring layer and a further through-via in the further insulating layer extending through the further insulating layer, wherein the further wiring layer is formed as an inner wiring layer, wherein the base substrate is disposed in the vertical direction between the inner wiring layers as well as between the insulating layers, and wherein the further through-via electrically conductively connects the further inner wiring layer to the further outer wiring layer and has a lateral cross-section with a maximum lateral extent of at most 100 μm.

24. The carrier according to claim 19, wherein the through-via in the insulating layer has a lateral cross-section with a maximum lateral extent of at most 75 μm.

25. The carrier according to claim 19, wherein the through-via in the insulating layer has a lateral cross-section which decreases with increasing vertical distance from the base substrate.

26. The carrier according to claim 19, wherein the inner wiring layer has an inner closure cap adjacent to the through-via in the base substrate and, in top view, completely covering this through-via, wherein the outer wiring layer has an outer closure cap adjoining the through-via in the insulating layer and, in the top view, completely covering this through-via, and wherein a maximum lateral offset between the outer closure cap and the through-via in the insulating layer is smaller than a maximum lateral offset between the inner closure cap and the through-via in the base substrate.

27. The carrier according to claim 19, wherein the outer wiring layer forms a freely accessible mounting surface configured to receive and electrically contact one electrical component or several electrical components.

28. The carrier according to claim 27, wherein the outer wiring layer has a plurality of conductor tracks and connection pads arranged next to one another, and wherein some of the connection pads are externally electrically connectable not via the through-vias in the insulating layer but exclusively via the conductor tracks of the outer wiring layer, and some further of the connection pads are electrically conductively connected to the inner wiring layer by the through-vias in the insulating layer.

29. The carrier according to claim 28, wherein at least some adjacently arranged connection pads are arranged as pairs, wherein, in each case, one connection pad of one pair is externally electrically connectable not via the through-via in the insulating layer but exclusively via at least one conductor track of the outer wiring layer, and wherein the respective other connection pad of the one pair is electrically conductively connected to the inner wiring layer by a through-via in the insulating layer.

30. The carrier according to claim 19, wherein the insulating layer and/or the further insulating layer is a layer of a potting compound, an oxide layer, a nitride layer, a polyimide layer, a solder resist layer or a photoresist layer, and/or wherein the base substrate is a printed circuit board, a metal core board, a plastic body or a ceramic body.

31. The carrier according to claim 19, wherein the outer wiring layer forms a freely accessible mounting surface configured to receive and to make electrical contact with one electrical component or with several electrical components, wherein the outer wiring layer has a plurality of conductor tracks and connection pads arranged next to one another, and wherein some of the connection pads are externally electrically connectable not via the through-vias in the insulating layer but exclusively via the conductor tracks of the outer wiring layer, and some further of the connection pads are electrically conductively connected to the inner wiring layer by the through-vias in the insulating layer.

32. The carrier according to claim 19, wherein the outer wiring layer forms a freely accessible mounting surface configured to receive and to make electrical contact with one electrical component or with several electrical components, wherein the outer wiring layer has a plurality of conductor tracks and connection pads arranged next to one another, wherein some of the connection pads are externally electrically connectable not via the through-vias in the insulating layer but exclusively via the conductor tracks of the outer wiring layer, and some further of the connection pads are electrically conductively connected to the inner wiring layer by the through-vias in the insulating layer, wherein some adjacently arranged connection pads are arranged as pairs, wherein, in each case, one connection pad of one pair is externally electrically connectable not via the through-via in the insulating layer but exclusively via conductor track/s of the outer wiring layer, and the respective other connection pad of the one pair is electrically conductively connected to the inner wiring layer by a through-via in the insulating layer.

33. A method for producing the carrier according to claim 19, wherein a method for forming the base substrate and a method for forming the insulating layer and/or the further insulating layer differ from each other.

34. The method according to claim 33, wherein the carrier comprises the through-via in the base substrate, wherein the through-via extends through the base substrate, is electrically conductive and has a larger lateral cross-section than the through-via in the insulating layer, and wherein a method for forming the through-via in the base substrate and a method for forming the through-via in the insulating layer differ from each other.

35. The method according to claim 33, further comprising: applying an electrically insulating material to the inner wiring layer; forming an opening in the insulating layer to partially expose the inner wiring layer; and filling the opening with an electrically conductive material to form the through-via.

36. The method according to claim 33, further comprising: applying an electrically conductive material onto the inner wiring layer in places for forming the through-via in the insulating layer prior to forming the insulating layer; applying an electrically insulating material onto the inner wiring layer to form the insulating layer so that the insulating layer completely covers the through-via in top view; and partially removing the insulating material of the insulating layer to expose the through-via.

37. A carrier comprising: a base substrate; at least one insulating layer; at least one inner wiring layer; at least one outer wiring layer; and at least one through-via in the insulating layer extending through the insulating layer, wherein the base substrate and the insulating layer are formed from different materials, wherein the base substrate is formed for mechanically stabilizing the carrier and supports the insulating layer, wherein the inner wiring layer is arranged in a vertical direction at least in places between the base substrate and the insulating layer, wherein the outer wiring layer is spatially separated from the inner wiring layer at least in places by the insulating layer, wherein the through-via electrically conductively connects the inner wiring layer to the outer wiring layer, wherein the outer wiring layer forms a freely accessible mounting surface configured to receive and to make electrical contact with one electrical component or with several electrical components, wherein the outer wiring layer has a plurality of conductor tracks and connection pads arranged next to one another, and wherein some of the connection pads are externally electrically connectable not via the through-vias but exclusively via the conductor tracks of the outer wiring layer, and some further of the connection pads are electrically conductively connected to the inner wiring layer by the through-vias in the insulating layer.

38. A carrier comprising: a base substrate; at least one insulating layer; at least one inner wiring layer; at least one outer wiring layer; and at least one through-via in the insulating layer extending through the insulating layer, wherein the base substrate and the insulating layer are formed from different materials, wherein the base substrate is formed for mechanically stabilizing the carrier and supports the insulating layer, wherein the inner wiring layer is arranged in a vertical direction at least in places between the base substrate and the insulating layer, wherein the outer wiring layer is spatially separated from the inner wiring layer at least in places by the insulating layer, wherein the through-via electrically conductively connects the inner wiring layer to the outer wiring layer, wherein the outer wiring layer forms a freely accessible mounting surface configured to receive and to make electrical contact with one electrical component or with several electrical components, wherein the outer wiring layer has a plurality of conductor tracks and connection pads arranged next to one another, wherein some of the connection pads are externally electrically connectable not via the through-vias but exclusively via the conductor tracks of the outer wiring layer, and some further of the connection pads are electrically conductively connected to the inner wiring layer by the through-vias in the insulating layer, wherein some adjacently arranged connection pads are arranged as pairs, and wherein in each case one connection pad of one pair is externally electrically connectable not via the through-via but exclusively via at least one conductor track of the outer wiring layer, and the respective other connection pad of the one pair is electrically conductively connected to the inner wiring layer by the through-via in the insulating layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Further embodiments and further developments of the carrier or of the method for producing the carrier will be apparent from the embodiments explained below in connection with FIGS. 1A to 10D.

[0045] FIGS. 1A, 1B and 1C show schematic representations of various comparative examples of a conventional carrier in vertical sectional view;

[0046] FIGS. 1D and 1E show schematic representations of various comparative examples of a conventional carrier in top view;

[0047] FIGS. 2A, 2B and 2C show schematic representations of a carrier in vertical sectional view;

[0048] FIGS. 3A and 3B show schematic representations of further exemplary embodiments of a carrier in vertical sectional view;

[0049] FIG. 3C shows schematic representation of a section of a carrier in vertical sectional view;

[0050] FIGS. 4A, 4B and 4C show schematic representations of various exemplary embodiments of a four-layer carrier in vertical sectional view;

[0051] FIGS. 4D and 4E show schematic representations of further exemplary embodiments of a multilayer carrier in vertical sectional view;

[0052] FIGS. 5A, 5B and 5C show schematic representations of a carrier, where 5A is a top view of the mounting surface, 5B is a vertical sectional view, 5C is a top view of the inner wiring position;

[0053] FIGS. 6A and 6B show schematic representations of another exemplary embodiment of a carrier, where 6A is a top view of the mounting surface and 6B is a top view of the inner wiring position;

[0054] FIGS. 7A and 7B show schematic representations of a further exemplary embodiment of a carrier, where 7A is a top view of the mounting surface and 7B is a top view of the inner wiring position;

[0055] FIGS. 8A, 8B, 8C, 8D, 8E, 8F and 8G show schematic representations of various method steps of a process for producing a carrier, each in vertical sectional view;

[0056] FIGS. 9A, 9B and 9C show schematic representations of various method steps of a process for producing a carrier according to a further exemplary embodiment, in each case in vertical sectional view; and

[0057] FIGS. 10A, 10B, 10C and 10D show schematic representations of further method steps of a process for producing a carrier, in each case in vertical sectional view.

[0058] Identical, equivalent or equivalently acting elements are indicated with the same reference numerals in the figures. The figures are schematic illustrations and thus not necessarily true to scale. Comparatively small elements and particularly layer thicknesses can rather be illustrated exaggeratedly large for the purpose of better clarification.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0059] FIG. 1A shows a comparative example of a single-layer conventional carrier 10. The carrier 10 has a base substrate 1. A wiring layer 2V is arranged on the base substrate 1. A mounting surface 10M of the carrier 10 is formed by exposed surfaces of the base substrate 1F and by exposed surfaces of the wiring layer 2V. The carrier 10 also has an exposed rear side 10B facing away from the mounting surface 10M, which is formed by a rear-side surface 1B of the base substrate 1.

[0060] In particular, the wiring layer 2V is formed by a structured covering layer 1Z of the base substrate 1. The structured covering layer 1Z may have a plurality of interconnected sub-regions or laterally spaced sub-regions, for example, in the form of conductor tracks 2W or connection pads 2P or other structures on the mounting surface 10M.

[0061] FIG. 1B shows a comparative example of a two-layer conventional carrier 10 which, in comparison with FIG. 1A, additionally has a rear wiring layer 3R on the rear side 1B of the base substrate 1. This wiring layer 3R can, for example, fulfill the function of a rear-side connection, contact or mounting surface. The front side 1F and/or the rear side 1B may be planar.

[0062] The front-side wiring layer 2V can be formed from a structured cover layer 1Z of the base substrate 1, which has a plurality of sub-regions, which are formed, for example, as conductor tracks 2W, connection pads 2P or as closure caps 2C (cf. FIG. 1D). The rear-side wiring layer 3R can be formed analogously to the front-side wiring layer 2V by a structured cover layer 1Z which has a plurality of sub-regions, which are formed, for example, as rear-side connection pads 3P, as rear-side conductor tracks 3W or as rear-side closure caps 3C.

[0063] The front-side wiring layer 2V is electrically conductively connected to the rear-side wiring layer 3R via a through-via 11 or via a plurality of through-vias 11. The closure caps 2C or 3C within the wiring layers 2V or 3R represent the end points of the through-vias 11.

[0064] FIG. 1C shows a comparative example of a four-layer conventional carrier 10, which—compared to FIG. 1B—additionally has two inner wiring layers 1V and 1R. In particular, the front side 1F or the rear side 1B together with the wiring layer 2V or 3R is planar. The inner wiring layers 1V and 1R are embedded in the same material of the base substrate 1.

[0065] Via the through-vias 21 and 31, the outer wiring layers 2V and 3R can be electrically conductively connected to the inner wiring layers 1V and 1R. The two inner wiring layers 1V and 1R may be electrically conductively connected to each other via the through-via/s 11.

[0066] In the carriers 10 shown in FIGS. 1A to 1C, the connection pads 2P are part of the mounting surface 10M for external contacting. They should therefore have a suitable minimum structural width and spacing so that an electrical component can be securely mounted on the mounting surface and electrically contacted. The connection pads 3P (if present) are part of rear side 10B of the carrier for external contacting. Therefore, they should have a suitable minimum structural width and spacing so that the carrier 10 can be securely mounted on and suitably electrically connected to a sub-mount.

[0067] The carriers 10 shown in FIGS. 1A to 1C may each have a base substrate 1 made of an electrically insulating material, wherein the through-vias 11, 21 and/or 31 shown in FIGS. 1B and 1C are in particular embedded in the same material of the base substrate 1 and/or laterally surrounded by the same material of the base substrate 1.

[0068] The through-vias 11, 21 and 23 each have a lateral diameter 11D, 21D and 31D, respectively. In conventional methods using conventional materials of the base substrate, the through-vias 11, 21 and 31 generally have a diameter of at least 125 μm or 150 μm. The closure caps 1C, 2C or 3C should be of such a size that, in top view, they reliably completely cover the respective associated through-vias 11, 21 or 31, even taking into account process-related offset tolerances. The size of the through-vias 11, 21 or 31 thus plays an important role in the design of the carrier 10, in particular of the mounting surface 10M of the carrier 10.

[0069] In FIG. 1D, a section of a mounting surface 10M of a carrier 10 is shown in top view. In particular, the mounting surface 10M is formed from an exposed surface 1F of the base substrate 1 and from an exposed surface of the outer wiring layer 2V. Thus, the mounting surface 10M is electrically conductive in places and electrically insulating in places.

[0070] Referring to FIG. 1D, the mounting surface 10M has at least one connection pad 2P, usually a plurality of conductor tracks 2W, and usually a plurality of closure caps 2C. If a connection pad 2P covers a through-via 11 or 21, it additionally fulfills the function of a closure cap 2C. The closure cap 2C may be integrated, i.e. included or at least partially included, in the connection pad. In top view, the closure caps 2C (and, if applicable, the connection pad 2P) completely cover the respective associated through-via 11 or 21.

[0071] The conductor tracks 2W have a minimum structural width (usually this is the conductor track width), which is given either by the producing process of the wiring layer 2V or by the application, for example, with respect to the required current carrying capacity.

[0072] The closure caps 2C have a minimum structure width (usually this is the cap diameter), which is given by the producing processes of the wiring layer 2V and of the through-vias 11 or 21.

[0073] There is a minimum distance between the connection pads 2P and/or the conductor tracks 2W and/or the closure caps 2C which is given either by the producing process of the wiring layer 2V or by the application, for example, in terms of the required dielectric strength.

[0074] Due to the presence of conductor tracks 2W and/or of closure caps 2C, as well as the minimum structure widths and minimum distances to be maintained, the design freedom of the connection pads 2P within the mounting surface 10M is limited, in particular with respect to their sizes and positions.

[0075] The designs of the wiring layer 2V, illustrated in FIG. 1D, apply analogously also to the outer wiring layer 3R and, excluding the connection pads, also to inner wiring layers.

[0076] If a dense regular arrangement of components on the mounting surface 10M is desired, the mounting surface 10M will usually have a regular arrangement of densely packed connection pads 2P, each having different electrical potentials. This may result in insufficient remaining free space on the mounting surface 10M for the required conductor tracks 2W or for the closure caps 2C to connect or to wire each of the connection pads 2P in an electrically suitable manner.

[0077] FIG. 1E illustrates an example of the problem of an arrangement of 6×3 connection pads 2P which is suitable for mounting 3×3 closely packed small bipolar components P. Due to the small component size, each connection pad 2P is too small to integrate a closure cap 2C therein. Due to the close packing of the components P, the spacing of the connection pads 2P is too small to allow conductor tracks to pass through between them. Consequently, in this example, the internal 4 of the total 18 connection pads cannot be electrically connected, neither by conductor track nor by through-via.

[0078] An arrangement of closely packed small components such as closely packed light emitting diode flip chips on the carrier 10 according to FIG. 1E is thus difficult to realize.

[0079] In the following, various exemplary embodiments of a carrier 10 are illustrated wherein the closure caps 2C can be reduced in size or the number of conductor tracks 2W and/or closure caps 2C on the mounting surface 10M can be reduced.

[0080] The exemplary embodiment for a carrier 10 shown in FIG. 2A is structurally similar to the carrier 10 shown in FIG. 1A. In contrast, the carrier 10 has an inner wiring layer 1V and an outer wiring layer 2V. An insulating layer 2 is arranged in places between the wiring layers 1V and 2V. The carrier 10 has a plurality of through-vias 21 that extend throughout the insulating layer 2 in places and electrically conductively connect the inner wiring layer 1V to the outer wiring layer 2V. In particular, the through-vias 21 each have a cross-section with a maximum lateral extent or with a lateral diameter of at most 100 μm.

[0081] Compared with conventional carriers (see for example FIG. 1A), the closure caps 2C and/or the connection pads 2P on the outer wiring layer 2V can be made correspondingly smaller. Referring to FIG. 2A, the outer wiring layer 2V projects beyond the insulating layer 2 along the vertical direction. The conductor tracks 2W, the closure caps 2C, the connection pads 2P and/or the through-vias 21 of the outer wiring layer 2V may be formed of the same material or of different materials. It is conceivable that the through-vias 21 and the associated closure cap 2C are formed of the same material and in one piece. Deviating from this, it is possible that the through-via 21 and the associated closure cap 2C are two different layers, which in particular are directly adjacent to one another and are produced in different method steps.

[0082] The mounting surface 10M is in particular planar and has a roughness of at most 50 μm, 40 μm, 30 μm, 20 μm or of at most 10 μm. In particular, the roughness of the mounting surface 10M is given by local depressions or local elevations, which are caused, for example, by the layer thickness of the conductor tracks 2W, the connection pads 2P and/or of the closure cap 2C. The conductor tracks 2W, the closure caps 2C and/or the connection pads 2P can have a vertical layer thickness of at most 50 μm, 40 μm, 30 μm, 20 μm or at most 10 μm.

[0083] The exemplary embodiment shown in FIG. 2B is essentially the same as the exemplary embodiment shown in FIG. 2A. In contrast, the insulating layer 2 extends beyond the outer wiring layer 2V in places. In this case, the insulating layer 2 may cover the closure caps 2C, the connection pads 2P in places, and the conductor tracks 2W completely. At positions of the connection pads 2P, the insulating layer 2 may have openings 20, so that the connection pads 2P are accessible in the openings 20 of the insulating layer 2. The connection pads 2P are configured to receive one or more components. The openings 20 may serve as a collecting basin for excess bonding material.

[0084] The exemplary embodiment shown in FIG. 2C essentially corresponds to the exemplary embodiment shown in FIG. 2A. The difference is that the cross-sections of the through-vias 21, in each case, decrease with increasing distance from the base substrate 1. Thus, the through-vias 21 have a smaller cross-section at the outer wiring layer 2V than at the inner wiring layer 1V.

[0085] According to the carriers 10 shown in FIGS. 2A to 2C, a rear side 10B is formed by a surface, in particular by a rear side 1B, of the base substrate 1.

[0086] The exemplary embodiment shown in FIG. 3A is substantially the same as the exemplary embodiment shown in FIG. 2A. In contrast, the carrier 10 includes a plurality of base through-vias 11, wherein the through-vias 11 extend throughout the base substrate 1 along the vertical direction. The carrier 10 further comprises a rear-side wiring layer 1R having closure caps 1C on the rear side 1B of the base substrate 1. The base through-vias 11 thus extend from the rear-side wiring layer 1R throughout the base substrate 1 to the inner wiring layer 1V. The rear side 1B of the carrier 10 is formed in places by surfaces of the rear-side wiring layer 1R and in places by surfaces of a further insulating layer 3, wherein the insulating layer 3 is disposed on the rear side 1B of the base substrate 1. This insulating layer 3 may fill up regions between the closure caps 1C, so that as a whole, the rear side 1B is planar.

[0087] The base through-via 11 has a lateral diameter 11D. In case of doubt, the diameter 11D is a maximum lateral extent of the cross-section of the base through-via 11. In particular, the diameter 11D is greater than 100 μm, particularly greater than 150 μm. It is possible that the diameter 11D of the base through-via 11 is at least 50%, 75%, 100% or 200% larger than the diameter 21D of the through-via 21. In top view, the base through-via 11 and the through-via 21 may overlap, partially overlap, or be arranged side by side.

[0088] The exemplary embodiment shown in FIG. 3B is substantially the same as the exemplary embodiment shown in FIG. 3A. In contrast, the base through-vias 11 do not extend from the rear-side wiring layer 1R to the inner wiring layer 1V but throughout the rear-side wiring layer 1R and throughout the inner wiring layer 1V. While the through-via 21 in FIG. 3A is arranged on the inner wiring layer 1V, according to FIG. 3B, at least one of the through-vias 21 may be arranged directly on the base through-via 11 in top view. In top view, the through-via 21 is completely covered by a closure cap 2C whose diameter 2CD is larger than a diameter 21D of the through-via 21.

[0089] In FIG. 3C, a base through-via 11 in the base substrate 1 and an associated closure cap 1C on the base substrate 1 are schematically shown as an example. The base through-via 11 has a lateral diameter 11D. The closure cap 1C has a lateral diameter 1CD.

[0090] In top view, the closure cap 1C completely covers the associated base through-via 11. In ideal coverage, the closure cap 1C and the associated base through-via 11 may have the same cross-section or diameter. In practice, however, the diameter 1CD of the closure cap 1C is chosen to be the sum of the diameter 11D of the base through-via 11 and the producing tolerances. In general, the required diameter of the closure cap is preferably at least as large as the sum of the diameter of the through-via and twice the producing tolerances. For example, the diameter 1CD is at least 110 μm, 130 μm, 160 μm, 210 μm or 250 μm.

[0091] In FIG. 3C, the optimal positioning of the closure cap 1C on the base through-via 11 is schematically shown on the left side, i.e. with an offset V of zero. A possible maximum offset between the base through-via 11 and the associated closure cap 1C is schematically shown in the center and on the right side in FIG. 3C. The edge of the closure cap 1C coincides with the edge of the through-via 11, so that the closure cap 1C just completely covers the base through-via 11.

[0092] The example illustrated in FIG. 3C can be applied to all corresponding pairs of matched through-vias and closures, for example, vias 21 having a lateral diameter 21D and closures 2C having a lateral diameter 2CD.

[0093] Because the through-vias 21 in the insulating layer 2 can have a smaller cross-section compared to the base through-vias 11 in the base substrate 1, it is possible that the minimum required diameter 2CD of the closure cap 2C is correspondingly smaller than the diameter 1CD of the closure cap 1C for the same maximum offset, and that the required area of the closure cap 2C is correspondingly smaller in square than the area of the closure cap 1C.

[0094] For some producing processes, the maximum occurring offset correlates with the size of the through-via and/or of the closure cap, so that a smaller closure cap 2C can be placed on a through-via 21 with a smaller offset V. This in turn further reduces the minimum required diameter 2CD of the closure cap 2C.

[0095] For example, for a base through-via 11 having a diameter 11D of 125 μm and extending throughout the base substrate 1, the offset V may be 50 μm, so that the minimum required diameter 1CD of the closure cap 1C is 225 μm, while for a through-via 21 having a diameter 21D of 30 μm and extending throughout an insulating layer 2, the offset V may be 25 μm, so that the minimum required diameter 2CD of the closure cap 2C is only 80 μm. The minimum required area of the closure cap 2C would be 5027 μm.sup.2, compared to 39761 μm.sup.2 for the closure cap 1C.

[0096] The exemplary embodiment shown in FIG. 4A is essentially the same as the exemplary embodiment shown in FIG. 3A. In contrast, the carrier 10 is four-layered. In addition to the inner wiring layer 1V and the outer wiring layer 2V, the carrier 10 has a further inner wiring layer 1R and a further outer wiring layer 3R. In addition, the inner wiring layers 1V and 1R each have a cover layer 1Z of the base substrate 1. The respective cover layers 1Z are arranged in particular on the base substrate 1, in particular directly on the base substrate 1. The base through-vias 11 extend in particular partially throughout the respective cover layers 1Z. The closure caps 1C are each arranged on the cover layer 1Z, in particular directly on the cover layer 1Z. The cover layers 1Z and the closure caps 1C can be congruent when viewed from above.

[0097] According to FIG. 4A, the carrier 10 has a further insulating layer 3. The insulating layer 3 may be formed analogously to the insulating layer 2. The carrier 10 has a plurality of further through-vias 31 which electrically conductively connect the further inner wiring layer 1R to the further outer wiring layer 3R. The outer wiring layer 3R is located on the rear side 10B of the carrier 10. The outer wiring layer 3R is thus accessible from the outside. Analogous to the front-side outer wiring layer 2V, the rear-side wiring layer 3R may have a plurality of conductor tracks 3W, closure caps 3C and/or connection pads 3P. In terms of material composition as well as of layer thickness, the outer wiring layer 3R may be formed analogously to the outer wiring layer 2V.

[0098] The exemplary embodiment shown in FIG. 4B essentially corresponds to the exemplary embodiment shown in FIG. 4A. In contrast, the insulating layers 2 and 3 in FIG. 4B are formed analogously to the insulating layer 2 in FIG. 2B. In other words, the insulating layers 2 and 3 may each have a plurality of openings 20 or 30, wherein the connection pads 2P or 3P are exposed. The conductor tracks 2W and/or 3W and the closure caps 2C and/or 3C may be partially or completely covered by the respective insulating layers 2 or 3. The connection pads 2P and/or 3P may be partially covered by the respective insulating layers 2 or 3.

[0099] The exemplary embodiment shown in FIG. 4C is substantially the same as the exemplary embodiment shown in FIG. 4A. In contrast, the through-vias 21 or 31 are formed such that their cross-section or diameter 21D or 31D decreases with increasing distance from the base substrate 1. The design of the through-vias 21 and 31 illustrated in FIG. 4C is analogous to the design of the through-vias 21 illustrated in FIG. 2C.

[0100] FIGS. 4D and 4E illustrate that further insulating layer layers and further wiring layers can be added on the mounting side and/or on the rear side.

[0101] Starting from a carrier shown in FIG. 1B without insulating layer and associated wiring layer, FIG. 4A shows on each side of the carrier an insulating layer 2 or 3 with associated wiring layer 2V or 3R. FIG. 4D shows two insulating layers 2 or 3 on each side with associated wiring layers. FIG. 4E shows three insulating layers 2 or 3 with associated wiring layers on each side. If further internal wiring layers are required, these can be arranged in the base substrate 1 and/or in the insulating layers 2 or 2, for example, as shown in FIG. 1C. The through-vias 21 and 31 between the wiring layers within the insulating layers 2 and 3 can be smaller than the base through-vias 11 in the base substrate 1.

[0102] FIGS. 5A, 5B and 5C show examples of how the problem illustrated in FIG. 1E can be solved, in particular by using insulating layers 2 and 3 and associated through-vias 21 and 31. FIG. 5A shows a top view of a part of the mounting surface 10M and the wiring layer 2V of a carrier 10. FIG. 5B shows a vertical sectional view through a portion AB of the carrier 10. FIG. 5C shows a top view of the wiring layer 1V within the carrier 10, which corresponds to a lateral sectional view.

[0103] The mounting surface 10M has an arrangement of 8×4 connection pads 2P suitable for mounting 4×4 closely packed small bipolar components P. These may be, for example, light emitting diode flip chips.

[0104] Since the through-vias 21 within the insulating layer 2 have a smaller diameter 21D than the base through-vias 11 having diameter 11D, the smallest possible diameters of the closure caps 2C can be significantly smaller than the smallest possible diameters of the closure caps 1C.

[0105] Analogous to the explanation of FIG. 3C, a closure cap 2C could have a diameter 2CD of 80 μm, compared to a closure cap 1C with a diameter 1CD of 225 μm. For example, if a connection pad has a width of 80 μm, 100 μm, 150 μm or 200 μm as specified by component P, this allows integration of a closure cap 2C into a connection pad 2P, i.e. positioning of a connection pad 2P over a through-via 21, whereas this would not be possible in the example without an insulating layer in FIG. 1E.

[0106] Thus, all 8×4 connection pads 2P can be electrically wired inside the carrier 10. For example, the external 20 connection pads can be electrically wired per conductor tracks 2W in the wiring layer 2V as illustrated. The inner 12 connection pads 2P can, for example, as illustrated, first be electrically wired via the through-vias 21 to the wiring layer 1V and then from there with conductor tracks 1W (see FIG. 5C). The through-vias 11 and 31 as well as the wiring within the wiring layers 1R and 3R as shown in FIG. 5B may be present or optional.

[0107] In this way, the example illustrated in FIGS. 5A to 5C can be easily extended to a larger number of components P and connection pads 2P, respectively.

[0108] Starting from the outer upper wiring layer 2V, all possible connection pads 2P are wired in each case per conductor tracks 2W within this wiring layer. These are usually the connection pads on the outside in the field. The potentials of the other, in particular of all other connection pads are routed to the next lower wiring layer via the through-vias 21. These are usually the inner connection pads.

[0109] There, the process is then successive in each case. This means that the potentials, usually the external potentials, are wired by conductor tracks in this wiring layer. The wiring of all other potentials, usually the inner potentials, is realized by through-vias in a lower wiring layer. This is realized by a sufficient number of wiring layers until sufficiently few potentials remain in wiring layer 1V to be wired there by conductor tracks 1W or by the through-vias 11 in base substrate 1.

[0110] FIGS. 6A and 6B show, as an example of application, a closely packed arrangement of 16×9 connection pads 2P suitable for, for example, 8×9 closely packed bipolar small components P such as light emitting diode flip chips. The components are partially wired via a common electrode 4, which may be a common anode or common cathode of the carrier 10. The respective components P each have a connection pad which can be assigned to an individual potential and can be electrically wired separately, while the other connection pads of the components have a common potential and can all be electrically connected to each other.

[0111] FIG. 6A shows, analogously to FIG. 5A, a top view of a part of the mounting surface 10M and the wiring layer 2V of a carrier 10. FIG. 6B shows, analogously to FIG. 5C, a top view of the wiring layer 1V within the carrier 10 and thus a lateral sectional view of the carrier 10 at the vertical level of the wiring layer 1V. The vertical structure of the carrier 10 is the same as that of the carrier 10 shown in FIG. 5B.

[0112] Analogous to the explanation of FIG. 3C, a closure cap 2C could have a diameter 2CD of 80 μm, compared to a closure cap 1C having a diameter 1CD of 225 μm. For example, if a connection pad 2P has a width of 80 μm, 100 μm, 150 μm or 200 μm as specified by the component P, this allows integration of a closure cap 2C into a connection pad 2P, i.e. positioning of a connection pad 2P over a through-via 21, wherein this would not be possible in the example without an insulating layer in FIG. 1E.

[0113] Thus, all 16×9 connection pads 2P can be electrically wired within the carrier 10. The 72 connection pads with the same potential and 18 connection pads with individual potential are wired by conductor tracks 2W in the wiring layer 2V, as illustrated in FIG. 6A. The remaining 54 connection pads with individual potential cannot be wired within the wiring layer 2V due to space restrictions and are first connected to the wiring layer 1V via the through-vias 21. Here, 50 of these 54 connection pads are wired by conductor tracks 1W in wiring layer 1V, as illustrated in FIG. 6B. The remaining 4 connection pads cannot be wired within the wiring layer 1V due to limitations of space, and are first placed on the wiring layer 1R by the through-vias 11 to be wired there.

[0114] The application illustrated in FIGS. 6A to 6B can be extended to a larger number of components P and connection pads 2P, respectively, analogously to the exemplary embodiments of FIGS. 4D and 4E.

[0115] FIGS. 7A and 7B illustrate, as an example of application, a close-packed arrangement of 16×9 connection pads 2P suitable for, for example, 8×9 close-packed bipolar small components P such as light emitting diode flip chips. The mounting surface 10M or outer wiring layer 2V thus has a plurality of connection pads 2P arranged, in particular, in a matrix form with a plurality of rows and columns.

[0116] Referring to FIG. 7A, the connection pads 2P of each second column of the matrix arrangement are electrically connected to each other via a common conductive track 2W. In particular, the common conductor track 2W is in line with the corresponding connection pads 2P of the same column. In other words, the common conductor track 2W in particular does not project laterally beyond the associated connection pads 2P to the connection pads 2P of the adjacent column. In particular, exactly half of the connection pads 2P are wired over the conductor tracks 2W on the wiring layer 2V.

[0117] Those connection pads 2P which are not electrically connected or electrically wired via the conductor tracks 2W on the wiring layer 2V or on the mounting surface 10M, respectively, can be electrically wired via the through-vias 21 to the conductor tracks in a lower-lying wiring layer, in particular in the inner wiring layer 1V.

[0118] Analogously to the outer wiring layer 2V, the connection pads 2P of the same row, which are not already electrically wired via the conductor tracks 2W on the mounting surface 10M, are electrically conductively connected to each other via the conductor tracks 1W in the inner wiring layer 1V according to FIG. 7B. Thus, FIGS. 7A and 7B show a cross-matrix circuit on two different wiring layers. Each component P arranged on a pair of two connection pads 2P of different polarities can be individually activated via the conductor tracks 1W and 2W arranged on different wiring layers.

[0119] In all of the exemplary embodiments for a carrier 10 described so far, the conductor tracks 1W, 2W, 3W, the closure caps 1C, 2C, 3C, the connection pads 2P and/or 3P may be formed of a metal such as copper, nickel or aluminum. The cover layer 1Z of the base substrate 1 may also be formed of such a material. The insulating layers 2 and 3 may each be formed from a solder resist, a photoresist, a potting compound, silicon oxide or from silicon nitride. The maximum possible offset between the through-via 21 or 31 and the associated closure cap 2C or 3C is preferably less than 100 μm, 50 μm, for instance less than 30 μm, in particular less than 25 μm or less than 20 μm.

[0120] It is possible that further layers are used at the joining locations between two electrically conductive layers to improve electrical contact, to improve thermal contact, to improve mechanical strength or to suppress diffusion. Such further layers may be formed of titanium, platinum, palladium, tungsten nitride or alloys of these layers.

[0121] The connection pads 2P or 3P, which are configured for electrical contacting the component, and/or the contact points of the component can be formed from titanium, platinum, palladium, tungsten nitride, gold, tin, silver, copper or from aluminum or alloys thereof. If the insulating layer 2 or 3 has openings 20 or 30, wherein the contact connection pads 2P or 3P are accessible at least in places, the insulating layer 2 or 3 can project beyond the contact connection pad 2P or 3P along the vertical direction. The opening 20 or 30 may serve as a collecting basin for excess solder material.

[0122] FIGS. 8A to 8G schematically illustrate various method steps of a method for producing a carrier 10.

[0123] According to FIG. 8A, a base substrate 1 is provided which has metallic coatings, in particular of copper, on both sides. The base substrate 1 may be formed from dielectric material of a printed circuit board. The base substrate has a front side 1F and a rear side 1B. A cover layer 1Z of the base substrate 1 is formed on the front side 1F and on the rear side 1B, respectively, by the metallic coating. In particular, the covering layer 1Z is partially provided to form a wiring layer 1V or 1R.

[0124] Referring to FIG. 8B, a plurality of openings for forming the through-vias 11 are formed which extend throughout the cover layer 1Z and the base substrate 1. The cross-section of the opening determines the cross-section 11D of the through-via 11.

[0125] Referring to FIG. 8C, the through-vias 11 are formed by filling the previously created openings. A closure layer 1C is also formed on the cover layer 1Z in each case. The closure layer 1C may be formed of copper. The closure layer 1C and the through-vias 11 may be formed of the same material or of different materials.

[0126] According to FIG. 8D, the cover layer 1Z and the closure layer 1C are structured on both sides of the base substrate 1. The closure layer 1C may be structured into a plurality of closure caps 1C, each of which completely covers at least one of the through-vias 11 in top view. The closure cap 1C has a diameter 1CD. By patterning the cover layer 1Z and the closure layer 1C, the base substrate 1 can be exposed in places.

[0127] According to FIG. 8E, an insulating layer 2 is applied to the front side 1F of the base substrate 1 and to the front-side closure caps 1C. The insulating layer 2 can completely cover the closure caps 1C and/or the base substrate 1 in top view. Analogous to the insulating layer 2, a further insulating layer 3 may be applied to the rear side 1B of the base substrate 1 and to the rear-side closure caps 1C. The insulating layers 2 and 3 can be produced in the same method step or in different method steps. The insulating layers 2 and 3 may be formed of the same material or of different materials.

[0128] According to FIG. 8F, openings are formed in the insulating layers 2 and 3 to form the through-vias 21 and 31. An outer wiring layer 2V with possible connection pads 2P, closure caps 2C and possible conductor tracks 2W is formed on the insulating layer 2. In particular, the inner closure caps 1C form an inner wiring layer 1V. Via the through-vias 21, the inner wiring layer 1V is electrically conductively connected to the outer wiring layer 2V.

[0129] Analogously to the through-vias 21 and to the outer wiring layer 2V on the front side 1F of the base substrate 1, a plurality of further through-vias 31 and an outer wiring layer 3R comprising a plurality of possible connection pads 3P, conductor tracks 3W and a plurality of possible closure caps 3C are formed on the rear side 1B of the base substrate 1. The exemplary embodiment shown in FIG. 8F corresponds to the exemplary embodiment of a carrier 10 shown in FIG. 4A.

[0130] According to FIG. 8G, a sub-layer of the insulating layer 2 or 3 is applied to the outer wiring layer 2V or 3R in such a way that the sub-layer partially covers the connection pads 2P or 3P and partially or, in particular, completely covers the conductor tracks 2W or 3W. The partial layer of the insulating layer 2 or 3 and the remaining part of the insulating layer 2 or 3 may be formed from the same material or from different materials. The partial layers can each have openings 20 or 30, wherein the connection pads 2P or 3P are at least partially accessible. The exemplary embodiment shown in FIG. 8G corresponds to the exemplary embodiment of a carrier 10 shown in FIG. 4B.

[0131] The exemplary embodiment illustrated in FIG. 9A essentially corresponds to the exemplary embodiment of a method step illustrated in FIG. 8D. In contrast, a plurality of electrically conductive interconnection structures, which are provided to form the through-vias 21 or 31, are applied onto the wiring layer 1V or onto the wiring layer 1R. The interconnection structures may be bond wires or are in the form of hemispheres. According to FIG. 9B, the insulating layer 2 and/or the insulating layer 3 is formed in such a way that it completely covers the through-vias 21 or 31.

[0132] According to FIG. 9C, the material of the insulating layer 2 and/or 3 is partially removed so that the through-vias 21 or 31 are exposed. In subsequent method steps, the outer wiring layer 2V or 3R can be formed on the insulating layer 2 or 3. This method is particularly suitable for the production of a carrier 10 shown, for example, in FIG. 2C or in FIG. 4C.

[0133] The exemplary embodiment shown in FIG. 10A is substantially the same as the exemplary embodiment for a method step shown in FIG. 8E. In contrast, the insulating layer 2 or 3 has a plurality of openings for forming the through-vias 21 or 31. The insulating layer 2 or 3 can be applied to the base substrate 1 in a structured manner. Alternatively, it is possible that the insulating layer 2 or 3 is first formed in a planar manner on the base substrate 1 and subsequently structured.

[0134] According to FIG. 10B, a sacrificial layer 5 is formed on the insulating layer 2 and/or 3, wherein in the regions of the openings of the insulating layer 2 or 3, the sacrificial layer 5 itself has openings. The openings of the sacrificial layer 5 have a larger cross-section than the openings of the insulating layer 2 and/or 3.

[0135] According to FIG. 10C, the openings of the insulating layer 2 or 3 and the openings of the sacrificial layer 5 are filled with an electrically conductive material. Through-vias 21 or 31 are formed inside the openings of the insulating layer 2 or 3. Outside the openings of the insulating layer 2 or 3 and inside the openings of the sacrificial layer 5, the front-side outer wiring layer 2V or the rear-side outer wiring layer 3R may be formed. The through-vias 21 and the connection pads 2P or the closure caps 2C of the front-side wiring layer 2V may be formed from the same material or from different materials. Similarly, the through-vias 31 and the connection pads 3P or the closure caps 3C of the outer wiring layer 3R may be formed from the same material or from different materials.

[0136] According to FIG. 10D, the sacrificial layer 5 is removed. The wiring layer 2V or 3R may be thinned, grinded or planarized. In particular, the sacrificial layer 5 is removed only after the corresponding wiring layer 2V or 3R has been thinned, grinded or planarized.

[0137] Using the method illustrated in FIGS. 10A to 10D, the shape, the layer thickness and/or the flanks of the through-vias 21 or 31 and the wiring layer 2V or 3R can be better controlled, for example, in comparison with an etching process, since the producing tolerances for patterning the sacrificial layer 5 are generally better than the producing tolerances, for example, for patterning an etching mask. Furthermore, an even more precise control can be achieved if the sacrificial layer 5 is formed to be transmissive to radiation, for instance transparent, or if an LDI process (laser direct imaging) and/or a so-called partitioning process is applied.

[0138] The invention is not restricted to the exemplary embodiments by the description of the invention made with reference to the exemplary embodiments. The invention rather comprises any novel feature and any combination of features, including in particular any combination of features in the claims, even if this feature or this combination is not itself explicitly indicated in the patent claims or exemplary embodiments.