Average power tracking power management integrated circuit

Abstract

An average power tracking (APT) power management integrated circuit (PMIC) is provided. The APT PMIC is configured to generate an APT voltage to a power amplifier for amplifying a high modulation bandwidth (e.g., ≥200 MHz) radio frequency (RF) signal. The APT PMIC includes a voltage amplifier configured to generate an initial APT voltage and an offset capacitor configured to raise the initial APT voltage by a modulated offset voltage. The APT PMIC can be configured to modulate the initial APT voltage and the modulated offset voltage concurrently based on a time-variant APT target voltage. As a result, the APT PMIC can adapt the APT voltage very quickly between different voltage levels, thus making it possible to amplify a high modulation bandwidth radio frequency (RF) signal for transmission in a fifth-generation (5G) communication system.

Claims

1. An average power tracking (APT) power management integrated circuit (PMIC) comprising: a voltage amplifier configured to generate an initial APT voltage at a voltage output based on a time-variant APT target voltage and a supply voltage; an offset capacitor coupled between an output of the voltage amplifier and the voltage output and configured to raise the initial APT voltage by a modulated offset voltage to generate an APT voltage at the voltage output; and a control circuit configured to: cause the modulated offset voltage to be generated across the offset capacitor based on a time-variant offset target voltage derived from the time-variant APT target voltage; and cause the initial APT voltage and the modulated offset voltage to change concurrently at a start of a predefined transition window to thereby change the APT voltage to a voltage level indicated by the time-variant APT target voltage within the predefined transition window.

2. The APT PMIC of claim 1 wherein the predefined transition window corresponds to a cyclic prefix (CP) between two consecutive orthogonal frequency division multiplexing (OFDM) symbols.

3. The APT PMIC of claim 1 further comprising: a multi-level charge pump (MCP) configured to generate a low-frequency voltage at a plurality of voltage levels; and a power inductor coupled between the MCP and the voltage output and configured to induce a low-frequency current based on the low-frequency voltage to thereby charge the offset capacitor to the modulated offset voltage.

4. The APT PMIC of claim 3 wherein the offset capacitor has a capacitance determined to cause the offset capacitor to be charged to the modulated offset voltage by the low-frequency current within the predefined transition window.

5. The APT PMIC of claim 3 wherein the control circuit is further configured to control the MCP to adjust the low-frequency voltage to thereby adjust the low-frequency current for charging the offset capacitor.

6. The APT PMIC of claim 1 further comprising a target voltage circuit configured to: receive a plurality of coded voltage words each defining a respective level of the time-variant APT target voltage; and generate the time-variant APT target voltage based on the plurality of coded voltage words.

7. The APT PMIC of claim 6 wherein the control circuit is further configured to: determine the time-variant offset target voltage based on the time-variant APT target voltage; and cause the modulated offset voltage to be generated based on the time-variant offset target voltage within the predefined transition window.

8. The APT PMIC of claim 7 wherein the control circuit is further configured to scale the time-variant APT target voltage based on a programmable gain coefficient to generate the time-variant offset target voltage.

9. The APT PMIC of claim 1 further comprising a supply voltage circuit configured to generate a plurality of supply voltages, wherein the control circuit is further configured to control the supply voltage circuit to provide one of the plurality of supply voltages to the voltage amplifier as the supply voltage.

10. The APT PMIC of claim 1, wherein the control circuit is further configured to: determine that the time-variant APT target voltage indicates an increase of the APT voltage; cause the initial APT voltage and the modulated offset voltage to increase concurrently at the start of the predefined transition window; and cause the initial APT voltage to start decreasing prior to an end of the predefined transition window.

11. An average power tracking (APT) power management apparatus comprising an APT power management integrated circuit (PMIC), the APT PMIC comprising: a voltage amplifier configured to generate an initial APT voltage at a voltage output based on a time-variant APT target voltage and a supply voltage; an offset capacitor coupled between an output of the voltage amplifier and the voltage output and configured to raise the initial APT voltage by a modulated offset voltage to generate an APT voltage at the voltage output; and a control circuit configured to: cause the modulated offset voltage to be generated across the offset capacitor based on a time-variant offset target voltage derived from the time-variant APT target voltage; and cause the initial APT voltage and the modulated offset voltage to change concurrently at a start of a predefined transition window to thereby change the APT voltage to a voltage level indicated by the time-variant APT target voltage within the predefined transition window.

12. The APT power management apparatus of claim 11 further comprising a power amplifier configured to amplify a high modulation bandwidth radio frequency (RF) signal based on the APT voltage.

13. The APT power management apparatus of claim 12 wherein: the high modulation bandwidth RF signal is modulated across a plurality of orthogonal frequency division multiplexing (OFDM) symbols; and the predefined transition window corresponds to a cyclic prefix (CP) between any two consecutive OFDM symbols among the plurality of OFDM symbols.

14. The APT power management apparatus of claim 11 wherein the APT PMIC further comprises: a multi-level charge pump (MCP) configured to generate a low-frequency voltage at a plurality of voltage levels; and a power inductor coupled between the MCP and the voltage output and configured to induce a low-frequency current based on the low-frequency voltage to thereby charge the offset capacitor to the modulated offset voltage.

15. The APT power management apparatus of claim 14 wherein the offset capacitor has a capacitance determined to cause the offset capacitor to be charged to the modulated offset voltage by the low-frequency current within the predefined transition window.

16. The APT power management apparatus of claim 14 wherein the control circuit is further configured to control the MCP to adjust the low-frequency voltage to thereby adjust the low-frequency current for charging the offset capacitor.

17. The APT power management apparatus of claim 11 wherein the APT PMIC further comprises a target voltage circuit configured to: receive a plurality of coded voltage words each defining a respective level of the time-variant APT target voltage; and generate the time-variant APT target voltage based on the plurality of coded voltage words.

18. The APT power management apparatus of claim 17 wherein the control circuit is further configured to: determine the time-variant offset target voltage based on the time-variant APT target voltage; and cause the modulated offset voltage to be generated based on the time-variant offset target voltage within the predefined transition window.

19. The APT power management apparatus of claim 18 wherein the control circuit is further configured to scale the time-variant APT target voltage based on a programmable gain coefficient to generate the time-variant offset target voltage.

20. The APT power management apparatus of claim 11 wherein the APT PMIC further comprises a supply voltage circuit configured to generate a plurality of supply voltages, wherein the control circuit is further configured to control the supply voltage circuit to provide one of the plurality of supply voltages to the voltage amplifier as the supply voltage.

Description

BRIEF DESCRIPTION OF THE DRAWING FIGURES

(1) The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

(2) FIG. 1 is a schematic diagram of an exemplary orthogonal frequency division multiplexing (OFDM) time-frequency grid illustrating at least one resource block (RB);

(3) FIG. 2 is a schematic diagram of an exemplary average power tracking (APT) power management apparatus wherein an APT power management integrated circuit (PMIC) is configured according to an embodiment of the present disclosure to support quick APT voltage adaptation for amplifying a high modulation bandwidth radio frequency (RF) signal; and

(4) FIG. 3 is a graphic diagram providing an exemplary illustration as to how the APT PMIC in FIG. 2 can be configured to quickly adapt the APT voltage between two consecutive OFDM symbols.

DETAILED DESCRIPTION

(5) The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

(6) It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

(7) It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

(8) Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

(9) The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

(10) Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

(11) Embodiments of the disclosure relate to an average power tracking (APT) power management integrated circuit (PMIC). The APT PMIC is configured to generate an APT voltage to a power amplifier for amplifying a high modulation bandwidth (e.g., 200 MHz) radio frequency (RF) signal. The APT PMIC includes a voltage amplifier configured to generate an initial APT voltage and an offset capacitor configured to raise the initial APT voltage by a modulated offset voltage. The APT PMIC can be configured to modulate the initial APT voltage and the modulated offset voltage concurrently based on a time-variant APT target voltage. As a result, the APT PMIC can adapt the APT voltage very quickly between different voltage levels, thus making it possible to amplify a high modulation bandwidth radio frequency (RF) signal for transmission in a fifth-generation (5G) communication system.

(12) In this regard, FIG. 2 is a schematic diagram of an exemplary APT power management apparatus 26 wherein an APT PMIC 28 is configured according to an embodiment of the present disclosure to support quick APT voltage adaptation for amplifying a high modulation bandwidth RF signal 30. The APT PMIC 28 includes a voltage amplifier 32 having an output 33 coupled to a voltage output 34 via an offset capacitor 36. The voltage amplifier 32 and the offset capacitor 36 are configured to collectively generate an APT voltage V.sub.CC at the voltage output 34 based on a time-variant APT target voltage V.sub.CC-TGT that defines a time-variant voltage target 38. Specifically, the voltage amplifier 32 generates an initial APT voltage V′.sub.CC at the output 33 and the offset capacitor 36 is configured to raise the initial APT voltage V′.sub.CC generated by the voltage amplifier 32 by a modulated offset voltage V.sub.OFF. As a result, the APT PMIC 28 will output the APT voltage V.sub.CC that equals a sum of the initial APT voltage V′.sub.CC and the modulated voltage V.sub.OFF (V.sub.CC=V′.sub.CC+V.sub.OFF) for amplifying the high modulation bandwidth RF signal 30.

(13) The APT power management apparatus 26 includes a power amplifier 40 coupled to the voltage output 34. The power amplifier 40 is configured to amplify the high modulation bandwidth RF signal 30 based on the APT voltage V.sub.CC. In a non-limiting example, the high modulation bandwidth RF signal 30 is modulated with at least 200 MHz modulation bandwidth for transmission in a 5G communications system. In this regard, the high modulation bandwidth RF signal 30 can be modulated across the orthogonal frequency division multiplexing (OFDM) symbols 20(1)-20(N) in FIG. 1. Thus, according to Table 1, the high modulation bandwidth RF signal 30 will be modulated based on 60 KHz subcarrier spacing (SCS). Accordingly, the transition settling time between any two consecutive OFDM symbols of the high modulation bandwidth RF signal 30 needs to be less than or equal to the cyclic prefix (CP) duration of 1.17 ρs (referred to as “a predefined transition window” hereinafter).

(14) As discussed in detail below, the APT PMIC 28 can be configured to modulate the initial APT voltage V′.sub.CC and the modulated offset voltage V.sub.OFF concurrently based on the time-variant APT target voltage V.sub.CC-TGT. As further illustrated later in FIG. 3, the APT PMIC 28 can adapt the APT voltage V.sub.CC from one level to another in accordance with the time-variant voltage target 38. More importantly, the APT PMIC 28 can adapt the APT voltage V.sub.CC from one level to another within the predefined transition window. As a result, the APT PMIC 28 can operate with the power amplifier 40 to amplify the high modulation bandwidth RF signal 30 for transmission in a 5G communication system.

(15) The APT PMIC 28 can include a tracker circuit 42, which includes a multi-level charge pump (MCP) 44 and a power inductor 46. The MCP 44 is configured to generate a low-frequency voltage V.sub.DC (e.g., a constant voltage) at a number of voltage levels. The power inductor 46 is coupled between the MCP 44 and the voltage output 34. The power inductor 46 is configured to induce a low-frequency current I.sub.DC (e.g., a constant current) based on the low-frequency voltage V.sub.DC to thereby charge the offset capacitor 36 to the modulated offset voltage V.sub.OFF during the predefined transition window. Notably, the modulated offset voltage V.sub.OFF can be expressed as in an equation (Eq. 1) below.
ΔV.sub.OFF=I.sub.DC/C  (Eq. 1)

(16) In the equation (Eq. 1) above, C represents a capacitance of the offset capacitor 36. It can be seen from Eq. 1 that, when the low-frequency current I.sub.DC is held constant, the smaller the capacitance C, the faster the offset capacitor 36 can be charged to a specific level of the modulated offset voltage V.sub.OFF. As such, the capacitance C of the offset capacitor 36 is so determined to ensure that the offset capacitor 36 can be charged to the modulated offset voltage V.sub.OFF by the low-frequency current I.sub.DC within the predefined transition window. In a non-limiting example, the capacitance C of the offset capacitor 36 is approximately 2.2 microfarad (2.2 μF).

(17) The APT PMIC 28 also includes a control circuit 48, which can be a microcontroller, a microprocessor, of a field-programmable gate array (FPGA), as an example. The control circuit 48 is configured to receive the time-variant APT target voltage V.sub.CC-TGT and cause the modulated offset voltage V.sub.OFF to be generated across the offset capacitor 36 based on the time-variant APT target voltage V.sub.CC-TGT within the predefined transition window. The control circuit 48 may be configured to determine a time-variant offset target voltage V.sub.OFF-TGT based on the time-variant APT target voltage V.sub.CC-TGT. The time-variant offset voltage V.sub.OFF-TGT is associated with a time-variant offset voltage target 50 that is proportionally related to the time-variant voltage target 38.

(18) In a non-limiting example, the control circuit 48 can derive the time-variant offset voltage V.sub.OFF-TGT from the time-variant APT voltage V.sub.CC-TGT based on a programmable gain coefficient K (0<K<1). Accordingly, the control circuit 48 can cause the modulated offset voltage V.sub.OFF to be generated based on the time-variant offset target voltage V.sub.OFF-TGT within the predefined transition window. In a specific but non-limiting example, the control circuit 48 can control the MCP 44 to adjust the low-frequency voltage V.sub.DC according to rises and falls of the time-variant offset voltage target 50 to thereby adjust the low-frequency current I.sub.DC. Thus, according to the equation (Eq. 1), the control circuit 48 can cause the modulated offset voltage V.sub.OFF to increase or decrease accordingly.

(19) FIG. 3 is a graphic diagram providing an exemplary illustration as to how the APT PMIC 28 in FIG. 2 can be configured to quickly adapt the APT voltage V.sub.CC between two consecutive OFDM symbols 52 and 54. As shown in FIG. 3, a transition from the preceding OFDM symbol 52 to the succeeding OFDM symbol 54 begins at time T.sub.0 and ends at time T.sub.1. In this regard, time T.sub.0 and T.sub.1 collectively define the CP (a.k.a. predefined transition window) between the two consecutive OFDM symbols 52 and 54. Accordingly, the APT PMIC 28 must adapt the sum of the APT voltage V.sub.CC and the modulated voltage V.sub.OFF (V.sub.CC+V.sub.OFF), which is outputted to the power amplifier 40 in FIG. 2, on or before time T.sub.1.

(20) In a non-limiting example, at time T.sub.0, the control circuit 48 receives the time-variant APT target voltage V.sub.CC-TGT that indicates a rise of the APT voltage V.sub.CC from a first voltage level V.sub.1 (e.g., 1 V) to a second voltage level V.sub.2 (e.g., 3.5 V) in the OFDM symbol 54. Accordingly, the control circuit 48 generates the time-variant offset target voltage V.sub.OFF-TGT that rises at time T.sub.0. The control circuit 48 controls the MCP 44 to increase the low-frequency voltage V.sub.DC to thereby increase the low-frequency current I.sub.DC. The control circuit 48 may determine the low-frequency voltage V.sub.DC based on an equation (Eq. 2) below.
V.sub.DC≤(1−K)*V.sub.CC-TGT−N.sub.headroom  (Eq. 2)

(21) In the equation (Eq. 2), K represents the programmable gain coefficient and N.sub.headroom represents a headroom voltage of the voltage amplifier 32. For example, if the time-variant APT target voltage V.sub.CC-TGT rises from 1 V to 3.5 V, K equals 0.7, and N.sub.headroom equals 0.3 V, the control circuit 48 can control the MCP 44 to generate the low-frequency voltage V.sub.DC at approximately 0.75 V according to Eq. 2.

(22) Concurrent to increasing the modulated offset voltage V.sub.OFF, the voltage amplifier 32 also increases the initial APT voltage V′.sub.CC. As such, it is possible to ramp up the APT voltage V.sub.CC on or before time T.sub.1. Notably, at time T0, the voltage amplifier 32 may have to ramp up the initial APT voltage V′.sub.CC while the offset capacitor 36 is being charged by the low-frequency current I.sub.DC toward the modulated offset voltage V.sub.OFF. When the modulated offset voltage V.sub.OFF increases to a sufficient level at time T′.sub.1, the voltage amplifier 32 can start reducing the initial APT voltage V′.sub.CC to help improve operating efficiency.

(23) With reference back to FIG. 2, the voltage amplifier 32 is biased by one of a lower supply voltage V.sub.SUPL and a higher supply voltage V.sub.SUPH (V.sub.SUPH>V.sub.SUPL) that are generated by a supply voltage circuit 56. The control circuit 48 may control the supply voltage circuit 56 to provide the higher supply voltage V.sub.SUPH to the voltage amplifier 32 at time T.sub.0 to help ramp up the APT voltage V.sub.CC while the offset capacitor 36 is being charged. At time T′.sub.1, the control circuit 48 may control the supply voltage circuit 56 to provide the lower supply voltage V.sub.SUPL to the voltage amplifier 32 to help improve operating efficiency of the voltage amplifier 32.

(24) The APT PMIC 28 can be configured to further include a target voltage circuit 58. In a non-limiting example, the target voltage circuit 58 receives a number of coded voltage words 60 each defining a respective level of the time-variant APT target voltage V.sub.CC-TGT. For instance, in the example shown in FIG. 3, one of the coded voltage words 60 indicates the first voltage level V.sub.1 (1 V) and another one of the coded voltage words 60 indicates the second voltage level V.sub.2 (3.5 V). Accordingly, the target voltage circuit 58 can generate the time-variant APT target voltage V.sub.CC-TGT based on the coded voltage words 60.

(25) Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.