Load Regulation for LDO with Low Loop Gain

Abstract

Circuits and methods for maintaining loop stability and good load regulation in low loop gain LDO regulator circuits. Embodiments encompass LDO regulator circuits that include an offset error correction circuit that generates an opposing voltage V.sub.OFFSET as a function of load current to substantially cancel out variations in V.sub.OUT that would otherwise occur due to load regulation limitations of the LDO regulator circuits. Embodiments use V.sub.OFFSET to imbalance currents in differential paths in a last-stage LDO error-amplifier so that an offset is propagated to a pair of inputs to the error-amplifier, thereby altering the output voltage V.sub.OUT to a corrected value. Benefits include improved LDO load regulation even when feedback loop gain is low, the available of both digital and analog implementations, high LDO accuracy and less variation of the output voltage V.sub.OUT, and suitability for implementation in integrated circuits for applications such as high precision power supplies.

Claims

1. An offset error correction circuit configured to be coupled to a low-dropout (LDO) regulator circuit that includes a feedback loop, an input for a voltage, and an output for a regulated voltage V.sub.OUT, the offset error correction circuit configured to generate an offset correction signal as a function of a load current I.sub.LOAD through the coupled LDO regulator circuit, the offset correction signal being provided to the coupled LDO regulator circuit so as to adjust the open-loop gain of the coupled LDO regulator circuit.

2. A low-dropout (LDO) regulator circuit including an input for a voltage, an output for a regulated voltage V.sub.OUT, and an offset error correction circuit that generates an offset current I.sub.OFFSET as a function of a load current I.sub.LOAD through the LDO regulator circuit, wherein the offset current I.sub.OFFSET produces a correction signal V.sub.OFFSET that substantially offsets variations in the regulated voltage V.sub.OUT due to closed-loop operation of the LDO regulator circuit.

3. The invention of claim 2, wherein the variations in the regulated voltage V.sub.OUT result from a low loop gain of the LDO regulator circuit.

4. The invention of claim 2, wherein the LDO regulator circuit includes a first stage that includes the input for the voltage and a second stage that outputs the regulated voltage V.sub.OUT, wherein the offset error correction circuit is coupled to sense the load current I.sub.LOAD through the input of the first stage.

5. The invention of claim 2, wherein the LDO regulator circuit includes a first stage that includes the input for the voltage and a second stage that outputs the regulated voltage V.sub.OUT, wherein the offset current I.sub.OFFSET generated by the offset error correction circuit is applied to the second stage to generate the correction signal V.sub.OFFSET.

6. The invention of claim 2, wherein the LDO regulator circuit includes a first stage that includes the input for the voltage and a second stage that outputs the regulated voltage V.sub.OUT, wherein the offset current I.sub.OFFSET generated by the offset error correction circuit is applied to the second stage and summed with currents flowing through a differential error amplifier circuit so as to substantially offset variations in the regulated voltage V.sub.OUT due to closed-loop operation of the LDO regulator circuit.

7. The invention of claim 2, wherein the LDO regulator circuit includes a first loop that includes the input for the voltage and a second loop that outputs the regulated voltage V.sub.OUT, wherein the offset error correction circuit is coupled to sense the load current I.sub.LOAD through the input of the first loop, and wherein the offset current I.sub.OFFSET generated by the offset error correction circuit is applied to the second loop to generate the correction signal V.sub.OFFSET.

8. The invention of claim 2, wherein the LDO regulator circuit further includes an error amplifier having a first differential input and a second differential input controlling the generation of the regulated voltage V.sub.OUT, the first differential input configured to pass a current reduced by the offset current I.sub.OFFSET and the second differential input configured to pass a current increased by the offset current I.sub.OFFSET.

9. The invention of claim 2, wherein the offset error correction circuit includes: (a) a sense field effect transistor (FET) configured to sense the load current I.sub.LOAD through the LDO regulator circuit and generate a sense current I.sub.SENSE as a function of the load current I.sub.LOAD; and (b) an offset current generator, coupled to the sense FET, configured to generate the offset current I.sub.OFFSET as a function of the sense current I.sub.SENSE.

10. The invention of claim 9, wherein the offset current generator includes: (a) a current transform circuit coupled to the sense FET and configured to convert the sense current I.sub.SENSE to a sense voltage V.sub.SENSE; (b) an analog-to-digital converter coupled to the current transform circuit and configured to convert a magnitude of the sense voltage V.sub.SENSE to a digital value comprising N bits; and (c) a digital-to-analog converter current generator coupled to the analog-to-digital converter and configured to convert the digital value comprising N bits to the offset current I.sub.OFFSET.

11. The invention of claim 9, wherein the offset current generator includes a current mirror circuit coupled to the sense FET and configured to amplify the sense current I.sub.SENSE to the offset current I.sub.OFFSET.

12. A low-dropout (LDO) regulator circuit including: (a) an input for a voltage; (b) an output for a regulated voltage V.sub.OUT; (c) an offset error correction circuit that generates an offset current I.sub.OFFSET as a function of a load current I.sub.LOAD through the LDO regulator circuit; (d) voltage regulation circuitry including an error amplifier having a first differential input and a second differential input controlling the generation of the regulated voltage V.sub.OUT, the first differential input configured to pass a current reduced by the offset current I.sub.OFFSET and the second differential input configured to pass a current increased by the offset current I.sub.OFFSET, thereby substantially cancelling out variations in V.sub.OUT that would otherwise occur due to load regulation limitations of the LDO regulator circuit.

13. The invention of claim 12, wherein the offset error correction circuit includes: (a) a sense field effect transistor (FET) configured to sense the load current I.sub.LOAD through the LDO regulator circuit and generate a sense current I.sub.SENSE as a function of the load current I.sub.LOAD; and (b) an offset current generator, coupled to the sense FET, configured to generate the offset current I.sub.OFFSET as a function of the sense current I.sub.SENSE.

14. The invention of claim 13, wherein the offset current generator includes: (a) a current transform circuit coupled to the sense FET and configured to convert the sense current I.sub.SENSE to a sense voltage V.sub.SENSE; (b) an analog-to-digital converter coupled to the current transform circuit and configured to convert a magnitude of the sense voltage V.sub.SENSE to a digital value comprising N bits; and (c) a digital-to-analog converter current generator coupled to the analog-to-digital converter and configured to convert the digital value comprising N bits to the offset current I.sub.OFFSET.

15. The invention of claim 13, wherein the offset current generator includes a current mirror circuit coupled to the sense FET and configured to convert the sense current I.sub.SENSE to the offset current I.sub.OFFSET.

16.-25. (canceled)

Description

DESCRIPTION OF THE DRAWINGS

[0019] FIG. 1 is a block diagram of a generalized prior art electronic circuit powered by an SMPS.

[0020] FIG. 2 is a schematic diagram of a prior art 2-Stage LDO regulator circuit connected to a capacitive and resistive output load.

[0021] FIG. 3 is a graph of gain as a function of frequency for an example high-frequency LDO regulator circuit.

[0022] FIG. 4A is a diagram of an equivalent model for a conventional LDO.

[0023] FIG. 4B is a graph showing the degree of variation in V.sub.OUT relative to I.sub.LOAD for a conventional LDO regulator circuit having a low loop gain.

[0024] FIG. 4C is a graph showing the degree of variation in V.sub.OUT relative to I.sub.LOAD for a conventional LDO regulator circuit having a high loop gain.

[0025] FIG. 5A is a diagram of an equivalent model for a low loop gain LDO in accordance with the present invention.

[0026] FIG. 5B is a two-part graph showing the degree of variation in V.sub.OUT relative to I.sub.LOAD for a low loop gain LDO regulator circuit with and without error correction in accordance with the present invention.

[0027] FIG. 6 is a block diagram of one embodiment a low loop gain LDO regulator circuit coupled to a capacitive and resistive output load and including an error correction circuit in accordance with the present invention.

[0028] FIG. 7 is a schematic diagram of one embodiment of a modified error amplifier coupled to an offset current generator that generates an offset current I.sub.OFFSET as a function of I.sub.SENSE.

[0029] FIG. 8A is a schematic diagram showing an embodiment of a current sensing circuit and a digital offset current generator.

[0030] FIG. 8B is a schematic diagram showing an embodiment of a DAC current generator.

[0031] FIG. 9 is a graph showing load current and output voltages (with and without error correction) as a function of time for one modeled instance of the low loop gain LDO regulator circuit of FIG. 6, using a digital offset current generator.

[0032] FIG. 10 is a schematic diagram showing an embodiment of a current sensing circuit and an analog offset current generator.

[0033] FIG. 11 is a graph showing load current and output voltages (with and without error correction) as a function of time for one modeled instance of the low loop gain LDO regulator circuit of FIG. 6, using an analog offset current generator.

[0034] FIG. 12 is a process flow chart showing a first method for maintaining loop stability and good load regulation in an LDO regulator circuit that includes an input for an unregulated voltage and an output for a regulated voltage V.sub.OUT.

[0035] FIG. 13 is a process flow chart showing a first method for maintaining loop stability and good load regulation in an LDO regulator circuit that includes an input for an unregulated voltage and an output for a regulated voltage V.sub.OUT.

[0036] Like reference numbers and designations in the various drawings indicate like elements.

DETAILED DESCRIPTION

[0037] The present invention encompasses circuits and methods for maintaining loop stability and good load regulation in LDO regulator circuits having a low loop gain.

[0038] High frequency (e.g., around 1 MHz) low drop-out (LDO) regulator circuits having a high PSRR are generally designed to have feedback loops that have higher Unity Gain Bandwidths (UGB) around their highest frequency. For example, FIG. 3 is a graph 300 of gain as a function of frequency for an example high-frequency LDO regulator circuit. In the illustrated example, if the cutoff frequency [F3 dB pole=1/(2*π*C.sub.LOAD*R.sub.LOAD)] is at about 10 KHz, then a low loop gain of 40 dB is required to have UGB at 1 MHz.

[0039] A design challenge for LDO regulator circuits is that low loop gains limit the ability of a conventional feedback loop to correct errors in the output due to load variations—that is, conventional LDO regulator circuits with low loop gains generally have low load regulation capability.

[0040] For example, FIG. 4A is a diagram 400 of an equivalent model for a conventional LDO. In the illustrated example, a voltage source V.sub.REF2/β is coupled in series with a load R.sub.OUT. Load regulation for this equivalent model is defined as:

[00001]$\begin{array}{cc}\mathrm{Load}\mathrm{Regulation}=\frac{\Delta V_{\mathrm{OUT}}}{\Delta I_{\mathrm{LOAD}}}=R_{OUT}=\frac{\mathrm{ro\_pass}2}{1+A\beta }& \mathrm{EQ}.1\end{array}$

[0041] In Equation 1, “ro_pass2” is the small-signal resistance between the drain and the source of a MOSFET due to a channel-length modulation effect when the transistor is in saturation, and Aβ is the LDO Stage 2 loop gain, where “A” is the feedforward gain of the feedback loop, and β is the feedback ratio and is less than one. Further, V.sub.OUT=(V.sub.REF2/β)−I.sub.LOAD*R.sub.OUT.

[0042] FIG. 4B is a graph 420 showing the degree of variation in V.sub.OUT relative to I.sub.LOAD for a conventional LDO regulator circuit having a low loop gain. FIG. 4C is a graph 440 having a high loop gain. In both graphs, V.sub.OUT is equal to V.sub.REF2/β in a no-load condition. However, in a full-load condition, V.sub.OUT is much less than V.sub.REF2/β for the low loop gain LDO regulator circuit compared to V.sub.OUT for the high loop gain LDO regulator circuit. Accordingly, the amount of variation in V.sub.OUT in the full-load condition relative to the no-load condition is much greater for the low loop gain LDO regulator circuit than for the high loop gain LDO regulator circuit. However, achieving the results shown in FIG. 4C is not known to be possible for conventional low loop gain LDO regulator circuits, which behave as shown in FIG. 4B.

[0043] One goal of the present invention is to achieve good load regulation capability for LDO regulator circuits having low loop gains. Embodiments of the present invention encompass LDO regulator circuits that include an offset error correction circuit that generates an opposing voltage V.sub.OFFSET as a function of load current I.sub.LOAD to substantially cancel out variations in V.sub.OUT that would otherwise occur due to load regulation limitations of the LDO regulator circuits.

[0044] For example, FIG. 5A is a diagram 500 of an equivalent model for a low loop gain LDO in accordance with the present invention. In the illustrated example, a voltage source V.sub.REF2/β and an offset voltage source V.sub.OFFSET are coupled in series with a the LDO output impedance R.sub.OUT. The offset voltage source V.sub.OFFSET should have an opposite polarity relative to the voltage drop across R.sub.OUT (i.e., I.sub.LOAD*R.sub.OUT) in order to correct the output error due to load regulation. Accordingly, for this model, V.sub.OUT=(V.sub.REF2/β)+V.sub.OFFSET−(I.sub.LOAD*R.sub.OUT).

[0045] FIG. 5B is a two-part graph 520 showing the degree of variation in V.sub.OUT relative to I.sub.LOAD for a low loop gain LDO regulator circuit with and without error correction in accordance with the present invention. Part 1 of the graph illustrates V.sub.OUT as a function of load current UAL) without error correction, showing essentially the same degree of variation of V.sub.OUT between no-load and full-load conditions as is shown in FIG. 4B. Part 1 of the graph also shows the opposing correction provided by V.sub.OFFSET as a function of load current I.sub.LOAD in accordance with the present invention. Part 2 of the graph illustrates V.sub.OUT as a function of load current I.sub.LOAD after error correction (that is, after V.sub.OFFSET is added to the uncorrected V.sub.OUT), showing essentially the same relatively small degree of variation of V.sub.OUT between no-load and full-load conditions as is shown in FIG. 4C, but in a low loop gain LDO regulator circuit.

[0046] A number of circuits can be used to monitor LOAD and generate V.sub.OFFSET in a low loop gain LDO regulator circuit. For example, FIG. 6 is a block diagram 600 of one embodiment a low loop gain LDO regulator circuit 601 coupled to a capacitive and resistive output load 202 and including an error correction circuit in accordance with the present invention. In general, the low loop gain LDO regulator circuit 601 is similar to the LDO regulator circuit 201 of FIG. 2, but with the changes noted below.

[0047] In the illustrated example, the error correction circuit includes a sense FET Msense coupled in parallel with the Stage 1 FET M1. The sense FET Msense may be, for example, a MOSFET, and typically would be quite small compared to FET M1; for example, 1/1000 of the size and the current characteristic of the FET M1. Accordingly, the presence of the sense FET Msense has little or no effect on the overall operation of the low loop gain LDO regulator circuit 601. In the illustrated example, the gate of the sense FET Msense is controlled by the Stage 1 error amplifier 204. A fractional current I.sub.SENSE proportional to the load current I.sub.LOAD passing through the Stage 1 FET M1 (more generally, through the main pass transistor if a more complex Stage 1 circuit is used) passes through the parallel FET Msense to an Offset Current Generator 602.

[0048] The Offset Current Generator 602, another part of the error correction circuit, generates an offset current I.sub.OFFSET from I.sub.SENSE. As described in greater detail below, the Offset Current Generator 602 may be implemented as a digital circuit and/or an analog circuit. The offset current I.sub.OFFSET is coupled to another part of the error correction circuit, a modified error amplifier 608 within Stage 2 of the low loop gain LDO regulator circuit 601.

[0049] In one embodiment, the modified error amplifier 608 uses the offset current I.sub.OFFSET to imbalance the input current to a pair of transistors to create a voltage offset V.sub.OFFSET between the voltages, V.sub.REF2 and V.sub.OUT, applied to the transistor gate inputs. The polarity of the voltage offset V.sub.OFFSET is in the opposite direction from the uncorrected value of V.sub.OUT to reduce the variation in the final, post-correction V.sub.OUT due to load regulation limitations of the low loop gain LDO regulator circuit 601. Thus, V.sub.OFFSET=f(I.sub.OFFSET)=f(I.sub.SENSE)=f(I.sub.LOAD).

[0050] FIG. 7 is a schematic diagram 700 of one embodiment of a modified error amplifier 608 coupled to an offset current generator 602 that generates an offset current I.sub.OFFSET as a function of I.sub.SENSE. Inputs V.sub.REF2 and V.sub.OUT (fed back from the ultimate output of the LDO regulator circuit) are applied to the gates of respective differential FETs M.sub.REF and M.sub.OUT, both coupled to a first current source 702. The combined current through the differential FETs M.sub.REF and M.sub.OUT is I.sub.TAIL. The supply voltage V.sub.SUPPLY to the modified error amplifier 608 is the output of Stage 1 of the low loop gain LDO regulator circuit 601. The output of the modified error amplifier 608 is a voltage, EA_V.sub.OUT, that is applied to the gate of the Stage 2 FET M2 (more generally, through the main pass transistor if a more complex Stage 2 circuit is used).

[0051] The modified error amplifier 608 is configured as a two-stage differential amplifier, each stage comprising two legs. A first leg of the first stage comprises FETs M.sub.EA1 and M.sub.EA2, with FET M.sub.EA3 functioning as a current source. FETs M.sub.OUT and M.sub.EA2 are configured in a folded cascode arrangement, with FET M.sub.EA1 providing bias current. A second leg of the first stage comprises FETs M.sub.EA4 and M.sub.EA5, with FET M.sub.EA6 functioning as a current source. FETs M.sub.REF and M.sub.EA5 are also configured in a folded cascode arrangement, with FET M.sub.EA4 providing bias current.

[0052] A first leg of the second stage comprises FETs MEAT and M.sub.EA8 coupled to a second current source 704, and a second leg of the second stage comprises FETs M.sub.EA9 and M.sub.EA10 coupled to a third current source 706. The first and second legs of the second stage are configured as a current mirror having inputs coupled to respective nodes after the cascode pairs of the first and second legs of the first stage. The differential FETs M.sub.REF and M.sub.OUT are coupled to respective nodes between the cascode pairs of the first and second legs of the first stage.

[0053] An essentially constant current through FET MEAL is shared between FET M.sub.OUT and the path through FETs M.sub.EA2 and M.sub.EA3. Similarly, an essentially constant current through FET M.sub.EA4 is shared between FET M.sub.REF and the path through FETs M.sub.EA5 and M.sub.EA6. The output of the M.sub.EA1/M.sub.EA2 cascode pair influences the current through the first leg of the second stage, while the output of the M.sub.EA4/M.sub.EA5 cascode pair influences the current through the second leg of the second stage.

[0054] In steady-state operation (i.e., V.sub.REF2=V.sub.OUT) and ignoring any contribution by the offset current generator 602 for the moment, the currents through the differential FETs M.sub.REF and M.sub.OUT are equal. However, if (for example) V.sub.OUT becomes less than V.sub.REF2, then the current through FET M.sub.OUT will be reduced by an amount A, resulting in an offsetting increase of current through FET M.sub.EA2 in the first leg of the first stage by A. The reduced current through FET M.sub.OUT by Δ will result in an offsetting increase of current through FET M.sub.REF by A. As a result, the current through FET M.sub.EA5 in the second leg of the first stage will decrease by A. The imbalance of currents in the first stage will propagate to the second stage, resulting in a decrease in EA_V.sub.OUT.

[0055] Taking into account the offset current generator 602, the basic idea is to imbalance currents in any differential path so that an offset is propagated to the pair of inputs V.sub.REF2 and V.sub.OUT, thus altering the output voltage EA_V.sub.OUT to a corrected value. The imbalance of currents through the input pair of transistors M.sub.REF and M.sub.OUT results in those transistors having different V.sub.GS values, which creates an offset V.sub.OFFSET=V.sub.GS_MOUT−V.sub.GS_MREF=f(I.sub.OFFSET). In the illustrated example, FETs M.sub.EA1-M.sub.EA3, when suitably biased, provide a current through the FET M.sub.OUT that is equal to one-half of I.sub.TAIL, plus I.sub.OFFSET from the current generator 602. FETs M.sub.EA4-M.sub.EA6, when suitably biased, provide a current through the FET M.sub.REF that is equal to one-half of I.sub.TAIL, minus I.sub.OFFSET from the current generator 602. Note that bias circuitry is not shown for to avoid clutter.

[0056] In greater detail, the offset current generator 602 is coupled to the respective second legs of the first and second stages as shown, and accordingly can influence the current flow through those legs. When the offset current generator 602 generates I.sub.OFFSET, that amount of current is subtracted from the current passing through FET M.sub.REF, and accordingly, that amount of current is added to the current passing through the FET M.sub.OUT, so that while the total current through differential FETs M.sub.REF and M.sub.OUT remains equal to I.sub.TAIL, an imbalance of currents exists through the input pair of transistors M.sub.REF and M.sub.OUT.

[0057] Of note, the point of connection of the current generator 602 is preferably chosen to be a relatively low impedance point so that loading by the circuitry generating I.sub.OFFSET does not affect pole locations within the low loop gain LDO regulator circuit 601 and the loop remains stable.

[0058] FIG. 8A is a schematic diagram 800 showing an embodiment of a current sensing circuit and a digital offset current generator 802. The digital offset current generator 802 may be used as the current generator 602 in FIG. 6. The current I.sub.SENSE through the FET M.sub.SENSE (see FIG. 6) is coupled to a current transform circuit, comprising resistor R in this example, to generate a voltage V.sub.SENSE, which is applied to an analog-to-digital converter (ADC) 804. The ADC 804 outputs a digital value comprising N bits that correspond to the magnitude of the input analog voltage V.sub.SENSE. For high frequency LDO regulator circuits, the ADC 804 should be fast, such as a flash ADC. As is known in the art, a flash ADC uses a linear voltage ladder with a comparator at each “rung” of the ladder to compare an input voltage to successive reference voltages to provide direct conversion of the magnitude of an analog voltage to a corresponding digital value.

[0059] In the illustrated example, the N bits from the ADC 804 may be applied to a digital-to-analog converter (DAC) current generator 806 to generate I.sub.OFFSET as a function of I.sub.SENSE. FIG. 8B is a schematic diagram 850 showing an embodiment of a DAC current generator 806. A set of parallel switch legs each comprise a FET M in series with a switch D<n>, where n is from 1 to N. The gates of each FET M are biased by a diode-connected FET M0 coupled to a voltage source V.sub.IN. In operation, the amount of current I.sub.OFFSET that can pass through the DAC current generator 806 is determined by the number of switches D<n> that are closed and the bias level for the FETs M. Thus, I.sub.OFFSET is a function of I.sub.SENSE, which is a function of I.sub.LOAD.

[0060] In alternative embodiments, V.sub.SENSE may be used directly within the modified error amplifier 608 to imbalance currents in any differential path so that an offset is propagated to the pair of inputs V.sub.REF2 and V.sub.OUT, thus altering the output voltage EA_V.sub.OUT to a corrected value. For example V.sub.SENSE may be used to bias the differential FETs M.sub.REF and M.sub.OUT so as to create a difference in the V.sub.GS of those FETs and thereby alter the flow of current through them to correct the load-induced error in V.sub.OUT that would otherwise occur.

[0061] FIG. 9 is a graph 900 showing load current and output voltages (with and without error correction) as a function of time for one modeled instance of the low loop gain LDO regulator circuit 601 of FIG. 6, using a digital offset current generator 802. Graph line 902 shows variations in the load current I.sub.LOAD from 0 A to about 200 mA and back, over a short period of time. Dotted graph line 904 shows what the corresponding value of V.sub.OUT would be without error correction by the digital offset current generator 802. Bold graph line 906 shows what the corresponding value of V.sub.OUT would be with error correction by the digital offset current generator 802. In this particular example, the error in V.sub.OUT was reduced from about 12 mV (about 2% of V.sub.OUT) to about 3 mV (about 0.5% of V.sub.OUT).

[0062] FIG. 10 is a schematic diagram 1000 showing an embodiment of a current sensing circuit and an analog offset current generator 1002. The analog offset current generator 1002 may be used as the current generator 602 in FIG. 6, and has the advantage that V.sub.OUT variation as a function of load current I.sub.LOAD is continuous and smooth. The current I.sub.SENSE through the FET M.sub.SENSE (see FIG. 6) is coupled to a current mirror comprising commonly-biased FET M.sub.S and M.sub.O. The current I.sub.SENSE is mirrored and amplified through the larger FET M.sub.O as the offset current I.sub.OFFSET. Thus, I.sub.OFFSET is a function of I.sub.SENSE, which is a function of I.sub.LOAD.

[0063] FIG. 11 is a graph 1100 showing load current and output voltages (with and without error correction) as a function of time for one modeled instance of the low loop gain LDO regulator circuit 601 of FIG. 6, using an analog offset current generator 1002. Graph line 1102 shows variations in the load current I.sub.LOAD from 0 A to about 200 mA and back, over a short period of time. Dotted graph line 1104 shows what the corresponding value of V.sub.OUT would be without error correction by the analog offset current generator 1002. Bold graph line 1106 shows what the corresponding value of V.sub.OUT would be with error correction by the analog offset current generator 1002. In this particular example, the error in V.sub.OUT was reduced from about 8.5 mV (about 1.4% of V.sub.OUT) to about 2.3 mV (about 0.4% of V.sub.OUT). As should be clear from the graph 1100, the load regulation of V.sub.OUT when error corrected is smooth, which may have advantages in some applications where noise spikes may be problematic.

[0064] Benefits of embodiments of the invention include improved LDO load regulation even when feedback loop gain is low (noting that the error correction circuitry described above can be used with high-gain LDO regulator circuits), the available of both digital and analog implementations, high LDO accuracy and less variation of the output voltage V.sub.OUT, and suitability for implementation in integrated circuits (ICs) for applications such as high precision power supplies.

[0065] Methods

[0066] Another aspect of the invention includes methods for maintaining loop stability and good load regulation in a low-dropout (LDO) regulator circuit. For example, FIG. 12 is a process flow chart 1200 showing a first method for maintaining loop stability and good load regulation in an LDO regulator circuit that includes an input for a voltage (generally an unregulated voltage) and an output for a regulated voltage V.sub.OUT. The method includes generating an offset correction signal as a function of a load current I.sub.LOAD through the LDO regulator circuit and applying the offset correction signal to the LDO regulator circuit to substantially cancel out variations in V.sub.OUT resulting from a low feedback loop gain of the LDO regulator circuit (Block 1202).

[0067] As another example, FIG. 13 is a process flow chart 1300 showing a first method for maintaining loop stability and good load regulation in an LDO regulator circuit that includes an input for a voltage (generally an unregulated voltage) and an output for a regulated voltage V.sub.OUT. The method includes: generating an offset current I.sub.OFFSET as a function of a load current I.sub.LOAD through the LDO regulator circuit (Block 1302); and applying the offset current I.sub.OFFSET to an error amplifier having a first differential input and a second differential input controlling the generation of the regulated voltage V.sub.OUT, such that the first differential input passes a current reduced by the offset current I.sub.OFFSET and the second differential input passes a current increased by the offset current I.sub.OFFSET, thereby substantially cancelling out variations in V.sub.OUT that would otherwise occur due to load regulation limitations of the LDO regulator circuit (Block 1304).

[0068] Additional aspects of the above method may include one or more of the following: wherein the LDO regulator circuit is a low loop gain LDO regulator circuit; wherein the LDO regulator circuit further includes an error amplifier having a first differential input and a second differential input controlling the generation of the regulated voltage V.sub.OUT, further including applying the offset current I.sub.OFFSET to the first differential input so that the first differential input passes a current reduced by the offset current I.sub.OFFSET, and applying the offset current I.sub.OFFSET to the second differential input so that the second differential input passes a current increased by the offset current I.sub.OFFSET; wherein generating the offset current I.sub.OFFSET includes configuring a sense field effect transistor (FET) to sense the load current I.sub.LOAD through the LDO regulator circuit and generate a sense current I.sub.SENSE as a function of the load current I.sub.LOAD, and configuring an offset current generator, coupled to the sense FET, to generate the offset current I.sub.OFFSET as a function of the sense current I.sub.SENSE; wherein the offset current generator includes a current transform circuit coupled to the sense FET and configured to convert the sense current I.sub.SENSE to a sense voltage V.sub.SENSE, an analog-to-digital converter coupled to the current transform circuit and configured to convert a magnitude of the sense voltage V.sub.SENSE to a digital value comprising N bits, and a digital-to-analog converter current generator coupled to the analog-to-digital converter and configured to convert the digital value comprising N bits to the offset current I.sub.OFFSET; and/or wherein the offset current generator includes a current mirror circuit coupled to the sense FET and configured to amplify the sense current I.sub.SENSE to the offset current I.sub.OFFSET.

[0069] Fabrication Technologies & Options

[0070] The term “MOSFET”, as used in this disclosure, includes any field effect transistor (FET) having an insulated gate whose voltage determines the conductivity of the transistor, and encompasses insulated gates having a metal or metal-like, insulator, and/or semiconductor structure. The terms “metal” or “metal-like” include at least one electrically conductive material (such as aluminum, copper, or other metal, or highly doped polysilicon, graphene, or other electrical conductor), “insulator” includes at least one insulating material (such as silicon oxide or other dielectric material), and “semiconductor” includes at least one semiconductor material.

[0071] As used in this disclosure, the term “radio frequency” (RF) refers to a rate of oscillation in the range of about 3 kHz to about 300 GHz. This term also includes the frequencies used in wireless communication systems. An RF frequency may be the frequency of an electromagnetic wave or of an alternating voltage or current in a circuit.

[0072] Various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice. Various embodiments of the invention may be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, embodiments of the invention may be implemented in other transistor technologies such as bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies. However, embodiments of the invention are particularly useful when fabricated using an SOI or SOS based process, or when fabricated with processes having similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (i.e., radio frequencies up to and exceeding 50 GHz). Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design.

[0073] Voltage levels may be adjusted, and/or voltage and/or logic signal polarities reversed, depending on a particular specification and/or implementing technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device sizes, serially “stacking” components (particularly FETs) to withstand greater voltages, and/or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and/or to provide additional functionality without significantly altering the functionality of the disclosed circuits.

[0074] Circuits and devices in accordance with the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be fabricated as integrated circuits (ICs), which may be encased in IC packages and/or in modules for ease of handling, manufacture, and/or improved performance. In particular, IC embodiments of this invention are often used in modules in which one or more of such ICs are combined with other circuit blocks (e.g., filters, amplifiers, passive components, and possibly additional ICs) into one package. The ICs and/or modules are then typically combined with other components, often on a printed circuit board, to form an end product such as a cellular telephone, laptop computer, or electronic tablet, or to form a higher level module which may be used in a wide variety of products, such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless communication.

CONCLUSION

[0075] A number of embodiments of the invention have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, and/or parallel fashion.

[0076] It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. In particular, the scope of the invention includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the claims below. (Note that the parenthetical labels for claim elements are for ease of referring to such elements, and do not in themselves indicate a particular required ordering or enumeration of elements; further, such labels may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting labeling sequence).