Intelligent multi-level voltage gate driving system for semiconductor power devices

Abstract

An improved gate driver using a microcontroller (uC), a voltage selector (VS), an adjustable voltage regulator (AVR), and an auxiliary current sinking circuit (ACSC) to actively provide selectable drive signals either higher, lower or equal to the basic on voltage and off voltage drive signals for a selected semiconductor device thereby providing an active voltage-mode gate driver for actively speeding up or slowing both the on time and off time transitions of a semiconductor.

Claims

1. An improved gate driver for providing a gate signal to a semiconductor power device controlled by a gate input with a time transition, comprising: a power supply providing a main voltage signal; an adjustable voltage regulator providing an adjusted voltage higher than the main voltage signal; a voltage selector receiving both the main voltage signal and the adjusted voltage signal and selectively applying one of the received voltages as a selected voltage signal; and a gate driver with a gate terminal, a pull up terminal, and a pull down terminal, the gate driver receiving the selected voltage signal at the pull up terminal and the pull down terminal, wherein the main voltage signal controls the semiconductor power device for a first time period and the adjusted voltage signal controls the semiconductor power device for a second time period shorter than the first time period; and the gate driver receiving the main voltage signal after the second time period ends.

2. The improved gate driver of claim 1, further comprising: an auxiliary current sinking circuit connected through the voltage selector.

3. The improved gate driver of claim 1, further comprising: an auxiliary current sinking circuit connected through the gate driver.

4. The improved gate driver of claim 1, further comprising: an auxiliary current sinking circuit connected through both the voltage selector and the gate driver.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

(1) In the following drawings, which form a part of the specification and which are to be construed in conjunction therewith, and in which like reference numerals have been employed throughout wherever possible to indicate like parts in the various views:

(2) FIG. 1 shows a typical prior art converter schematic.

(3) FIG. 2 shows a schematic of the novel multi-level voltage gate driver.

(4) FIG. 3 shows a working principle of the auxiliary current sinking circuit.

(5) FIG. 4 shows a switching waveform of the gate driver.

(6) FIG. 5 shows a flow chart of the optimization algorithm.

(7) FIG. 6 shows a fast turn-on process of the voltage selector.

(8) FIG. 7 shows a fast turn-off process of the voltage selector.

(9) FIG. 8 shows a slow turn-on process of the voltage selector.

(10) FIG. 9 shows a slow turn-off process of the voltage selector.

(11) FIG. 10 shows a DPT setup schematic.

(12) FIG. 11 shows an experimental setup photo.

(13) FIG. 12 shows a DPT result where the active gate driver can adjust the V.sub.adj2, from 3.5 V to 5.5 V to change the slew rate of V.sub.ds and I.sub.ds.

DETAILED DESCRIPTION OF THE INVENTION

(14) As shown in FIG. 1 of the drawings, one exemplary embodiment of the present invention is generally shown as a buffered multi-level voltage gate driver 100 to dynamically control the slew rates of SiC power devices, which are known for their high-speed switching transients. These fast transients are beneficial because they enable high-frequency converters and lower switching power losses. However, the fast transients also interact with circuit parasitic inductance and capacitance, resulting in undesirable side effects. Such effects are false turn-on of a device, which could result in a short circuit and device failure. Additionally, voltage overshoot across the device can occur, which may reduce the device's lifetime, and thus result in early failure of a converter or damage surrounding electronics. Electromagnetic interference (EMI) is also a problem due to the fast dv/dt transients. This gate driver solution utilizes a variable voltage level to control the transients, and is implemented in a simple topology that is both convenient and simple to use. The transients can be effectively reduced, or sped up if desired, through the use of an intermediate voltage levels between the highest and lowest switching state.

(15) The conceptual schematics of the buffered multi-level voltage gate driver 100 are as shown in FIG. 2. It consists of a microcontroller (uC), a voltage selector (VS), multiple adjustable voltage regulators (AVR), and an auxiliary current sinking circuit (ACSC).

(16) A. The Working Principle of the Adjustable Voltage Regulators

(17) The microcontroller is used to interpret the feedback signals and translate them into physical changes in the driver voltage output. The feedback signals are V.sub.BUS and the drain current I.sub.O, The microcontroller determines the driver output voltage, V.sub.dr, based on the feedback signal using a lookup table program. The lookup table is formulated through the testing results of power devices, which may have varying parameters and switching characteristics. Based on the selected V.sub.dr and duration, the microcontroller will change the control signal to control the AVR and VS.

(18) The adjustable voltage regulator provides the signal for each V.sub.adj signal. Thus, each AVR has a V.sub.adj as represented by either V.sub.adj1 or V.sub.adj2 as generated by AVR1 and AVR2. Each AVR is an analog adder circuit with an inverted voltage amplifier. The output voltage of the AVR is controlled by adjusting the input resistance connected in parallel. The schematic of the AVR2 is shown in FIG. 2 with AVR 1 having a similar schematic.

(19) For each position of the AVR, V.sub.adj is the voltage for the turn-on process or the voltage for the turn-off process, respectively. This output voltage is calculated by:

(20) $V_{\mathrm{adj}}=V_{\mathrm{cri}}\left(\frac{1}{R_0}+\frac{S_{a1}}{R_1}+\frac{S_{a2}}{R_2}.Math.\frac{S_{an}}{R_n}\right)R_X\frac{R_8}{R_9}$
S.sub.a1, S.sub.a2 . . . S.sub.an are the control signals from the microcontroller which are either fully high or fully low to control the adjust voltage. V.sub.ctr is the output voltage level of the controller.

(21) V.sub.ON and V.sub.OFF are the high-level and low-level voltages supplied from the isolated power supply which are set to be the normal turn-on voltage and normal turn-off voltage for the power device. These two voltage levels are chosen based on the recommendation on the power device's datasheet.

(22) The microcontroller calculates the current at every switching cycle. The algorithm to determine the V.sub.dr profile is based on the V.sub.BUS and I.sub.O feedback signal and the model of the power module. Different power modules have different switching characteristics.

(23) Compared with the conventional two-level turn-off waveform, the waveform provided by this gate driver has an additional first level. The conventional two-level turn-off waveform has the disadvantage of a long switching transient due to a long turn-off delay. Since the turn-off delay time does not have high dv/dt or di/dt, a short turn-off delay has no adverse effects, thus a short initial voltage is generated to reduce this delay time, compensating for some of the length due to the increased time during the main switching interval.

(24) B. The Auxiliary Current Sinking Circuit (ACSC)

(25) The ACSC is assisting to sink the gate current when the power device is switching off. It should be noted that the power device can be any type of voltage-driven semiconductor power device, such as a Si or SiC MOSFET or IGBT. To simplify the statement, in the following section, a MOSFET is used as an example.

(26) The ACSC consists of a N-BJT, a capacitor Ca, and a resistor Ra. It is used for preventing false trigger caused by crosstalk noise. This invention utilizes this circuit to assist the AVR to sink gate current. When the power MOSFET is switching off, the gate charge in the junction of the MOSFET will flow back to the AVR. Since the current sinking capability of the Op Amp is low, the ACSC will help the AVR sink some part of gate current and prevent a false trigger.

(27) The working principle of the ACSC is introduced in detail in FIG. 3. When the gate current is flowing back to the AVR, there will be voltage Va on the resistor Ra. When Va is higher than the threshold voltage of the N-BJT, the BJT will open and some gate current will flow into the capacitor Ca. In this case, the current flowing to the AVR will be reduced and the false trigger probability will decrease.

(28) C. The Working Principle of the Voltage Selector

(29) The VS is also controlled by the microcontroller. Its schematics are also shown in FIG. 2. The multi-level gate driver described in this disclosure consists of three buffers that can be configured in a variety of ways depending on the desired effects on the device, either to speed up or slow down the switching transients, through the control voltages applied at each of the buffers. The three buffers are controlled by the signals from the microcontroller, S1, S2 and S3. The main gate driver buffer, Buffer 1, has the same control signal as the converter. In other words, the signal of Buffer 1 is the same with the PWM signal from the main controller unit of the converter. Buffer 1 provides the final output to the power device. Buffer 3 serves as the turn-on voltage changer which provides two possible voltage levels to the positive pole of the main buffer. Buffer 2 serves as the turn-off voltage changer, providing two possible voltage levels at the turn-off. The output of Buffer 2 is connected to the negative pole of Buffer 1. Since Buffer 3 and Buffer 2 are connected in cascaded way to Buffer 1, the gate driver scheme can be called a cascaded topology.

(30) There are five operation modes for the AGD that can be achieved through the use of this gate driver. Through the combination of different turn-on and turn-off processes, these modes can be generated.

(31) The gate driver operates in five possible modes:

(32) 1: Conventional drive (i.e. single turn-on, single turn-off). For this case, no active driving technologies are used. The signals of buffer 2 and buffer 3 are always pulled down to low level.

(33) 2: Speed-up mode (i.e. fast turn-on, fast turn-off). It is used for the case when the parasitics on the PCB are very low. The switching of the power device can be sped up to reduce the switching losses and increase the switching frequency of the converter. Also, this mode is suitable for the power MOSFET in some occasions such as the radiative frequency (RF) or high power density converter.

(34) 3: Slow-down mode (i.e. slow turn-on, slow turn-off). It is used for the case when the switching frequency is not as significant as the EMI issues, such as the high voltage power device. The power losses are not a main factor in this case. A typical application is the high voltage SiC, typically 10 kV, power devices. Due to the high price and high voltage rating of 10 kV devices, the EMI noise suppression is the priority. In this case, slow-down mode is preferred.

(35) 4: Combining mode I (i.e. fast turn-on, slow turn-off). This mode is for some cases when the turn-off EMI and turn-on power losses are too high. In this mode, the turn-on losses are reduced and the turn-off transient are slowed down. This is a commonly used mode for the SiC power devices since the turn-on power losses of the SiC power devices are higher than the turn-off power losses. For the turn-off, the EMI immunity is more significant since the false turn-on and voltage overshoot always happens during the turn-off process. The crosstalk noise caused by hard turn-off is a common cause of a shoot-through event. Therefore, speeding up the turn-on process and slowing down the turn-off process can maximize the benefit and avoid detrimental effects of the SiC power devices under some conditions.

(36) 5: Combining mode II (i.e. slow turn-on, fast turn-off). This mode is not commonly used. It can be used in the case when high di/dt and dv/dt transitions are affecting EMI performance. If the turn-on di/dt dominates the detrimental effects of the switching, that will have high EMI immunity pressure for the upper switch. Also, if the dv/dt does not affect the turn-off process significantly, it can be sped up to reduce the turn-off power losses.

(37) The working principle of all modes will be introduced in details as below. Herein, V.sub.ON and V.sub.OFF are the manufacturer recommended voltage level for normal turn-on and turn-off, respectively. The duration of each stage in the process will be determined by the microcontroller. As introduced in the sections above, the microcontroller selects an optimal intermediate voltage based on the feedback V.sub.BUS and I.sub.O. If the intermediate voltage level, V.sub.BUS, and I.sub.O are determined, the duration of each stage of the switching transient process can be calculated with the mathematical model.

(38) Conventional Drive

(39) In this mode, the gate driver will utilize the main voltage supplied by the power supply, V.sub.ON and V.sub.OFF for turn-on and turn-off, respectively. This is the most common case for a typical gate driver, and will enable the normal switching speed of the device. The switching speed of the power MOSFET will not be controlled by the gate driver. It just depends on the gate resistance.

(40) Fast Turn-on Mode

(41) In this mode, the gate driver will turn on the power device faster with a higher initial drive voltage. The positive pole of buffer 3 is connected to Vadj1 which is the output voltage of an AVR and negative pole is connected to V.sub.ON. The transient turn-on voltage Vadj1 is higher than the normal turn-on voltage. During the turn-on process, buffer 1 is pulled up to select buffer 3. The buffer 3 is also pulled up, and thus V.sub.dr is equal to V.sub.adj1. Since V.sub.adj1>V.sub.ON, the switching process can be accelerated. After the turn-on transient ends, the driver voltage V.sub.dr will change back to V.sub.ON in order to not overstress the gate connection. The operation of this mode is as shown in FIG. 6.

(42) Fast Turn-Off Mode

(43) In this mode, the gate driver will turn off the power device faster with a lower driving voltage. The negative pole of the Buffer 2 is connected to a lower adjustable voltage Vadj2. The positive pole of the buffer 2 is connected to V.sub.OFF. It should be noted that V.sub.th<V.sub.adj2<V.sub.OFF. After the turn-off transient ends, the driver voltage V.sub.dr will change back to normal turn-off voltage. The current route of the fast turn-off mode in the VS is as shown in FIG. 7. When the turn-off PWM signal comes from the microcontroller, Buffer 1 will be pulled down. To speed up the switching process, Buffer 2 will be pulled down and V.sub.adj2 is connected to the gate of the power device. After the turn-off process ends, Buffer 2 will be pulled up and the normal turn-off voltage V.sub.OFF will be connected to the power device. The current flow and the working principle are as plotted in FIG. 7.

(44) Slow Turn-on Mode

(45) In this mode, the gate driver will turn on the power device slower with a lower driving voltage V.sub.adj1. The positive pole of Buffer 3 is connected to V.sub.ON and negative pole is connected to V.sub.adj1 where V.sub.adj1<V.sub.ON. When the turn-off process comes, Buffer 1 is pulled up to select Buffer 3. Before turning-on, Buffer 3 is high. The gate driver will set to V.sub.adj1 to reduce the turn-on transient delay. After the turn-on delay, the drain-source current I.sub.ds start increasing and the drain-source voltage V.sub.ds starts decreasing. To slow down the turn-on dv/dt and di/dt, during the Miller plateau, buffer 3 is pulled down and the V.sub.dr changes to V.sub.adj1. After the drain-source voltage decreases to zero, buffer 3 is pulled up and V.sub.dr increases to V.sub.ON again. The turn-on voltage will only cover the voltage rising time and the current decreasing time of the power devices. The reason why V.sub.dr will change to V.sub.ON during the conducting period is due to the conducting resistance. A lower V.sub.gs will lead to higher on-resistance and higher conduction power losses. The gate current flow and the working principle are plotted in FIG. 8.

(46) Slow Turn-Off Mode

(47) In this mode, the gate driver will turn off the power device slower with a lower driving voltage V.sub.adj2. With a lower level during the Miller plateau period, the dv/dt and di/dt can be reduced. The positive pole of Buffer 2 is connected to a lower voltage, i.e. V.sub.adj2. The negative pole of Buffer 2 is connected to the normal turn-off voltage V.sub.OFF where V.sub.adj2>V.sub.OFF. When the turn-off signal from DSP comes, buffer 1 will be pulled down to select the buffer 2. Buffer 2 is pulled down to output V.sub.OFF first. As mentioned before, the initial turn-off voltage is pulled down to V.sub.OFF to reduce the turn-off delay before the switching transient happens. After the turn-off delay ends, the buffer 2 will be pulled up and V.sub.dr is V.sub.adj2. Since V.sub.adj2>V.sub.OFF, the dv/dt and di/dt will be lower and the turn-off transient is slowed down. This is beneficial to the EMI immunity and reduction of voltage overshoot. After the I.sub.ds decreases to zero and the turn-off transient ends, the buffer 2 will be pulled up again and V.sub.dr is V.sub.OFF to provide negative clamping voltage for V.sub.gs. The process is shown in FIG. 9.

(48) The Optimization Algorithm

(49) The function of the optimization algorithm is to calculate the output voltage profile with the V.sub.BUS and I.sub.O feedback. The basic working flow chart is as shown in FIG. 3. The microcontroller receives the V.sub.BUS and I.sub.O feedback from the main controller of the converter. With the equation from [16], all the considerations that may affect the switching, such as dv/dt, di/dt, power losses, and total duration, can be quantified.

(50) The total loss function is as shown in Eq. (1).

(51) $\begin{array}{cc}{{{J=\alpha \frac{\mathrm{dv}}{dt}/\frac{dv}{dt}.Math.}_{\mathrm{Normal}}+\beta \frac{di}{dt}/\frac{di}{dt}.Math.}_{\mathrm{Normal}}+\gamma E_{\mathrm{loss}}/E_{\mathrm{loss}}.Math.}_{\mathrm{Normal}}& \left(1\right)\end{array}$

(52) In (1), slew rate dv/dt and di/dt and the total turn-off losses E.sub.loss can be calculated with [16]. dv/dt|.sub.Normal, di/dt|.sub.Normal, and E.sub.loss|Normal are the slew rate dv/dt and di/dt and the total turn-off losses under conventional switching conditions. w.sub.1, w.sub.2, and w.sub.3 are the weight coefficients of the several considerations. For different conditions, the selection of the weight coefficients are different. Weight coefficients are determined by the external factors such as parasitics and the thermal management. Generally, low PCB EMI immunity requires high w.sub.1, w.sub.2. Conversely, poor thermal management should have a higher w.sub.3.

(53) If the V.sub.BUS and I.sub.O are constant, for a specific power MOSFET, only V.sub.adj, i.e. V.sub.adj1 or V.sub.adj2, affects the output waveform. Therefore, the microcontroller will check with the lookup table for different value of V.sub.adj with dv/dt, di/dt, and E.sub.loss.

(54) The process has been explained in FIG. 4. The weight coefficients will be selected first. Then, the microcontroller will read the V.sub.BUS and I.sub.O feedback and calculate the parameters. After calculating the results of dv/dt, di/dt, E.sub.loss, total V.sub.adj duration t.sub.int, and the delay time t.sub.delay, the parameters will be substituted into Eq. (1) and the total cost will be calculated. Then, the optimal V.sub.adj will be selected. Based on the selected V.sub.adj, the microcontroller will send signals to control the AVR and the VS to generate the right V.sub.dr voltage profile.

Example of Operation

(55) The multi-level turn-off functionality, i.e., slow turn-off function, has been tested and verified to produce desired results. The test is a double pulse test (DPT). The device under test (DUT) is the CREE C2M0045170 SiC power MOSFET. The diode is the Cree C4D30120D. The inductor is an air core type. This methodology has been compared with the conventional method of replacing the gate resistor with a different value. The test circuit schematics are as shown in FIG. 10 and the experiment setup is as shown in FIG. 11 with FIG. 12 showing the DPT results. From FIG. 12, the active gate driver can adjust the Vadj2, from 3.5 V to 5.5 V. Through changing the intermediate voltage, the slew rate of V.sub.ds and I.sub.ds can be changed.

(56) Reference numerals and nomenclature used throughout the detailed description and the drawings correspond to the following elements: multi-level voltage gate driver 100 I.sub.ds Drain-source voltage of the power device I.sub.O Load current R.sub.g Gate resistance of the gate driver S.sub.a1-S.sub.an Control signals for the AVR S1-S3 Control signals for Buffer 1-3 respectively t.sub.int Intermediate voltage duration uC Microcontroller V.sub.adj The output voltage of the AVR. It includes V.sub.adj1 for turn-on and V.sub.adj2 for turn-off. V.sub.BUS Bus voltage of the converter V.sub.ctr Power supply voltage for the digital isolator of AVR V.sub.dr Output voltage of the gate driver V.sub.ds Drain-source voltage of power device V.sub.gs Gate-source voltage of power device V.sub.OFF Normal turn-off voltage of power device V.sub.ON Normal turn-off voltage of power device V.sub.th Threshold voltage of power device

(57) From the foregoing, it will be seen that this invention is well adapted to obtain all the ends and objects herein set forth, together with other advantages which are inherent to the structure. It will also be understood that certain features and subcombinations are of utility and may be employed without reference to other features and subcombinations. This is contemplated by and is within the scope of the claims. Many possible embodiments may be made of the invention without departing from the scope thereof. Therefore, it is to be understood that all matter herein set forth or shown in the accompanying drawings is to be interpreted as illustrative and not in a limiting sense.

(58) When interpreting the claims of this application, method claims may be recognized by the explicit use of the word ‘method’ in the preamble of the claims and the use of the ‘ing’ tense of the active word. Method claims should not be interpreted to have particular steps in a particular order unless the claim element specifically refers to a previous element, a previous action, or the result of a previous action. Apparatus claims may be recognized by the use of the word ‘apparatus’ in the preamble of the claim and should not be interpreted to have ‘means plus function language’ unless the word ‘means’ is specifically used in the claim element. The words ‘defining,’ ‘having,’ or ‘including’ should be interpreted as open ended claim language that allows additional elements or structures. Finally, where the claims recite “a” or “a first” element of the equivalent thereof, such claims should be understood to include incorporation of one or more such elements, neither requiring nor excluding two or more such elements.