Flip chip interconnection and circuit board thereof

Abstract

A flip chip interconnection including a circuit board is disclosed. The circuit board includes a substrate, inner leads, a T-shaped circuit line and a dummy pattern. The inner leads, the T-shaped circuit line and the dummy pattern are located on an inner bonding area of the substrate. The T-shaped circuit line includes a main segment, a branch segment and a connection segment that is connected to the main segment and the branch segment. The main segment and the branch segment are extended along a lateral direction and a longitudinal direction, respectively. The dummy pattern is located between the connection segment and the inner leads.

Claims

1. A circuit board, comprising: a substrate having a surface, an inner bonding area is defined on the surface and configured to be divided into a first area and a second area, the first area is located outside the second area; a plurality of inner leads located on the first area; at least one T-shaped circuit line located on the second area and including a main segment, a connection segment and a branch segment, the main segment is connected to the connection segment and extended along a lateral direction, the branch segment is connected to the connection segment and extended toward the first area along a longitudinal direction, wherein the branch segment is configured to be bonded with a bump; and at least one dummy pattern located between the connection segment and the plurality of inner leads and not electrically connected to the plurality of inner leads and the at least one T-shaped circuit line.

2. The circuit board in accordance with claim 1, wherein the main segment has a first width along the longitudinal direction and the connection segment has a second width along the longitudinal direction, the second width is less than the first width.

3. The circuit board in accordance with claim 2, wherein the branch segment has a third width along the lateral direction, and a quotient of the second and third widths is higher than or equal to 0.5.

4. The circuit board in accordance with claim 1, wherein the branch segment is extended toward one of the plurality of inner leads along the longitudinal direction.

5. The circuit board in accordance with claim 1, wherein the branch segment is extended to between two adjacent of the plurality inner leads along the longitudinal direction.

6. The circuit board in accordance with claim 1, wherein the branch segment includes a first end and a second end, the first end is connected to the connection segment, the second end is configured to be bonded with the bump, and the first end is wider than the second end.

7. The circuit board in accordance with claim 1, wherein the branch segment includes a first end and a second end, the first end is connected to the connection segment, the second end is configured to be bonded with the bump, and the first end is perpendicular to the second end.

8. The circuit board in accordance with claim 1 comprising two dummy patterns, wherein the dummy patterns are located at two sides of the branch segment respectively.

9. A flip chip interconnection, comprising: a circuit board including a substrate, a plurality of inner leads, at least one T-shaped circuit line and at least one dummy pattern, an inner bonding area is defined on a surface of the substrate and configured to be divided into a first area and a second area, the first area is located outside the second area, the plurality of inner leads are located on the first area, the at least one T-shaped circuit line is located on the second area and includes a main segment, a connection segment and a branch segment, the main segment is connected to the connection segment and extended along a lateral direction, the branch segment is connected to the connection segment and extended toward the first area along a longitudinal direction, the at least one dummy pattern is located between the connection segment and the plurality of inner leads and not electrically connected to the plurality of inner leads and the at least one T-shaped circuit line; a chip mounted on the inner bonding area and including a plurality of first bumps and at least one second bump; and a solder layer located between the circuit board and the chip and configured to bond the plurality of first bumps to the plurality of inner leads and bond the at least one second bump to the branch segment.

10. The flip chip interconnection in accordance with claim 9, wherein the main segment has a first width along the longitudinal direction and the connection segment has a second width along the longitudinal direction, the second width is less than the first width.

11. The flip chip interconnection in accordance with claim 10, wherein the branch segment has a third width along the lateral direction, and a quotient of the second and third widths is higher than or equal to 0.5.

12. The flip chip interconnection in accordance with claim 9, wherein the branch segment is extended toward one of the plurality of inner leads along the longitudinal direction.

13. The flip chip interconnection in accordance with claim 9, wherein the branch segment is extended to between two adjacent of the plurality inner leads along the longitudinal direction.

14. The flip chip interconnection in accordance with claim 9, wherein the branch segment includes a first end and a second end, the first end is connected to the connection segment, the second end is configured to be bonded with the at least one second bump, and the first end is wider than the second end.

15. The flip chip interconnection in accordance with claim 9, wherein the branch segment includes a first end and a second end, the first end is connected to the connection segment, the second end is configured to be bonded with the at least one second bump, and the first end is perpendicular to the second end.

16. The flip chip interconnection in accordance with claim 9, wherein the circuit board includes two dummy patterns that are located at two sides of the branch segment respectively.

17. The flip chip interconnection in accordance with claim 10, wherein the at least one second bump has a fourth width and a quotient of the second and fourth widths is less than 2.

18. The flip chip interconnection in accordance with claim 10, wherein the connection segment has a first length along the lateral direction and the at least one second bump has a second length, a quotient of the first and second lengths is higher than or equal to 4.

19. The flip chip interconnection in accordance with claim 10, wherein a linear distance is defined from the connection segment to the at least one second bump, and a quotient of the linear distance and the second width is higher than or equal to 3.

Description

DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a top view diagram illustrating a substrate in accordance with a preferred embodiment of the present invention.

(2) FIG. 2 is a top view diagram illustrating a flip chip interconnection in accordance with a preferred embodiment of the present invention.

(3) FIG. 3 is a top view diagram illustrating a part of an inner bonding area of a circuit board in accordance with a preferred embodiment of the present invention.

(4) FIG. 4 is a partial enlarged diagram of FIG. 3.

(5) FIG. 5 is a partial enlarged diagram of FIG. 3.

(6) FIG. 6 is a partial enlarged diagram of FIG. 3.

(7) FIG. 7 is a top view diagram illustrating a part of an inner bonding area of a circuit board in accordance with a preferred embodiment of the present invention.

(8) FIG. 8 is a top view diagram illustrating a part of an inner bonding area of a circuit board in accordance with a preferred embodiment of the present invention.

(9) FIG. 9 is a cross-section view diagram illustrating a flip chip interconnection in accordance with a preferred embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

(10) With reference to FIGS. 1 to 3, a circuit board 100 in accordance with a preferred embodiment of the present invention includes a substrate 110 and a circuit layer 120 that is located on a surface 111 of the substrate 110. An outer bonding area 112 and an inner bonding area 113 are defined on the surface 111. The circuit layer 120 includes outer leads 121 and inner leads 122 that are located on the outer bonding area 112 and the inner bonding area 113, respectively. In this preferred embodiment, the outer leads 121 and the inner leads 122 are arranged on the outer bonding area 112 and the inner bonding area 113, respectively, along a lateral direction X. The inner bonding area 113 is divided into a first area 113a and a second area 113b, and the first area 113a is located outside the second area 113b. Preferably, the inner bonding area 113 is divided into two first areas 113a and one second area 113b, the second area 113b is located between the two first areas 113a, and the inner leads 122 are arranged on the two first areas 113a.

(11) The substrate 110 may be made of polyimide (PI), polyethylene terephthalate (PET), glass, ceramic, metal or other material, and the circuit layer 120 may be made of copper (Cu), nickel (Ni), gold (Au) or other metal or alloy.

(12) With reference to FIG. 2, the circuit board 100 preferably further includes a solder resist layer 130 that covers the circuit layer 120, except the outer leads 121 and the inner leads 122. The solder resist layer 130 is provided to protect the circuit layer 120, and the exposed outer leads 121 and the exposed inner leads 122 are provided to bond to an electronic device and a chip, respectively.

(13) With reference to FIGS. 3 and 4, the circuit board 100 further includes at least one T-shaped circuit line 140 located on the second area 113b of the inner bonding area 113. The T-shaped circuit line 140 is designed for ground connection or power connection and is not electrically connected to the inner leads 122. The T-shaped circuit line 140 includes a main segment 141, a connection segment 142 and a branch segment 143, the main segment 141 is connected to the connection segment 142 and extended along the lateral direction X, and the branch segment 143 for bonding with a bump is connected to the connection segment 142 and extended toward the first area 113a along a longitudinal direction Y. In the preferred embodiment, the main segment 141 and the connection segment 142 connected with each other are linear, and the connection segment 142 and the branch segment 143 connected to one another are perpendicular. However, in different embodiment(s), the connection of the main segment 141 and the connection segment 142 may be nonlinear, and the included angle between the connection segment 142 and the branch segment 143 may be greater or less than 90 degrees, or equal to 90 degrees.

(14) Preferably, there are multiple T-shaped circuit lines 140 on the circuit board 100, the main segments 141 of the T-shaped circuit lines 140 are extended along the lateral direction X to connect with each other, and the branch segments 142 of the T-shaped circuit lines 140 are extended toward the first area 113a of the inner bonding area 113 along the longitudinal direction Y for bonding bumps.

(15) With reference to FIGS. 3 and 4, the circuit board 100 further includes at least one dummy pattern 150 that is located between the connection segment 142 and the inner leads 122 and not electrically connected to the T-shaped circuit line 140 and the inner leads 122. The profile of the dummy pattern 150 is adjustable according to the arrangement of the surrounding circuit lines without restrictions in the present invention. The dummy pattern 150 is provided to protect the T-shaped circuit line 140 from damage, particularly, protect the connection segment 142 and the branch segment 143 from breaking caused by over-etching. There may be two dummy patterns 150 of the same or different profiles located at two sides of the branch segment 143 symmetrically or asymmetrically.

(16) In the preferred embodiment, the circuit layer 120, the T-shaped circuit line 140 and the dummy pattern 150 are formed on the substrate 110 by the same etching process. The dummy pattern 150 is located in the space surrounded by the connection segment 142, the branch segment 143 and the inner leads 122 and able to prevent etching solution from accumulating around the connection segment 142 and the branch segment 143 so as to reduce possibility of damage of the connection segment 142 and the branch segment 143 caused by over-etching.

(17) FIGS. 4 to 8 represent the T-shaped circuit lines 140 of different possible patterns, respectively. The branch segment 143 shown in FIG. 5 is extended toward one of the inner leads 122 along the longitudinal direction Y, different to that shown in FIG. 4. The branch segment 143 shown in FIG. 6 is extended to between two adjacent inner leads 122 along the longitudinal direction Y and preferably has the same line width as the inner leads 122. With reference to FIG. 7, the branch segment 143 has a first end 143a and a second end 143b, the first end 143a is connected to the connection segment 142 and the second end 143b is provided for bonding a bump. Additionally, the first end 143a has a width greater than that of the second end 143b, thus the connection segment 142 and the branch segment 143 are protected from breaking, and the second end 143b is located between two adjacent inner leads 122. In another embodiment, as shown in FIG. 8, the branch segment 143 is nonlinear and the first end 143a is perpendicular to the second end 143b.

(18) With reference to FIGS. 2 and 9, a flip chip interconnection I in accordance with a preferred embodiment of the present invention includes the circuit board 100 as mentioned previously, a chip 200 and a solder layer 300. The chip 200 is mounted on the inner bonding area 113 of the substrate 110 and includes first bumps 210 and at least one second bump 220. The solder layer 300 is located between the circuit board 100 and the chip 200 for the bonding of the first bumps 210 with the inner leads 122 and for the bonding of the second bump 220 with the branch segment 143 of the T-shaped circuit line 140. The solder layer 300 has a thickness, preferably less than or equal to 0.30 μm, and more preferably less than or equal to 0.20 μm. In a preferred embodiment, the solder layer 300 is formed on the inner leads 122 and the T-shaped circuit line 140 and has a thickness of 0.16±0.40 μm. In the thermal bonding process, the chip 200 is placed on the inner bonding area 113 and then the solder layer 300 is heated to be softened for bonding the chip 200 to the circuit board 100.

(19) The heat-softened solder layer 300 has the flowability, for this reason, while the second bump 220 is bonded to the branch segment 143, the solder layer 300 on the T-shaped circuit line 140 flows toward the branch segment 143 from different directions with high possibility of overflow. The T-shaped circuit line 140 of the present invention can be modified in pattern to prevent solder overflow and solder short.

(20) With reference to FIG. 4, along the longitudinal direction Y, the main segment 141 has a first width W1 and the connection portion 142 has a second width W2 that is preferably less than the first width W1. Because of the width reduction of the connection segment 142, the amount of softened solder flowing from the connection segment 142 to the branch segment 143 can be reduced effectively. As a result, solder overflow induced by excess softened solder flowing toward the second bump 220 is significantly reduced.

(21) Furthermore, the branch segment 143 has a third width W3 along the lateral direction X, and the quotient of the second width W2 and the third width W3 is higher than or equal to 0.5

(22) $\left(\frac{W2}{W3}\ge 0.5\right).$
The quotient is between 0.5 and 1

(23) $\left(0.5\le \frac{W2}{W3}<1\right)$
when the second width W2 is less than the third width W3, the quotient is 1

(24) $\left(\frac{W2}{W3}=1\right)$
when the second width W2 is equal to the third width W3, and the quotient is higher than 1

(25) $\left(\frac{W2}{W3}>1\right)$
when the second width W2 is greater than the third width W3.

(26) In addition to change the width of the main segment 141, the connection segment 142 or the branch segment 143 with the restriction of width quotient, the width of the connection segment 142 can be determined according to the size of the second bump 220. As shown in FIG. 5, the second bump 220 has a fourth width W4 along the lateral direction X, and the quotient of the second width W2 and the fourth width W4 is preferably less than 2

(27) $\left(\frac{W2}{W4}<2\right).$
The quotient between 1 and 2

(28) $\left(1<\frac{W2}{W4}<2\right)$
indicates that the second width W2 is higher than the fourth width W4 and less than double of the fourth width W4, the quotient of 1

(29) $\left(\frac{W2}{W4}=1\right)$
indicates that the second width W2 and the fourth width W4 are the same, and the quotient less than 1

(30) $\left(0<\frac{W2}{W4}<1\right)$
indicates that the second width W2 is less than the fourth width W4.

(31) With reference to FIG. 6, a first length L1 of the connection segment 142 is defined along the lateral direction X and a second length L2 of the second bump 220 is defined along the longitudinal direction Y. Preferably, the connection segment 142 is not shorter than four times of the second bump 220, in other words, the quotient of the first length L1 and the second length L2 is higher than or equal to 4

(32) $\left(\frac{L1}{L2}\ge 4\right).$
The length of the width-reduced connection segment 142 can be determined based on the length of the second bump 220. In a preferred embodiment, the branch segment 143 is connected to the central part of the connection segment 142 and the shortest distance from the branch segment 143 to one of both ends of the connection segment 142 is equal to one another. However, the branch segment 143 of the present invention is not limited in position, it can be connected to any part of the connection segment 142 according to different layout requirements.

(33) With reference to FIG. 6, a linear distance LD between the connection segment 142 and the second bump 220 is the shortest distance from the connection segment 142 to the second bump 220, and the quotient of the linear distance LD and the second width W2

(34) 0$\left(\frac{LD}{W2}\right)$
is required to be proportional to the thickness of the solder layer 300. The linear distance LD has to be increased when the solder layer 300 is increased in thickness and the connection segment 142 is not decreased in width in order to lower the occurrence rate of solder short resulted from excess softened solder flowing to the branch segment 143. Preferably, while the solder layer 300 has a thickness of 0.16 μm, the linear distance LD has to be higher than or equal to three times of the second width W2, namely, the quotient of the linear distance LD and the second width W2 is not less than 3

(35) $\left(\frac{LD}{W2}\ge 3\right).$
And if the solder layer 300 has a thickness of 0.18 μm, the linear distance LD has to be higher than or equal to four times of the second width W2 so the quotient of the linear distance LD and the second width W2 is higher than or equal to 4

(36) $\left(\frac{LD}{W2}\ge 4\right).$

(37) In the embodiments shown in FIGS. 4 to 7, the second bump 220 has the fourth width W4 along the lateral direction X and has the second length L2 along the longitudinal direction Y, and the dummy patterns 150 located at two sides of the branch segment 143 have the same shape and mirror symmetrical to one another. In the embodiment as shown in FIG. 8, the second bump 220 has the fourth width W4 along the longitudinal direction Y and has the second length L2 along the lateral direction X, different to that in the embodiments of FIGS. 4 to 7, and the dummy patterns 150 located at two sides of the branch segment 143 have different shapes and asymmetrical.

(38) While this invention has been particularly illustrated and described in detail with respect to the preferred embodiments thereof, it will be clearly understood by those skilled in the art that is not limited to the specific features shown and described and various modified and changed in form and details may be made without departing from the scope of the claims.