All-MOSFET voltage reference circuit with stable bias current and reduced error

Abstract

An all-MOSFET voltage reference circuit includes a first cascaded branch configured to generate a bias current and composed of a first current source and a diode-connected first N-type transistor connected at a first interconnected node; a second cascaded branch composed of a second current source, a diode-connected second N-type transistor and a third N-type transistor connected with the second N-type transistor disposed in between, wherein the second N-type transistor and the third N-type transistor are connected at a second interconnected node; a third cascaded branch composed of a third current source and a diode-connected fourth N-type transistor connected at an output node that provides a reference voltage; and an amplifier with a non-inverting node coupled to the first interconnected node and an inverting node coupled to the second interconnected node. A threshold voltage of the third N-type transistor is larger than a threshold voltage of the second N-type transistor.

Claims

1. An all-MOSFET (metal-oxide-semiconductor field-effect transistor) voltage reference circuit, comprising: a first cascaded branch configured to generate a bias current and composed of a first current source and a diode-connected first N-type transistor connected in series at a first interconnected node between a power supply voltage and ground; a second cascaded branch composed of a second current source, a diode-connected second N-type transistor and a third N-type transistor connected in series with the second N-type transistor disposed in between, wherein the second N-type transistor and the third N-type transistor are connected at a second interconnected node, and gates of the second N-type transistor and the third N-type transistor are connected together; a third cascaded branch composed of a third current source and a diode-connected fourth N-type transistor connected in series at an output node that provides a reference voltage, the bias current being mirrored through the third current source; and an amplifier with a non-inverting node coupled to the first interconnected node and an inverting node coupled to the second interconnected node; wherein a threshold voltage of the third N-type transistor is larger than a threshold voltage of the second N-type transistors; wherein the first N-type transistor adopts a MOSFET with a standard-type threshold voltage, which is larger than a medium-type threshold voltage.

2. The circuit of claim 1, wherein the third N-type transistor includes a MOSFET adaptable to a higher power supply voltage than the power supply voltage of the voltage reference circuit.

3. The circuit of claim 2, wherein said higher power supply voltage is 3.3V, and the power supply voltage of the all-MOSFET voltage reference circuit is 1.8V.

4. The circuit of claim 2, wherein the second N-type transistor includes a MOSFET adaptable to the power supply voltage of the all-MOSFET voltage reference circuit.

5. The circuit of claim 1, wherein the first current source comprises a first P-type transistor, the second current source comprises a second P-type transistor, and the third current source comprises a third P-type transistor.

6. The circuit of claim 5, wherein a source of the first P-type transistor is connected to the power supply voltage, drains of the first P-type transistor and the first N-type transistor are connected together at the first interconnected node, and a source of the first N-type transistor is connected to the ground.

7. The circuit of claim 5, wherein a source of the second P-type transistor is connected to the power supply voltage, drains of the second P-type transistor and the second N-type transistor are connected together, a source of the second N-type transistor and a drain of the third N-type transistor are connected together, and a source of the third N-type transistor is connected to the ground.

8. The circuit of claim 5, wherein the third P-type transistor has a source connected to the power supply voltage and a drain connected to the output node; gates of the first P-type transistor, the second P-type transistor and the third P-type transistor are connected together; and the fourth N-type transistor has a drain connected to the output node, and a source connected to the ground.

9. The circuit of claim 5, wherein the amplifier has an output end coupled to gates of the first P-type transistor, the second P-type transistor and the third P-type transistor.

10. The circuit of claim 9, further comprising: an anti-noise capacitor connected between the output end of the amplifier and the power supply voltage.

11. The circuit of claim 1, further comprising: an active load that is coupled to receive the reference voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows a block diagram illustrating an all-MOSFET (metal-oxide-semiconductor field-effect transistor) voltage reference circuit according to one embodiment of the present invention;

(2) FIG. 2 shows a circuit diagram of the all-MOSFET voltage reference circuit of FIG. 1; and

(3) FIG. 3 shows a table listing exemplary medium-type threshold voltages and standard-type threshold voltages at some process corners with corresponding process variation percentage.

DETAILED DESCRIPTION OF THE INVENTION

(4) FIG. 1 shows a block diagram illustrating an all-MOSFET (metal-oxide-semiconductor field-effect transistor) voltage reference circuit 100 according to one embodiment of the present invention, and FIG. 2 shows a circuit diagram of the all-MOSFET voltage reference circuit 100 of FIG. 1.

(5) In the embodiment, the all-MOSFET voltage reference circuit (“voltage reference circuit” hereinafter) 100 may primarily include a current generator 11 that is configured to generate a bias current Ibias and a reference voltage Vref, and an active load 12 that is coupled to receive the reference voltage Vref.

(6) The current generator 11 of the embodiment may include a first cascaded branch composed of a first current source (such as a first P-type transistor MP1) and a diode-connected (i.e., with gate and drain connected) first N-type transistor MN1 connected in series at a first interconnected node B. The first current source is connected to a power supply voltage VDD (e.g., 1.8V (volts) in the embodiment) and the first N-type transistor MN1 is connected to ground. Specifically, a source of the first P-type transistor MP1 is connected to the power supply voltage VDD, drains of the first P-type transistor MP1 and the first N-type transistor MN1 are connected together at the first interconnected node B, and a source of the first N-type transistor MN1 is connected to the ground. As shown, the bias current Ibias may flow through the first cascaded stage, that is, the first P-type transistor MP1 and the first N-type transistor MN1.

(7) The current generator 11 of the embodiment may include a second cascaded branch composed of a second current source (such as a second P-type transistor MP2), a diode-connected second N-type transistor MN2 and a third N-type transistor MN3 connected in series between the power supply voltage VDD and the ground. The second N-type transistor MN2 disposed between the second current source and the third N-type transistor MN3. The second current source is connected to the power supply voltage VDD and the third N-type transistor MN3 is connected to the ground. The second N-type transistor MN2 and the third N-type transistor MN3 are connected at a second interconnected node A. Particularly, gates of the second N-type transistor MN2 and the third N-type transistor MN3 are connected together. Specifically, a source of the second P-type transistor MP2 is connected to the power supply voltage VDD, drains of the second P-type transistor MP2 and the second N-type transistor MN2 are connected together. A source of the second N-type transistor MN2 and a drain of the third N-type transistor MN3 are connected together, and a source of the third N-type transistor MN3 is connected to the ground.

(8) The current generator 11 of the embodiment may further include a third cascaded branch composed of a third current source (such as a third P-type transistor MP3) and a diode-connected fourth N-type transistor MN4 connected in series between the power supply voltage VDD and the ground. A source of the third P-type transistor MP3 is connected to the power supply voltage VDD, and drains of the third P-type transistor MP3 and the fourth N-type transistor MN4 are connected together at an output node that provides the reference voltage Vref. A source of the fourth N-type transistor MN4 is connected to the ground. Gates of the first P-type transistor MP1, the second P-type transistor MP2 and the third P-type transistor MP3 are connected together. The bias current Ibias is mirrored through the third P-type transistor MP3.

(9) The current generator 11 of the embodiment may include an amplifier 111 with a non-inverting node (+) coupled to the first interconnected node B and an inverting node (−) coupled to the second interconnected node A. Accordingly, the drains of the first N-type transistor MN1 and the third N-type transistor MN3 are forced to a substantially same potential. The amplifier 111 has an output end coupled to the gates of the first P-type transistor MP1, the second P-type transistor MP2 and the third P-type transistor MP3. Moreover, an anti-noise capacitor Cc may be connected between the output end of the amplifier 111 and the power supply voltage VDD. According to the current generator 11 as described above, the bias current Ibias may be mirrored through the third P-type transistor MP3 and may enter the active load 12 via the output node Vref. In the embodiment, the active load 12 may include a load capacitor CL connected between the output node Vref and the ground.

(10) Regarding Liu's voltage reference circuit as mentioned before, in order to ensure that the bias current Ibias flowing through the first N-type transistor (connected to the non-inverting node (+) of the amplifier) is large enough, Liu's first N-type transistor must use a MOSFET with a (smaller) medium-type threshold voltage. However, the MOSFET with a (smaller) medium-type threshold voltage has a large process variation percentage of up to 38%, thereby resulting in the bias current, for example, ranging from 90 nA to 0.8 nA and thus generating a reference voltage Vref with percentage error of up to 50%.

(11) To the contrary, according to one aspect of the embodiment, the first N-type transistor MN1 adopts a MOSFET with a (larger) standard-type threshold voltage, which has a process variation percentage substantially smaller than the MOSFET with the medium-type threshold voltage.

(12) FIG. 3 shows a table listing exemplary medium-type threshold voltages Vth and standard-type threshold voltages Vth at some process corners with corresponding process variation percentage.

(13) The first N-type transistor MN1 of the embodiment adopts the MOSFET with a (larger) standard-type threshold voltage instead of a (smaller) medium-type threshold voltage as in Liu. In order to maintain the bias current Ibias (to prevent it from becoming smaller) flowing through the first N-type transistor MN1, according to another aspect of the embodiment, the third N-type transistor MN3 of the embodiment includes a MOSFET adaptable to (or designed for) a higher power supply voltage than the power supply voltage VDD of the voltage reference circuit 100, while the second N-type transistor MN2 still includes a MOSFET adaptable to the power supply voltage VDD. In the embodiment, the power supply voltage VDD of the voltage reference circuit 100 is 1.8V, and the third N-type transistor MN3 includes a MOSFET adaptable to a next higher power supply voltage of 3.3V, for example, while the second N-type transistor MN2 still include MOSFETs adaptable to the power supply voltage VDD of 1.8V. Therefore, a threshold voltage of the third N-type transistor MN3 is larger than a threshold voltage of the second N-type transistor MN2, thereby pulling up the potential at the second interconnected node A.

(14) As the voltages at the (second/first) interconnected nodes A and B are forced to the substantially same potential (by the amplifier 111), the potential at the first interconnected node B may then be pulled up accordingly, and the bias current Ibias flowing through the first N-type transistor MN1 may therefore be increased.

(15) Regarding Liu's voltage reference circuit as mentioned above, the second N-type transistor and the third N-type transistor must use same MOSFETs with standard-type threshold voltage and adaptable to the power supply voltage VDD, otherwise Liu's required performance cannot be achieved.

(16) Compared to Liu's voltage reference circuit having a bias current ranging from 90 nA to 0.8 nA with percentage error of up to 50%, the voltage reference circuit 100 of the embodiment may generate a bias current Ibias ranging from 20 nA to 8.2 nA, therefore generating a reference voltage Vref with smaller percentage error of 6%.

(17) Although specific embodiments have been illustrated and described, it will be appreciated by those skilled in the art that various modifications may be made without departing from the scope of the present invention, which is intended to be limited solely by the appended claims.