High-frequency signal detector and method thereof
11323111 · 2022-05-03
Assignee
Inventors
Cpc classification
International classification
H03K5/153
ELECTRICITY
Abstract
A method of signal detection includes receiving an input voltage signal; using AC (alternate current) coupling to couple the input voltage signal into a coupled voltage signal; establishing a DC (direct current) value of the coupled voltage signal using a resistor; generating a self-mixed voltage signal by performing a self-mixing of the coupled voltage signal using a pair of cross-coupling MOS (metal oxide semiconductor) transistors; generating an output voltage by applying low-pass filtering on the self-mixed voltage signal; generating a reference voltage using a reference current terminated with a reference load; and determining a logical signal by comparing the output voltage with the reference voltage.
Claims
1. A signal detector comprising: a rectifier comprising a pair of AC (alternate current) coupling capacitors configured to couple an input voltage signal to a coupled voltage signal, a pair of resistors configured to establish a DC (direct current) value of the coupled voltage signal, a pair of cross-coupling MOS (metal oxide semiconductor) transistors configured to output a self-mixed voltage signal in accordance with a self-mixing of the coupled voltage signal, a low-pass filter network configured to filter the self-mixed voltage signal into an output voltage signal; a reference voltage generator comprising a current source configure to output a reference current and a reference load configured to establish a reference voltage in accordance with the reference current; and a comparator configured to output a logical signal in accordance with a comparison between the output voltage signal and the reference voltage, wherein said pair of resistors comprises a first resistor configured to couple the first end of the coupled voltage signal to a DC node and a second resistor configured to couple the second end of the coupled voltage signal to the DC node, wherein an end of the first resistor is directly connected to the DC node and an end of the second resistor is directly connected to the DC node.
2. The signal detector of claim 1, wherein said pair of AC coupling capacitors comprises a first capacitor configured to couple a first end of the input voltage signal to a first end of the coupled voltage signal and a second capacitor configured to couple a second end of the input voltage signal to a second end of the coupled voltage signal.
3. The signal detector of claim 1, wherein said pair of MOS transistors comprises a first MOS transistor and a second MOS transistor, the first end of the coupled voltage signal couples to a source of the first MOS transistor and a gate of the second MOS transistor, while the second end of the coupled voltage signal couples to a source of the second MOS transistor and a gate of the first MOS transistor.
4. The signal detector of claim 3, wherein the low-pass filter comprises a third capacitor configured to hold the output voltage signal at a center node, a third resistor configured to couple a drain of the first MOS transistor to the center node, and a fourth resistor configured to couple a drain of the second MOS transistor to the center node.
5. The signal detector of claim 4, wherein the current source comprises a third MOS transistor configured to output the reference current in accordance with a bias voltage.
6. The signal detector of claim 5, wherein the reference load comprises a series connection of a fifth resistor, a fourth MOS transistor, and a sixth resistor.
7. A method of signal detection comprising: receiving an input voltage signal; using AC (alternate current) coupling to couple the input voltage signal into a coupled voltage signal; establishing a DC (direct current) value of the coupled voltage signal using a resistor; generating a self-mixed voltage signal by performing a self-mixing of the coupled voltage signal using a pair of cross-coupling MOS (metal oxide semiconductor) transistors; generating an output voltage signal by applying low-pass filtering on the self-mixed voltage signal; generating a reference voltage using a reference current terminated with a reference load; and determining a logical signal by comparing the output voltage signal with the reference voltage, wherein establishing a DC (direct current) value of the coupled voltage signal using a resistor comprises: using a first resistor to couple the first end of the coupled voltage signal to a DC node and using a second resistor to couple the second end of the coupled voltage signal to the DC node, wherein an end of the first resistor is directly connected to the DC node and an end of the second resistor is directly connected to the DC node.
8. The method of signal detection of claim 7, wherein using AC (alternate current) coupling to couple the input voltage signal into a coupled voltage signal comprises using a first capacitor to couple a first end of the input voltage signal to a first end of the coupled voltage signal and using a second capacitor to couple a second end of the input voltage signal to a second end of the coupled voltage signal.
9. The method of signal detection of claim 7, wherein said pair of cross-coupling MOS transistors comprises a first MOS transistor and a second MOS transistor, the first end of the coupled voltage signal being coupled to a source of the first MOS transistor and a gate of the second MOS transistor, the second end of the coupled voltage signal being coupled to a source of the second MOS transistor and a gate of the first MOS transistor.
10. The method of signal detection of claim 9, wherein generating an output voltage signal by applying low-pass filtering on the self-mixed voltage signal comprises: using a third capacitor to hold the output voltage signal at a center node, coupling a drain of the first MOS transistor to the center node via a third resistor, and coupling a drain of the second MOS transistor to the center node via a fourth resistor.
11. The method of signal detection of claim 10, wherein the reference current is output from a current source comprising a third MOS transistor controlled by a bias voltage.
12. The method of signal detection of claim 11, wherein the reference load comprises a series connection of a fifth resistor, a fourth MOS transistor, and a sixth resistor.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1)
(2)
(3)
(4)
DETAILED DESCRIPTION OF THIS DISCLOSURE
(5) The present disclosure is directed to high-frequency signal detection. While the specification describes several example embodiments of the disclosure considered favorable modes of practicing the invention, it should be understood that the invention can be implemented in many ways and is not limited to the particular examples described below or to the particular manner in which any features of such examples are implemented. In other instances, well-known details are not shown or described to avoid obscuring aspects of the disclosure.
(6) Persons of ordinary skill in the art understand terms and basic concepts related to microelectronics that are used in this disclosure, such as “circuit node,” “power supply node,” “ground node,” “differential signal,” “voltage,” “current,” “MOS (metal oxide semiconductor)” “CMOS (complementary metal oxide semiconductor),” “PMOS (P-channel metal oxide semiconductor) transistor,” “NMOS (N-channel metal oxide semiconductor) transistor,” “square-law characteristic (pertaining to a PMOS transistor or a NMOS transistor),” “resistor,” “capacitor,” “signal,” “comparator,” “AC (alternate current),” “AC (alternate current) couple,” “DC (direct current),” “DC (direct current) couple,” “current source,” and “load.” Terms and basic concepts like these, when used in a context of microelectronics, are apparent to those of ordinary skill in the art and thus will not be explained in detail here.
(7) Those of ordinary skills in the art can read schematics of a circuit comprising components such as capacitors, resistors, NMOS transistors, PMOS transistors, and so on, and do not need a verbose description about how one component connects with another in the schematics. Those of ordinary skill in the art can also recognize symbols of PMOS transistor and NMOS transistor, and identify the “source terminal,” the “gate terminal,” and the “drain terminal” thereof. Pertaining to a MOS transistor, for brevity, hereafter, “source terminal” is simply referred to as “source,” “gate terminal” is simply referred to “gate,” and “drain terminal” is simply referred to “drain.” Those of ordinary skill in the art also understand units such as GHz (giga-Hertz), mV (mini-Volt), μA (micro-Ampere), μm (micron), nm (nanometer), Ohm (Ohm), and fF (femto-Farad).
(8) A MOS transistor, PMOS or NMOS, has a width and a channel length. Sometimes, “channel length” is simply stated as “length” for short when it is obvious from the context that the “length” refers to the “channel length” of the transistor without causing confusion. Width and length of a MOS transistor are referred by a notation “W/L.” For instance, when it is said that “W/L of a NMOS transistor are 10 μm/30 nm,” it means that “width and length of a NMOS transistor are 10 μm and 30 nm, respectively.”
(9) This disclosure is presented in an engineering sense, instead of a rigorous mathematical sense. For instance, “A is equal to B” means “a difference between A and B is smaller than an engineering tolerance. “X is zero” means “an absolute value of X is smaller than an engineering tolerance.”
(10) In this disclosure, a “circuit node” is frequently simply stated as a “node” for short, when what it means is clear from a context.
(11) Throughout this disclosure, a ground node is a node of substantially zero voltage (0V). A power supply node is a node of a substantially fixed voltage and is denoted by “V.sub.DD,” which is a convention widely used in the literature. In this disclosure, depending on a context that is apparent to those of ordinary skill in the art, sometimes “V.sub.DD” refers to the voltage level at the power supply node “V.sub.DD.” For instance, it is apparent that “V.sub.DD is 1.5V” mean that the voltage level at the power supply node V.sub.DD is 1.5V.
(12) A DC (direct current) node is a node of a substantially stationary voltage level. Both a power supply node and a ground node are a DC node.
(13) A circuit is a collection of a transistor, a capacitor, a resistor, and/or other electronic devices inter-connected in a certain manner to embody a certain function. A network is a circuit or a collection of circuits.
(14) In this present disclosure, a signal is a voltage of a variable level that carry a certain information and can vary with time. A level of the signal at a moment represents a state of the signal at that moment.
(15) A logical signal is a voltage signal of two states: a low state and a high state. The low state is also known as a “0” state, while the high stage is also known as a “1” state. Regarding a logical signal Q, “Q is high” or “Q is low,” means that “Q is in the high state” or “Q is in the low state.” Likewise, “Q is 1” or “Q is 0,” means that “Q is in the 1 state” or “Q is in the 0 state.”
(16) Throughout this disclosure, a differential signaling scheme is widely used. When embodied in a differential signaling scheme, a voltage signal comprises two voltages denoted with suffixes “+” and “−,” respectively, attached in subscript, and a value of the voltage signal is represented by a difference between said two voltages. For instance, a voltage signal V.sub.i (V.sub.c) in a differential signaling embodiment comprises V.sub.i+ (V.sub.c+) and V.sub.i− (V.sub.c−) and a value of the voltage signal V.sub.i (V.sub.c) is represented by a difference between V.sub.i+ (V.sub.c+) and V.sub.i− (V.sub.c−). V.sub.i+ (V.sub.c+) is said to be a first end of V.sub.i (V.sub.c); V.sub.i− (V.sub.c−) is said to be a second end of V.sub.i (V.sub.c). The first end is also referred to as a positive end; the second end is also referred to as a negative end. When a voltage signal is balanced in a differential signaling scheme, an AC value of its positive end is opposite to an AC value of its negative end.
(17) A schematic diagram of signal detector 100 in accordance with an embodiment of the present disclosure is shown in
(18) In an embodiment, signal detector 100 is integrated and fabricated on a silicon substrate using a CMO process technology. By way of example but not limitation, a 28 nm CMO process is used, wherein a minimum channel length is 30 nm.
(19) The rectifier 110 comprises: a first capacitors C.sub.1 and a second capacitor C.sub.2 configured to provide AC (alternate current) coupling between the input voltage signal V.sub.i and a coupled voltage signal V.sub.c, the input voltage signal V.sub.i comprising V.sub.i+ and V.sub.i− and the coupled voltage signal V.sub.c comprising V.sub.c+ and V.sub.c− at nodes 111 and 112, respectively, in a differential signaling scheme; a first resistor R.sub.1 and a second resistor R.sub.2 configured to connect nodes 111 and 112, respectively, to a ground node to establish a DC (direct current) value for V.sub.c+ and V.sub.c−, respectively; a pair of cross-coupling PMOS transistors M.sub.1 and M.sub.2 configured to output a first self-mixed voltage V.sub.sm1 at node 113 and a second self-mixed voltage V.sub.sm2 at node 114, wherein V.sub.c+ connects to the source of M.sub.1 and the gate of M.sub.2, V.sub.c− connects to the source of M.sub.2 and the gate of M.sub.1, and M.sub.1 and M.sub.2 are said to be cross-coupling since the gate of M.sub.1 connects to the source of M.sub.2 and the gate of M.sub.2 connects to the source of M.sub.1; a low-pass filter embodied by a T-network 119 comprising a center node 115 shunt with a third capacitor C.sub.3 to hold the output voltage signal V.sub.o, the center node 1115 being coupled to the third node 113 via a third resistor R.sub.3 and coupled to the fourth node 114 via a fourth resistor R.sub.4.
(20) In an embodiment, a MOS transistor embodies a mixer; when a gate of the MOS transistor connects to a first voltage signal and a source of the MOS transistor connects to a second voltage signal, a drain of the MOS transistor outputs a third voltage signal that contains a mixing product of the first voltage signal and a second voltage signal due to a square-law characteristic of a MOS transistor, wherein the third voltage signal is approximately proportional to a square of a difference between the first voltage signal and the second voltage signal. Therefore, PMOS transistor M.sub.1 embodies a mixing of V.sub.c− with V.sub.c+, while PMOS transistor M.sub.2 embodies a mixing of V.sub.c+ with V.sub.c−. Since V.sub.c+ and V.sub.c− are the same signal but with opposite signs in a differential signaling scheme, the mixing function that PMOS transistors M.sub.1 and M.sub.2 perform are said to be self-mixing.
(21) The T-network 119 performs a first low-pass filtering on the first self-mixed voltages V.sub.sm1 using the third resistor R.sub.3 and the third capacitor C.sub.3 and a second low-pass filtering on the second self-mixed voltages V.sub.sm2 using the fourth resistor R.sub.4 and the third capacitor C.sub.3 and consolidates outputs from the first low-pass filtering and the second low-pass filtering into the output voltage signal V.sub.o at the center node 115.
(22) By way of example but not limitation, in an embodiment: a frequency of V.sub.i is 8.5 GHz; C.sub.1 and C.sub.2 are 77 fF; R.sub.1 and R.sub.2 are 30K Ohm; W/L of PMOS transistors M.sub.1 and M.sub.2 are 600 nm/250 nm; R.sub.3 and R.sub.4 are 30K Ohm; and C.sub.3 are 50 fF. A simulation result of a value of V.sub.o versus an amplitude of V.sub.i is shown in
(23) The reference voltage generator 120 comprises: a current source embodied by a third PMOS transistor M.sub.3 configured to output a reference current I.sub.ref in accordance with a bias voltage V.sub.B and a reference load 130 configured to establish the reference voltage V.sub.ref in accordance with the reference current I.sub.ref. The reference load 130 comprises: a series connection of a fifth resistor R.sub.s, a fourth PMOS transistor M.sub.4, and a sixth resistor R.sub.6. The reference load 130 is to establish the reference voltage V.sub.ref in a way that mimics the rectifier 110. By way of example but not limitation: V.sub.DD is 1.5V; V.sub.B is 490 mV; W/L of PMOS transistor M.sub.3 is 5 μm/500 nm; I.sub.ref is 12.5 μA; V.sub.ref is 519 mV; R.sub.5 is 625 Ohm; W/L of PMOS transistor M.sub.4 is 70.4 μm/250 nm; and R.sub.6 is 40K Ohm.
(24) Comparators are well known in the prior art and thus not described in detail. Comparator 140 can be embodied using whatever comparator circuit known in the prior art in accordance with a discretion of a circuit designer.
(25) Given a network comprising a plurality of PMOS transistors and/or a plurality of NMOS transistors along with a plurality of passive elements (capacitors, resistors, or inductors), there exists an alternative network that is functionally equivalent to the given network, wherein the alternative network is modified from the given network by replacing every PMOS transistor with a NMOS transistor, replacing every NMOS transistor with a PMOS transistor, replacing every power supply node with a ground node, and replacing every ground with a power supply node. The alternative network is a “flipped” version of the given network and preserves the same function.
(26) Although it is shown that resistors R.sub.1 and R.sub.2 couple nodes 111 and 112, respectively, to a ground node, it is just an example but not limitation. R.sub.1 and R.sub.2 are used to establish a DC value of nodes 111 and 112, and the DC value doesn't necessarily need to be zero. The node that R.sub.1 and R.sub.2 jointly connect to can be a DC node that is not a ground node.
(27) As illustrate by a flow diagram 300 shown in
(28) Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the disclosure. Accordingly, the above disclosure should not be construed as limited only by the metes and bounds of the appended claims.