CURRENT LIMIT PROTECTION

Abstract

A current limiting circuit portion for limiting an output current of an electronic device includes an input voltage line for receiving an input voltage and a trimming circuit portion. The trimming circuit portion includes a resistive part providing a first resistance that is configurable based on one or more resistance control signals applied thereto, and a condition-tracking part connected in series with the resistive part that includes a condition-tracking transistor, the condition-tracking part providing a second resistance that is dependent on temperature and the input voltage.

Claims

1. A current limiting circuit portion for limiting an output current of an electronic device, the current limiting circuit portion comprising: an input voltage line for receiving an input voltage; and a trimming circuit portion comprising: a resistive part providing a first resistance that is configurable based on one or more resistance control signals applied thereto; and a condition-tracking part connected in series with the resistive part and comprising a condition-tracking transistor, the condition-tracking part providing a second resistance that is dependent on temperature and said input voltage.

2. The current limiting circuit portion as claimed in claim 1, further comprising a supply rail for receiving a supply voltage, wherein the second resistance provided by the condition-tracking part is further dependent on said supply voltage.

3. The current limiting circuit portion as claimed in claim 2, wherein a gate terminal of the condition-tracking transistor is coupled to a configurable voltage source, the configurable voltage source being configured to provide a voltage to a gate terminal of the condition-tracking transistor that causes the condition-tracking transistor to operate in the linear region.

4. The current limiting circuit portion as claimed in claim 3, wherein the configurable voltage source is configured to supply the gate terminal of the condition-tracking transistor with a voltage that is dependent on said supply voltage and said input voltage.

5. The current limiting circuit portion as claimed in claim 1, wherein the resistive part comprises a plurality of resistors and a selective bypass connection arranged to bypass at least one of the resistors in dependence on the one or more resistance control signals.

6. The current limiting circuit portion as claimed in claim 5, wherein the selective bypass connection comprises at least one bypass transistor, and wherein the one or more resistance control signals are fed to a gate terminal of the at least one bypass transistor.

7. The current limiting circuit portion as claimed in claim 1 further comprising a sensing circuit portion, the sensing circuit portion comprising: a main transistor; and a sensing device; wherein: the main transistor is arranged such that the output current flows therethrough; and the sensing device is coupled to the main transistor and configured such that a current that flows through the sensing device is dependent, at least in part, on the output current.

8. The current limiting circuit portion as claimed in claim 7, wherein: a gate terminal of the sensing device is connected to a gate terminal of the main transistor; an input terminal of the main transistor is coupled to the input voltage line; and an input terminal of the sensing device is coupled to the input voltage line.

9. The current limiting circuit portion as claimed in claim 7, wherein an output of the sensing circuit portion is coupled to an input of the trimming circuit portion such that any current that flows through the sensing device also flows through the trimming circuit portion.

10. The current limiting circuit portion as claimed in claim 7, wherein the sensing circuit portion further comprises a first differential amplifier, wherein: a first input of the first differential amplifier is coupled to an output terminal of the main transistor; a second input of the first differential amplifier is coupled to an output terminal of the sensing device; and an output of the first differential amplifier is coupled to a gate terminal of a sensing branch output transistor that is located in a same current path as the sensing device.

11. The current limiting circuit portion as claimed in claim 10, further comprising an adaptive biasing circuit portion coupled to the trimming circuit portion, the adaptive biasing circuit portion being configured to provide a first adaptive bias current to the first differential amplifier that is dependent, at least in part, on a voltage at a or the input of the trimming circuit portion.

12. The current limiting circuit portion as claimed in claim 7, wherein the sensing device comprises a plurality of sensing transistors connected in series, wherein a gate terminal of each sensing transistor is coupled to a gate terminal of each other sensing transistor.

13. The current limiting circuit portion as claimed in claim 12, wherein a gate terminal of the condition-tracking transistor is coupled to a or the configurable voltage source, the configurable voltage source comprising a configurable connection to one of a plurality of nodes within the sensing device.

14. The current limiting circuit portion as claimed in claim 7, wherein the circuit portion further comprises a feedback loop configured to counter-act increases in the output current that flows through the main transistor.

15. The current limiting circuit portion as claimed in claim 14, wherein the feedback loop comprises a second differential amplifier with a first input coupled to a substantially constant reference voltage and a second input coupled to a configurable node within the trimming circuit portion.

16. The current limiting circuit portion as claimed in claim 15, wherein an output of the second differential amplifier is configured to control, at least in part, a voltage at a gate terminal of the main transistor.

17. The current limiting circuit portion as claimed in claim 15, wherein: an output of the second differential amplifier is coupled to a gate terminal of a feedback transistor; an input terminal of the feedback transistor is coupled to the supply rail; and an output terminal of the feedback transistor is connected to the gate terminal of the main transistor and to a gate terminal of the sensing device.

18. The current limiting circuit portion as claimed in claim 15 further comprising an adaptive biasing circuit portion coupled to the trimming circuit portion, the adaptive biasing circuit portion being configured to provide a second adaptive bias current to the second differential amplifier that is dependent, at least in part, on a voltage at an input of the trimming circuit portion.

19. The current limiting circuit portion as claimed in claim 7, further comprising a soft-start circuit portion arranged to provide a first gate voltage to the main transistor that causes the main transistor to conduct a smaller current during a start-up phase and to provide a second gate voltage to the main transistor that causes the main transistor to conduct a larger current after said start-up phase is completed.

20. The current limiting circuit portion as claimed in claim 19, wherein the soft-start circuit portion comprises a first switch and a corresponding first control resistor having a first resistance, said first switch being closed during said start-up phase, and a second switch and a corresponding second control resistor having a lower resistance, said second switch being closed after said start-up phase.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0056] An embodiment of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0057] FIG. 1 is a circuit diagram of a circuit portion for limiting an output current in accordance with an embodiment of the present invention;

[0058] FIG. 2 is a more detailed circuit diagram of the trimming circuit portion, and sensing device of the circuit portion of FIG. 1.

DETAILED DESCRIPTION OF THE DRAWINGS

[0059] FIG. 1 shows a diagram of a circuit portion 101 for limiting an output current I.sub.OUT that flows through an output pin 102 such that it does not exceed a desired maximum value, according to an embodiment of the present invention. The circuit portion 101 comprises: a sensing circuit portion 104, a trimming circuit portion 106, a feedback circuit portion 108, an adaptive biasing circuit portion 110 and a soft-start circuit portion 120.

[0060] The sensing circuit portion 104 comprises a main transistor 140, a sensing device 160, a sensing branch output transistor 180, a first differential amplifier 200 and an electrostatic discharge protection (ESD) resistor 220. In this embodiment, the main transistor 140 and the sensing branch output transistor 180 each comprise P-channel metal-oxide-semiconductor field-effect (PMOS) transistors, and the first differential amplifier 200 comprises an operational transconductance amplifier (OTA). As will be explained in further detail later with reference to FIG. 2, in this embodiment the sensing device 160 comprises a plurality of PMOS transistors, connected in series, with coupled gate terminals. For the sake of simplicity, however, the sensing device 160 can be considered to function as a single PMOS transistor, and is represented as such in FIG. 1.

[0061] The source terminal of the main transistor 140 and the source terminal of the sensing device 160 are each coupled to an input voltage line 103, over which an input voltage V.sub.IN is received that is to be provided to the output pin 102. The input voltage V.sub.IN is subject to variation within a permitted operating range, which in this example is between 1.68 V and 1.92 V. The gate terminal of the main transistor 140 is coupled, via the ESD resistor 220, to the gate terminal of the sensing device 160. The drain terminal of the main transistor 140 is coupled to the positive input of the first differential amplifier 200, and to the output pin 102. The drain terminal of the sensing device 160 is coupled to the negative input of the first amplifier 200, and to the drain terminal of the sensing branch output transistor 180. The output of the first amplifier 200 is coupled to the gate terminal of the sensing branch output transistor 180. The first bias voltage input of the first amplifier 200 is coupled to the supply rail 300, over which a supply voltage V.sub.DD is received. The supply voltage V.sub.DD is subject to variation within a permitted operating range, which in this example is between 2.4 V and 5.5 V. The second voltage bias input of the first amplifier 200 is coupled to an offset trimming input 460 over which a configurable offset trimming voltage signal V.sub.TRIMOFF is received.

[0062] The trimming circuit portion 106 is described in further detail later with reference to FIG. 2. For the sake of simplicity, however, the trimming circuit portion 106 can be considered to function as a variable resistance from which a configurable trim voltage V.sub.TRIM can be tapped, and is represented as such in FIG. 1. The input terminal of the trimming circuit portion 106 is coupled to the source terminal of the sensing branch output transistor 180, and the output terminal of the trimming circuit portion 106 is coupled to ground.

[0063] The feedback circuit portion 108 comprises a second differential amplifier 240 and a feedback PMOS transistor 260. In this embodiment, the second differential amplifier 240 comprises an OTA. The configurable trim voltage V.sub.TRIM, tapped from the trimming circuit portion 106, is applied to the negative input of the second differential amplifier 240. The positive input of the second differential amplifier 240 is coupled to a reference voltage input line 280, over which a substantially constant reference voltage V.sub.REF is received. The output of the second differential amplifier 240 is coupled to the gate terminal of the feedback transistor 260. The first bias voltage input of the second amplifier 240 is coupled to the supply rail 300. The second bias voltage input of the second amplifier 240 is coupled to ground, though, for the sake of simplicity, this is not shown in FIG. 1. The source terminal of the feedback transistor 260 is coupled to the supply rail 300, and the drain terminal of the feedback transistor 260 is coupled to the gate terminal of the sensing device 160 and to the ESD resistor 220.

[0064] The adaptive biasing circuit portion 110 comprises a measurement NMOS transistor 320, a first biasing NMOS transistor 340, a second biasing PMOS transistor 360, a mirror PMOS transistor 380 and a grounding resistor 400.

[0065] The drain terminal of the measurement transistor 320 is coupled to ground, via the grounding resistor 400. The gate terminal of the measurement transistor 320 and the gate terminal of the first biasing transistor 340 are each coupled to the drain terminal of the sensing branch output transistor 180 and to the input terminal of the trimming circuit portion 106. The drain terminal of the first biasing transistor 340 is coupled to ground, and the source terminal of the first biasing transistor 340 is coupled to a first biasing node 420.

[0066] The source terminal of the second biasing transistor 360 and the source terminal of the mirror transistor 380 are each coupled to the supply rail 300. The gate terminal of the second biasing transistor 360 is coupled to the gate terminal of the mirror transistor 380. The drain terminal of the second biasing transistor 360 is coupled to a second biasing node 440. The drain terminal of the mirror transistor 380 is coupled to the source terminal of the measurement transistor 320. The mirror transistor 380 is diode-connected, and thus the gate terminal thereof is coupled to the drain terminal thereof.

[0067] The current bias input of the first differential amplifier 200 is coupled to the first biasing node 420 of the adaptive biasing circuit portion 110, and the current bias input of the second amplifier 240 is coupled to the second biasing node 440 of the adaptive biasing circuit portion 110. However, for the sake of simplicity, these connections between the differential amplifiers 200, 240 and the biasing nodes 420, 440 respectively are represented in FIG. 1 by variable current sources connected to ground. This arrangement results in the first differential amplifier 200 receiving a first adaptive bias current I.sub.ADAPN that is equal to the current flowing through the first biasing transistor 340, and the second differential amplifier 240 receiving a second adaptive bias current I.sub.ADAP that is equal to the current flowing through the second biasing transistor 360.

[0068] The soft-start circuit portion 120 comprises an enable switch 480, a soft-start switch 500, a first control resistor 520 and a second control resistor 540. The switches 480, 500 are each individually controlled by further circuitry that is not shown in FIG. 1, and may comprise any suitable type of switch including but not limited to physical switches, transistors, etc.

[0069] The output terminal of the enable switch 480 is coupled to ground, and the input terminal of the enable switch 480 is coupled, via the first control resistor 520, to the gate terminal of the sensing device 160 and the drain terminal of the feedback transistor 260.

[0070] Similarly, the output terminal of the soft-start switch 500 is coupled to ground, and the input terminal of the soft-start switch 500 is coupled, via the second control resistor 540, to the gate terminal of the sensing device 160 and the drain terminal of the feedback transistor 260.

[0071] For the purposes of the following description, the circuit portion 101 will be considered to be fully enabled and operating under steady-state conditions, which in this embodiment means that the enable switch 480 is closed, and the soft-start switch 500 is open. The operation of the switches 480 and 500 on start-up of the circuit portion 101 will be described in further detail later.

[0072] The input voltage V.sub.IN is received at the main transistor 140 and the sensing device 160, causing a current to flow respectively through each. The main transistor 140 and the sensing device 160 are designed such that the current flowing through the sensing device 160 is smaller than the current flowing through the main transistor 140. In this embodiment, the current flowing through the main transistor 140 is approximately one thousand times greater than the current flowing through the sensing device 160. The current that flows through the main transistor 140 also flows through the output pin 102, and is thus the output current I.sub.OUT.

[0073] The current that flows through the sensing device 160, hereinafter referred to as the sensing branch current I.sub.SENS, also flows through the sensing branch output transistor 180 and the trimming circuit portion 106 and is thus controlled in part by the output of the first amplifier 200, which is proportional to the difference between the voltages at its inputs and thus any mismatch between the output current and the sensing current (taking into account the designed scale factor mentioned above).

[0074] The sensing branch current I.sub.SENS creates a voltage drop across the trimming circuit portion 106. When the output current I.sub.OUT flowing through the main transistor 140 increases (e.g. due to a short circuit at the output pin 2), the sensing branch current I.sub.SENS flowing through the sensing device 160 also increases and so this voltage drop also increases. As a result, the configurable trim voltage V.sub.TRIM, which is tapped from a point along the trimming circuit portion 106, also increases.

[0075] The second differential amplifier 240 compares the configurable trim voltage V.sub.TRIM to the substantially constant reference voltage V.sub.REF, and outputs a current that is proportional to the difference between them. In this embodiment, the reference voltage V.sub.REF is approximately equal to 0.6 V. This current output by the second differential amplifier 240 creates a voltage at the gate terminal of the feedback transistor 260.

[0076] When the configurable trim voltage V.sub.TRIM increases (e.g. as a result of a short at the output pin 102), it approaches the reference voltage V.sub.REF. This causes the output current of the second differential amplifier 240 to decrease, thereby decreasing the gate voltage of the feedback transistor 260 thus causing the feedback transistor 260 to conduct more effectively. This increases the voltage at the gate terminals of the main transistor 140 and the sensing device 160, thereby causing the main transistor 140 and the sensing device 160 to conduct less effectively. This causes the currents I.sub.OUT, I.sub.SENS that flow through the main transistor 140 and the sensing device 160 respectively to decrease.

[0077] Thus, a negative feedback loop is formed: when the output current I.sub.OUT through the main transistor 140 increases, the feedback loop formed by the second differential amplifier 240 and the feedback transistor 260 causes the gate voltage of the main transistor 140 to increase, thus reducing the output current I.sub.OUT. This feedback loop causes the circuit portion 101 to limit the output current I.sub.OUT to a desired maximum value, thus providing short-circuit protection for the output pin 102.

[0078] Additionally, the arrangement of the first differential amplifier 200 and the sensing branch output transistor 180 effectively form another feedback loop in which the first amplifier 200 effectively tries to equalise the drain-to-source voltages of the main transistor 140 and the sensing device 160 (where the sensing device 160 is considered as a single effective transistor) by controlling the gate voltage of the sensing branch output transistor 180. This arrangement forces the current I.sub.SENS that flows through the sensing device 160 to be proportional to the output current I.sub.OUT, with the proportionality constant being dependent on the ratio between the size of the main transistor 140 and the size of the sensing device 160 - i.e. the size of the effective transistor that the sensing device 160 effectively operates as, which may be equal to the size of one of the plurality of transistors included in the sensing device 160, or to an average size of the plurality of transistors included in the sensing device 160. This advantageously forces the sensing branch current I.sub.SENS to closely track any variations that may occur in the output current I.sub.OUT.

[0079] The gains of the feedback loops formed by the differential amplifiers 200, 240 are controlled, in part, by the adaptive bias currents I.sub.ADAPN, I.sub.ADAP provided to the differential amplifiers 200, 240 respectively.

[0080] When the voltage at the input terminal of the trimming circuit portion 106 increases as a result of e.g. a short circuit at the output pin 102, as explained earlier, the respective gate voltages of the transistors 320, 340 increase, thereby causing the transistors 320, 340 to conduct more effectively thus increasing the respective currents flowing therethrough.

[0081] The increased current through the first biasing transistor 340 increases the first adaptive bias current I.sub.ADAPN provided to the first differential amplifier 200. The increased current through the measurement transistor 320 increases the current through the diode-connected mirror transistor 380, and thus the current through the second biasing transistor 360. This increases the second adaptive bias current I.sub.ADAP provided to the second differential amplifier 240.

[0082] Thus, the first and second adaptive bias currents I.sub.ADAPN, I.sub.ADAP are dependent on the voltage at the input of the trimming circuit portion 106, and thus dependent on the output current I.sub.OUT. The adaptive bias currents I.sub.ADAPN, I.sub.ADAP are configured to control the gains of the feedback loops formed by the differential amplifiers 200, 240 to be high enough to increase the speed of both loops’ response to changes in the output current I.sub.OUT, but low enough to provide increased stability to the respective feedback loops formed by the amplifiers 200, 240 across process, voltage and temperature (PVT) variations.

[0083] The enable switch 480 and the soft-start switch 500 are controlled by further control circuitry (not shown in FIG. 1) in order to enable/disable the circuit portion 101. When both switches 480, 500 are open, the circuit portion 101 is disabled. When at least one of the switches 480, 500 is closed, the circuit portion 101 is enabled, with the closed switches 480, 500 providing current paths from the gate terminals of the main transistor 140 and the sensing device 160 to ground via the respective control resistors 520, 540. This enables the feedback loop formed by the second differential amplifier 240 and the feedback transistor 260 to control the voltage at the gate terminal of the main transistor 140 in order to limit the output current I.sub.OUT to a desired value, or range of values dependent on operating conditions.

[0084] The provision of the two independently controlled switches 480, 500 and their respective control resistors 520, 540 enables the start-up of the circuit portion 101 to be controlled so as to prevent initial spikes in the output current I.sub.OUT that may occur as a result of transient effects of various components included in the circuit portion 101 on start-up. This is accomplished by providing a higher resistance path from the gate terminals of the main transistor 140 and the sensing device 160 to ground when the circuit portion 101 is initially enabled, and then providing a lower resistance path from said gate terminals to ground after a sufficient period of time for any transient effects to pass. Providing a higher resistance path to ground on start-up in this manner increases the voltage at the gate terminals of the main transistor 140 and the sensing device 160, thereby decreasing the maximum output current I.sub.OUT that is permitted by the circuit portion 101 and thus result in softer start-up behaviour of the circuit portion 101. This can also be explained by considering the parasitic capacitance at the gate terminal of the main transistor 140 and the resistance from the gate terminals of the main transistor 140 and the sensing device 160 to ground as a resistor-capacitor (RC) circuit. Increasing the resistance to ground increases the overall RC time constant of the RC circuit and therefore causes the gate voltages of the main transistor 140 and the sensing device 160 to settle to a steady-state condition a longer period of time after initial start-up. This limits the maximum output current I.sub.OUT that is permitted by the circuit portion 101 on start-up, resulting in softer start-up behaviour of the circuit portion 101.

[0085] In this embodiment, the first control resistor 520 has a smaller resistance than the second control resistor 540. Thus, when the circuit portion 101 is initially enabled, the soft-start switch 500 is initially closed while leaving the enable switch 480 open, providing a higher resistance path from the gate terminal of the main transistor 140 to ground. Then, after a sufficient period of time to enable any transient effects to pass, the enable switch 480 is closed and the soft-start switch 500 is opened, thus providing a lower resistance path from the gate terminal of the main transistor 140 to ground. The circuit portion 101 is then fully enabled and operating as normal. There may in some embodiments be an overlap where both switches 480, 500 are closed, before the soft-start switch 500 is opened.

[0086] In other embodiments, instead of opening the soft-start switch 500 after start-up is complete, the enable switch 480 is closed while leaving the soft-start switch 500 closed after start-up, thereby also providing a lower resistance path to ground. It will be appreciated that the start-up control of the switches 480, 500 may be modified in any suitable manner in dependence on the resistances of the control resistors 520, 540.

[0087] The trimming circuit portion 106 and the sensing device 160 will now be described in detail, with reference to FIG. 2. In this embodiment, the trimming circuit portion 106 comprises a first bypassable resistor 560, two non-bypassable resistors 580, 590, a variable resistor 600 and a condition-tracking NMOS transistor 620. The variable resistor 600 comprises a plurality of non-bypassable resistors 640 and a bypassable resistor 660. In this embodiment, resistive part of the trimming circuit portion 106 comprises the first bypassable resistor 560, the two non-bypassable resistors 580, 590 and the variable resistor 600, and the condition-tracking part of the trimming circuit portion 106 comprises the condition-tracking transistor 620. The resistors 560, 580, 590 may have any suitable resistance value: they may have equal resistances, or they may have different resistances, dependent on desired functionality of the trimming circuit portion 106.

[0088] In this embodiment, the resistors 560, 580, 590, 640, 660 are connected in series, as a chain, between the drain terminal of the sensing branch output transistor 180 and the source terminal of the condition-tracking transistor 620. The source terminal of the condition-tracking transistor 620 is connected to ground. It will be appreciated by those skilled in the art that the resistors 560, 580, 590, 640, 660 are not limited to being connected in series as shown in FIG. 2: in other embodiments, the resistors 560, 580, 590, 640, 660 may be connected in any suitable manner (e.g. in parallel) in order to provide a desired overall resistance for the resistive part of the trimming circuit portion 106.

[0089] The bypassable resistors 560, 660 are respectively connected, in parallel, to two bypass NMOS transistors 680, 700. The gate terminals of the bypass transistors 680, 700 are connected to a bypass control line 720, over which a bypass control signal CTRL is received from further circuitry that is not shown in the figures. In this embodiment, each of the bypass transistors 680, 700 respectively form selective bypass connections as referred to previously.

[0090] In this embodiment, the sensing device 160 comprises five sensing PMOS transistors 740, 760, 780, 800, 820 connected in series, with their gate terminals connected together. It will be appreciated that the sensing device 160 is not limited to five transistors as shown in this embodiment, but may comprise any suitable number of transistors, dependent on configuration. In this embodiment, the five sensing PMOS transistors 740, 760, 780, 800, 820 each comprise the same unit cell size transistor, though it will be appreciated that in other embodiments they may comprise different sized transistors. This arrangement causes the sensing device 160 to effectively operate as a single effective transistor with a size equal to that of one of the sensing PMOS transistors 740, 760, 780, 800, 820, or equal to the average size of the sensing PMOS transistors 740, 760, 780, 800, 820. The source terminal of the first sensing transistor 740 is coupled to the input voltage line 103 and the drain terminal of the fifth sensing transistor 820 is coupled to the source terminal of the sensing branch output transistor 180.

[0091] In FIG. 2, the gate terminal of the condition-tracking transistor 620 is shown to be coupled to the drain terminal of the third sensing transistor 780 and the source terminal of the fourth sensing transistor 800. This connection is configurable, using further circuitry that is not shown in the figures, such that the gate terminal of the condition-tracking transistor 620 may be connected to the drain terminal of any one of the first, second, third or fourth transistors 740, 760, 780, 800 (and, respectively, the source terminal of any one of the second, third, fourth or fifth transistors 760, 780, 800, 820). In other words, the gate terminal of the condition-tracking transistor 620 is connected to a configurable node within the sensing device 160.

[0092] The trimming circuit portion 106 provides two main benefits to the circuit portion 101: i) it enables the circuit portion 101 to be trimmed (i.e. configured after manufacture, but before deployment) so as to configure the maximum output current I.sub.OUT permitted by the circuit portion 101 to a desired value; and ii) it reduces variation in the maximum output current I.sub.OUT permitted by the circuit portion 101 that may occur as a result of variations in temperature, supply voltage V.sub.DD and input voltage V.sub.IN.

[0093] The operation of the trimming circuit portion 106 will now be described in detail. The overall resistance of the trimming circuit portion 106 in this embodiment is the sum of the resistances of the series-connected resistors 560, 580, 590, 640, 660 that have not been bypassed and the resistance of the condition-tracking transistor 620.

[0094] In this embodiment, the condition-tracking transistor 620 is provided with a configurable gate voltage that causes it to operate in the linear region. The condition-tracking transistor 620 can therefore be considered to function similarly to a conventional resistor, but with a resistance that is dependent on both the gate voltage fed thereto and temperature.

[0095] The voltages V.sub.D0, V.sub.D1, V.sub.D2, V.sub.D3 at each of the nodes within the sensing device 160 vary in dependence on the input voltage V.sub.IN, as the source terminal of the sensing transistor 740 is coupled to the input line 103. In other words, if the input voltage V.sub.IN decreases, the voltages V.sub.D0, V.sub.D1, V.sub.D2, V.sub.D3 at each of the nodes within the sensing device 160 decrease accordingly. Thus, the gate voltage of the condition-tracking transistor 620 is dependent, in part, on the input voltage V.sub.IN.

[0096] Furthermore, the voltages V.sub.D0, V.sub.D1, V.sub.D2, V.sub.D3 at each of the nodes within the sensing device 160 vary in dependence on the supply voltage V.sub.DD. This is because the gate terminals of the sensing transistors 740, 760, 780, 800, 820 are coupled to the feedback transistor 260, whose gate terminal is coupled to the output of the second amplifier 240. As the supply voltage V.sub.DD is provided to the second amplifier 240 as its bias voltage, the output of the second amplifier 240, and therefore the gate voltage of the feedback transistor 260, are dependent in part on the supply voltage V.sub.DD. Furthermore, as the source terminal of the feedback transistor 260 is coupled to the supply rail 300, the voltage at said source terminal is also dependent on the supply voltage V.sub.DD. Hence, the voltage at the drain terminal of the feedback transistor 260, and thus the gate voltages of the sensing transistors 740, 760, 780, 800, 820, are dependent in part on the supply voltage V.sub.DD. Thus, the resistances of the sensing transistors 740, 760, 780, 800, 820, and therefore the voltages V.sub.D0, V.sub.D1, V.sub.D2, V.sub.D3 at each of the nodes within the sensing device 160, are dependent in part on the supply voltage V.sub.DD.

[0097] It will therefore be seen that the gate voltage of the condition-tracking transistor 620 is dependent on both input voltage V.sub.IN and supply voltage V.sub.DD, and thus the resistance of the condition-tracking transistor 620 changes in dependence on supply voltage V.sub.DD and input voltage V.sub.IN, as well as temperature due to the inherent temperature dependency of transistors. However in the present embodiment whereby the input voltage is lower than the supply voltage, the dependence on input voltage will be larger than the dependence on supply voltage.

[0098] This condition-tracking resistance of the condition-tracking transistor 620 advantageously counter-acts variations in parameters of other components included in the circuit portion 101 that may occur as a result of varying supply voltage V.sub.DD, input voltage V.sub.IN and temperature. This advantageously reduces variation in the maximum output current I.sub.OUT permitted by the circuit portion 101 that occurs as a result of such variations.

[0099] Once the circuit portion 101 has been manufactured, various measurements may be taken at various nodes of the circuit portion 101 (particularly the output pin 102) in order to experimentally determine how that particular manufacture of the circuit portion 101 operates at typical operating conditions (V.sub.DD = 3.7 V, V.sub.IN = 1.8 V, Temperature = 27° C.). From these measurements, a trim code may be obtained which can be used to determine the configuration that should be used for the circuit portion 101 for optimal operation.

[0100] Once a trim code has been obtained, further control circuitry (not shown in the figures) is used to configure the trimming circuit portion 106 for optimal operation. A number of different elements of the trimming circuit portion 106 can be configured based on the trim code.

[0101] One element that can be configured based on the measured trim code is the overall resistance of the resistive part of the trimming circuit portion 106. This is configured by selectively shorting the bypassable resistors 560, 660 using the bypass control signal CTRL, transmitted over the bypass control line 720. This allows the adaptive bias currents I.sub.ADAPN, I.sub.ADAP provided by the adaptive bias circuit portion 110 to the first and second amplifiers 200, 240 respectively to be configured as desired, as these bias currents are dependent on the voltage at the input terminal of the trimming circuit portion 106, as explained earlier with reference to FIG. 1.

[0102] Another element that may be configured in dependence on the trim code is the point from which the trim voltage V.sub.TRIM is tapped within the trimming circuit portion 106. In this embodiment, the trim voltage V.sub.TRIM may be tapped from any point along the variable resistor 600 (i.e. at any node located between any two resistors 640, 660). This may be implemented in any appropriate manner, e.g. through physical switches, transistors, etc. This allows the maximum output current I.sub.OUT permitted by the circuit portion 101 to be configured to a particular value under normal operating conditions, or a particular range of values in dependence on operating conditions.

[0103] Another element that may be configured in dependence on the trim code is the voltage that is fed to the gate terminal of the condition-tracking transistor 620. In this embodiment, this is configured by configuring which drain terminal of the sensing transistors 760, 780, 800, 820 is connected to the gate terminal of the condition-tracking transistor 620, and thus which of the voltages V.sub.D0, V.sub.D1, V.sub.D2, V.sub.D3 is received by said gate terminal. This may be implemented in any appropriate manner, e.g. through physical switches, transistors, etc. This enables the condition-tracking transistor 620 to be configured for optimal operation - e.g. optimal tracking of variations in temperature, input voltage V.sub.IN and supply voltage V.sub.DD.

[0104] In the embodiment shown in FIG. 2, the gate terminal of the condition-tracking transistor 620 is coupled to a node within the sensing device 160. However, in other embodiments, the gate terminal of the condition-tracking transistor 620 may be coupled to any appropriate voltage or current source instead. For example, in some embodiments, the gate terminal of the condition-tracking transistor 620 is not coupled to any node within the sensing device 160 and is instead coupled to a temperature dependent current source (not shown in the figures) which is configured to provide a gate voltage to the condition-tracking transistor 620 that tracks variations in input voltage V.sub.IN and, to some extent, supply voltage V.sub.DD.

[0105] Turning back to FIG. 1, another element that may be configured in dependence on the trim code is the offset trimming voltage signal V.sub.TRIMOFF, which is received by the second voltage bias input of the first amplifier 200 via the offset trimming input 460. The offset trimming voltage signal V.sub.TRIMOFF may be controlled by further control circuitry that is not shown in the figures. By controlling the offset trimming voltage signal V.sub.TRIMOFF, the circuit portion 101 is able to adapt to manufacturing variations between the main transistor 140 and the sensing device 160 by biasing the first amplifier 200 more towards its positive input or towards its negative input.

[0106] It has been found through experimentation that by using the circuit portion 101, particularly the trimming circuit portion 106, in accordance with embodiments of the present invention, the variation in the maximum output current I.sub.OUT permitted by the circuit portion 101 that occurs as a result of variations in supply voltage V.sub.DD, input voltage V.sub.IN and temperature may be reduced when compared to e.g. the use of a simple chain of resistors, connected in series, in place of the trimming circuit portion 106.

[0107] An experiment was performed in which the performance of the circuit portion 101 using a simple chain of resistors in place of the trimming circuit portion 106 was compared to the performance of the circuit portion 101 using the trimming circuit portion 106 in accordance with the present invention, after trimming had been performed. In this experiment, the target limit on the output current I.sub.OUT was set to 50mA by trimming the circuit portion 101 appropriately, and measurements of the output current I.sub.OUT were taken at three defined corner conditions: typical (V.sub.DD = 3.7 V, V.sub.IN = 1.8 V, Temperature = 27° C.), fast (V.sub.DD = 2.4 V - 5.5 V, V.sub.IN = 1.68 V-1.92 V, Temperature = -40° C. - 125° C.) and slow (V.sub.DD = 2.4 V - 5.5 V, V.sub.IN = 1.68 V-1.92 V, Temperature = -40° C. - 125° C.).

[0108] It was found that, after trimming, using a simple chain of resistors in place of the trimming circuit portion 106 provided a minimum output current I.sub.OUT limit of 41.01 mA and a maximum of 75.67 mA across corners (translating to a deviation of -18.00% to +51.34% from the target, or 69.34% total variation). By contrast, using the trimming circuit portion 106 in accordance with an embodiment of the present invention, in combination with the remainder of the circuit portion 101, provided a minimum output current I.sub.OUT limit of 39.83 mA and a maximum of 60.84 mA across corners (translating to a deviation of -20.30% to +21.70% from the target, or 42.00% total variation).

[0109] Thus, it will be seen that the circuit portion 101 including the trimming circuit portion 106 in accordance with an embodiment of the present invention provides the distinct advantage of reducing variation in the output current I.sub.OUT limit due to variations in supply voltage V.sub.DD, input voltage V.sub.IN and temperature.

[0110] A number of transistors have been described herein with reference to FIG. 1. It will be understood by those skilled in the art that although these transistors have been described as being a particular type of transistor in this embodiment (e.g. PMOS, NMOS, etc.), they are not limited as such and may equally comprise any suitable type of transistor or any suitable number of transistors connected appropriately.

[0111] It will be appreciated by those skilled in the art that the invention has been illustrated by describing one or more specific embodiments thereof, but is not limited to these embodiments; many variations and modifications are possible within the scope of the appended claims.