AUTOMATED ATOMIC SCALE FABRICATION
20220130033 · 2022-04-28
Assignee
Inventors
Cpc classification
G01Q60/10
PHYSICS
B82B3/0019
PERFORMING OPERATIONS; TRANSPORTING
International classification
Abstract
A method for autonomously applying a dangling bond pattern to a substrate for atom scale device fabrication includes inputting the pattern, initiating a patterning process, scanning the substrate using a scanning probe microscope (SPM) to generate an SPM image of the substrate, feeding the SPM image into a trained convolution neural network (CNN), analyzing the SPM image using the CNN to identify substrate defects, determining a defect free substrate area for pattern application; and applying the pattern to the substrate in that area. An atom scale electronic component includes functional patches on a substrate and wires electrically connecting the functional patches. Training a CNN includes recording a Scanning Tunneling Microscope (STM) image of the substrate, extracting images of defects from the STM image, labeling pixel-wise the defect images, and feeding the extracted and labeled images of defects into a CNN to train the CNN for semantic segmentation.
Claims
1. A method for autonomously applying a dangling bond pattern to a substrate for atom scale device fabrication: inputting the pattern to be applied to the substrate; initiating a patterning process; scanning the substrate using a scanning probe microscope (SPM) to generate an SPM image of the substrate; feeding the SPM image into a trained convolution neural network (CNN); analyzing the SPM image using the CNN to identify defects on the substrate; determining a suitable defect free area on the substrate for application of the pattern; and applying the pattern to the substrate in the suitable defect free area.
2. The method of claim 1 wherein the substrate is hydrogen-terminated Si(100) surface.
3. The method of claim 1 wherein the SPM image has a resolution of 10 pixels/nm.
4. The method of claim 1 wherein identifying defects on the substrate includes characterizing defects on the substrate.
5. The method of claim 1 wherein identifying defects on the substrate includes locating defects on the substrate.
6. The method of claim 1 wherein analyzing the SPM image includes pixelating the image.
7. An atom scale electronic component comprising: a plurality of functional patches on a substrate, each of the plurality of functional patches containing a dangling bond pattern; and a plurality of wires electrically connecting the plurality of functional patches.
8. The electronic component of claim 7 wherein each of the plurality of functional patches is formed in a defect-free are of the substrate.
9. The electronic component of claim 7 wherein the plurality of functional patches are disconnected on the substrate.
10. The electronic component of claim 7 wherein the plurality of wires are routed to avoid defects between the plurality of functional patches.
11. A method for training a convolution neural network (CNN) to assess the quality of a surface of a substrate for atom scale device fabrication, said method comprising: recording a Scanning Tunneling Microscope (STM) image of the surface of the substrate; extracting a plurality of images of defects in the surface from the STM image; labeling pixel-wise each of the plurality of images of the defects; and feeding the extracted and labeled plurality of images of defects into a convolution neural network one image at a time to train the CNN for semantic segmentation.
12. The method of claim 11 wherein the STM image recorded is of a hydrogen-terminated Si(100) surface.
13. The method of claim 11 wherein the STM image is recorded at a sample bias of 1.3 V or 1.4 V.
14. The method of claim 11 wherein the STM image is recorded with a tunneling current of 50 μA.
15. The method of claim 11 wherein the STM image has a resolution of 10 pixels/nm.
16. The method of claim 11 wherein the CNN is trained to identify H—Si (100) surface defects.
17. The method of claim 11 wherein the CNN is trained to locate H—Si (100) surface defects.
18. The method of claim 11 wherein the SPM image recorded is 40×40 nm.sup.2.
19. The method of claim 11 wherein the SPM image recorded is 100×100 nm.sup.2.
20. The method of claim 11 wherein the convolution neural network includes five convolution encoder layers and five convolution decoder layers.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0017] The present invention is further detailed with respect to the following drawings that are intended to show certain aspects of the present invention but should not be construed as a limit on the practice of the present invention.
[0018]
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[0022]
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[0027]
DESCRIPTION OF THE INVENTION
[0028] The present invention has utility as a system and method for automated atomic scale fabrication capable of characterizing and locating defects on the H—Si(100)-2×1 surface to allow for a rapid and commercially feasible way to mass produce electronic components with atomic precession with limited human intervention. The present invention implements an encoder-decoder type convolutional neural network (CNN).sup.28,29,30 to locate and classify features on the substrate surface. By using semantic segmentation,.sup.31,32 the neural network is trained to recognize a variety of defects commonly found on the H—Si(100) surface. After implementing the model with existing patterning,.sup.13 and probe tip forming suites,.sup.23 full automation of the patterning process is achieved.
[0029] It is to be understood that in instances where a range of values are provided that the range is intended to encompass not only the end point values of the range but also intermediate values of the range as explicitly being included within the range and varying by the last significant figure of the range. By way of example, a recited range of from 1 to 4 is intended to include 1-2, 1-3, 2-4, 3-4, and 1-4.
[0030] Crystalline silicon is tetravalent and forms a diamond lattice; each silicon atom shares 4 bonds, two above and two below the atom. At the surface, two of these bonds are unsatisfied so the crystal reorganizes to a lower energy configuration. The addition of atomic hydrogen to the silicon surface during the annealing process results in the formation of one of three possible phases. The likelihood of forming these phases can be controlled by the annealing temperature at which the sample is prepared. The 2×1 phase forms at ˜377° C., the 3×1 phase forms at ˜127° C., and the 1×1 phase forms below ˜20° C..sup.33,14,34 The most regularly used for DB patterning is the 2×1 phase reconstruction where each surface atom pairs with a neighboring surface atom to create a dimer pair. The dimer pairs form in rows which run parallel to each other across the surface. Each silicon atom at the surface is left with a single unsatisfied bond which extends out into vacuum and can either be terminated with hydrogen or left vacant creating a dangling bond. Although the preparation of the H—Si(100)-2×1 phase is well understood, it is often difficult to create a perfectly clean, defect free surface. These defects as well as clean H—Si(100) can be imaged using a STM.
[0031] In order to train the CNN to recognize these surface defects, the defects are labeled pixel-wise in the STM images. The neural network is trained with seven different classes of labels. The first is regular, clean H—Si(100)-2×1, as shown in
[0032] After the training data is acquired and labeled, as described in the experimental methods below, it is used to develop and train the CNN for semantic segmentation. Semantic segmentation allows for both the localization and classification of objects in images. This can be used in many applications where the network must make a distinction between different objects in an image including use in self-driving cars.sup.41,42,43 and medical image analysis..sup.44,45,46 Here, a distinction is made between the pixels that make up each of the labelled defects. The various CNN architectures are trained. The CNN architecture that shows the greatest performance in recognizing the defects is implemented, as shown in
[0033] The network training data set is made from 28 images (100×100 nm.sup.2 and a resolution of 1028×1028). Each of the 28 images is divided into 64 smaller images (128×128). Each of the smaller images is rotated by 90°, 180°, and 270° as well as flipped along its axis and rotated again increasing the data set by a factor of 8 resulting in a total of 14336 images. The images are divided into training, testing, and validating images at a ratio of ˜2/3:1/6:1/6 respectively (corresponding to 9560:2384:2392 images). The Adam optimization algorithm.sup.47 is utilized with an exponentially decaying learning rate to achieve better convergence on a local minimum. The loss function used is a soft Dice loss function.sup.48. The soft Dice loss function is preferably used above other loss functions.sup.49,29 because it removes the need to weight different labels that appear less frequently. This solves any class imbalance which may otherwise be caused given that clean H—Si appears much more frequently than all other classes.
[0034] A subset of the outputs of the fully trained CNN is shown in
[0035] With the successful development of the neural network, specifically in locating charged defects, as well as clean H—Si, the CNN is implemented in the automation of DB patterning.
[0036] Accordingly, the present invention provides a routine that can assess the quality of a sample and executes a device manufacturing procedure in an area that is free of defects to fully develop atomically-precise fabrication tools. This routine relies on the use of a CNN which uses semantic segmentation to identify and locate certain defects that inhibit the manufacturing process. The neural network is trained with images of defects commonly found on the H—Si(100)-(2×1) surface. It is envisioned that defect-free regions, or patches, adequate for fabrication of functional logic units comprised of roughly one hundred atoms will exist and that interconnections between such units will be custom routed so as to avoid defects. According to embodiments, defect-free regions, or patches, are somewhat disconnected by unused and or defective areas. Small functional circuit units are made in the patches identified by the machine and have wires interconnecting the patches to make larger function circuits. The wire paths may be determined on the fly, with each wire routed to avoid microscopic defects between good patches. In this way, defect-free surface areas are connected to form larger, effectively defect-free circuit blocks. The techniques shown here have applications in device fabrication using any form of scanning probe microscopy as well as subsets of semiconductor device fabrication where the quality of the materials used must be assessed to optimize the fabrication process.
EXAMPLES
[0037] The following experiments are performed using an Omicron LT STM operating at 4.5 K and ultrahigh vacuum (4×10.sup.−11 Torr). Tips are electrochemically etched from polycrystalline tungsten wire and resistively heated in ultrahigh vacuum to remove surface adsorbates and oxide, and sharpened to a single atom tip using field ion microscopy.sup.46. In situ tip processing is performed by controlled tip contact with the surface.sup.6,47,48. Tip shaping parameters are the same as those detailed in incorporated Reference 29 below.sup.29.
[0038] Samples used are highly arsenic doped (1.5×10.sup.−19 atoms/cm.sup.3) Si(100). Samples are degassed at 600° C. overnight followed by flash annealing at 1250° C. The samples are then terminated with hydrogen by exposing them to atomic hydrogen gas at 330° C.
[0039] Image and data acquisition are done using a Nanonis SPM controller and software. All training data is acquired at an imaging bias of either 1.3 V or 1.4 V with a tunneling current of 50 μA. The patterning automation routine is programmed in Python and Labview using the Nanonis programming interface library.
[0040] The CNN is implemented using Keras (2.1.3) with TensorFlow backend. Data was labelled using LabelMe (1.0) software.
[0041] References and patent documents cited herein are incorporated by reference to the same extent as if each reference was individually and explicitly incorporated by reference.
[0042] As a person skilled in the art will recognize from the previous detailed description and from the figures and claims, modifications and changes can be made to the preferred embodiments of the invention without departing from the scope of this invention defined in the following claims.
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