DC-DC converter with flying capacitor pre-charging capabilities

Abstract

The voltage stress is limited across switches in multi-level flying capacitor step-down dc-dc converters during a start-up sequence by a circuit. In one embodiment, the circuit includes a diode that is adapted to prevent reverse current flow during steady state operation, a pull-down switch and a commutation cell, which includes a start-up capacitor and a flying capacitor.

Claims

1. A power converter comprising a circuit as part of the power converter, wherein the circuit comprises: a commutation cell, the commutation cell including a start-up capacitor and a flying capacitor connected in series; a diode, the diode being directly connected between the start-up capacitor and the flying capacitor, and the diode being adapted to prevent reverse current flow during steady state operation; a first inductor; a second inductor directly connected to the first inductor; a first switch connected to an input voltage source of the power converter, the flying capacitor being directly arranged between the first switch and the first inductor; a second switch comprising a second switch terminal directly connected to a node between the flying capacitor and the first inductor and another terminal directly connected to a ground; a third switch comprising a third switch terminal directly connected to a node between the first switch and the flying capacitor and another terminal directly connected to the second inductor; a fourth switch comprising a fourth switch terminal directly connected to a node between the third switch and the second inductor and another terminal directly connected to the ground; and a pull-down switch directly connected to a node between the start up capacitor and the diode and is configured to pull a potential of an anode of the diode to the ground after a start-up phase of the power converter, and maintain the diode in a reverse biased state of operation during a state of normal operation.

2. The power converter according to claim 1, wherein the power converter is a multi-level flying capacitor converter.

3. The power converter according to claim 1, wherein the power converter is a N-stage converter, wherein N is one of 3 and 4.

4. The power converter according to claim 1, wherein the start-up capacitor, the flying capacitor, and an output capacitor are connected in series during a power-up state.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a circuit diagram of a three-level flying capacitor buck converter during start-up, according to some embodiments. The inrush current path is shown in dashed lines. Initial voltage distribution showing full input voltage across S.sub.1.

(2) FIG. 2. is a circuit diagram of an example commutation cell for the input filter capacitive divider start-up method, according to some embodiments.

(3) FIG. 3. is a circuit diagram of an example commutation cell for the flying capacitor divider start-up method, according to some embodiments.

(4) FIG. 4. is a circuit diagram of an example three-level flying capacitor buck converter with input filter capacitive divider start-up method, according to some embodiments. The inrush current path is shown in dashed lines along with initial voltage distribution.

(5) FIG. 5. is a circuit diagram of an example simplified ideal circuit model for the 3L-FC buck on start-up, according to some embodiments.

(6) FIG. 6. is a waveform diagram of voltage and current waveforms corresponding to FIG. 5, according to some embodiments.

(7) FIG. 7. is a circuit diagram of an example 3L-FC buck with flying capacitor divider start-up method. The initial inrush current path and the inductor discharge path shown in dashed and dotted lines, according to some embodiments.

(8) FIGS. 8A, 8B, 8C, 8D, 8E, and 8F are non-limiting example extensions of start-up methods to different flying capacitor buck topologies. FIGS. 8A, 8C, and 8E show the split input capacitor divider start-up method with the 2-phase series-capacitor buck, 4L-FC buck, and the 3-phase series-capacitor buck, respectively. FIGS. 8B, 8D, and 8F show the flying capacitor divider start-up method with the 2-phase series-capacitor buck, 4L-FC buck, and the 3-phase series-capacitor buck, respectively.

(9) FIG. 9A is a waveform diagram of a fast input voltage ramp (˜400 ns) in the 3L-FC buck prototype showing the converter switch voltages on start-up in the absence of any start-up scheme, with the full input voltage seen across S.sub.1 (V.sub.ds1=V.sub.in).

(10) FIG. 9B is a waveform diagram of a fast input voltage ramp (˜400 ns) in the 3L-FC buck prototype using the input capacitor divider start-up method. All switch voltages are limited to ˜V.sub.in/2. The flying capacitor is also pre-charged to ˜V.sub.in/2.

(11) FIG. 9C is a waveform diagram of a fast input voltage ramp (˜1 μs) in the 3L-FC buck prototype showing the converter switch voltages on start-up in the absence of any start-up scheme, with the full input voltage seen across S.sub.1 (V.sub.ds1=V.sub.in).

(12) FIG. 9D is a waveform diagram of a fast input voltage ramp (˜1 μs) in the 3L-FC buck prototype using the flying capacitor divider start-up method. All switch voltages are limited to ˜V.sub.in/2. The flying capacitor is also pre-charged to ˜V.sub.in/2.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

(13) Two sets of methods are described in various embodiments for limiting the voltage stress across switches of multi-level flying capacitor (ML-FC) step-down DC-DC converters. For a general N-level converter, embodiments of the presented methods reduce the voltage stress to (N−1) times lower value than that of a conventional buck, allowing lower voltage rating transistors with smaller on-resistances to be used. These methods require no active control of switches on initial start-up, permitting use with systems where the gate driver and logic supply voltages are sourced from the converter input voltage or from an internal converter node. They rely on the segmentation of the input filter capacitor or the utilization of flying capacitors as parts of voltage dividers.

(14) The first set of methods also reduces the stress during input voltage transients. The commutation cells shown in FIG. 2 and FIG. 3 illustrate different methods. FIG. 2 is a commutation cell for an input capacitor divider start-up method, and FIG. 3 is a commutation cell for a flying capacitor divider start-up method.

(15) The speed of these approaches is limited only by the quality of the matching between high-frequency impedances of the components. The methods have been verified on a 3-level 24V to 5V, 20 W experimental prototype, where an input voltage rise time of 5 us and reduction of voltage stress of 2 times are demonstrated.

(16) FIG. 1 shows the in-rush current paths on start-up for a common flying capacitor topology, the three-level flying capacitor buck (3L-FC buck) converter. The current paths are shown in dashed lines at 102, 104, and 106.

(17) In addition to the current charging the input filter capacitor, there is a small current that flows through the drain-source capacitance of S.sub.1, C.sub.ds1, through the flying capacitor, the body diode of S.sub.3 and toward the relatively low impedance of the output filter. Upon initial ramp-up of the input voltage, C.sub.ds1 forms a capacitive divider with the flying and output capacitors, which due to the much larger impedance of C.sub.ds1 compared to C.sub.fly and C.sub.out results in nearly the entire input voltage being seen across S.sub.1. Furthermore, once switching action begins, the flying capacitor takes many cycles to charge, during which time other switches may be exposed to the full input voltage. In the case of the 3L-FC buck, S.sub.4 would also be exposed to the full input voltage upon initial switching.

(18) Various solutions have been proposed to address these issues. Some assume that the input voltage ramps up slowly enough that the flying capacitor can be pre-charged and the converter soft-started, which would still permit the use of half-rated switches.

(19) These solutions assume input voltage ramp times of 100s of microseconds to a few milliseconds and low input voltage slew rates. Others propose shorter input voltage ramp times and higher slew rates of 1V/μs, but expect that prior to start-up, logic and gate drive supplies are already on and stable. However, in the targeted low-power applications, these assumptions may not hold. Low power converters are usually exposed to much faster slew rates during input voltage ramp up due to the lower impedances of the reactive components at the converter input. To satisfy these criteria, some solutions propose adding a hot-swap circuit or some other series element in the conduction path at the converter input. One such approach involves adding two parallel fully rated switches at the converter input. One is a low impedance path that is enabled during normal operation, while the other path is a high impedance that serves to pre-charge the flying capacitor.

(20) Similar hot-swapping structures can also be seen in power delivery architectures for server applications. While hot-swap events can be handled safely, the additional series switch serves no function as part of normal operation and generally degrades the power processing efficiency and/or increases silicon area, while also increasing complexity.

(21) Instead of adding additional switches to the conduction pathway, one can also rate the main switch for the full input voltage. Pre-charging the flying capacitor can also be done in a more controlled manner through the action of two current sources placed in series with the flying capacitor. A feedback network forces the current sourced from the input voltage and the current discharged to ground to match.

(22) These solutions eliminate the need for having both S.sub.1 and S.sub.4 rated for the full input voltage, but still require the use of one high voltage rating transistor in the conduction path and thus do not provide the full utilization of the lower voltage rating advantages of multi-level topologies. It is suggested that half rated switches can still be used if the current sources are scaled up sufficiently thereby increasing the charge rate of the flying capacitor.

(23) However, generating these current sources and their supply voltages, particularly for higher input voltages, may be a significant challenge. These supplies would also have to be stable before the input voltage ramp and may burn non-negligible static power. Effectiveness is limited in the presence of relatively high start-up inrush currents caused by high input voltage slew rates.

(24) The previous discussion indicates that the ideal solution would be a start-up approach that: requires no additional series elements to be placed in the conduction path, can respond to an infinitely fast input voltage ramp (i.e. hot-swap), is entirely passive and requires no additional supply voltages on start-up, and uses switches rated for steady state operation (e.g. V.sub.in/2 plus some margin for the 3L-FC buck).

(25) A converter that generally meets these criteria was recently proposed, which is functionally identical to the 2-phase series-capacitor buck. The strategy involves moving the main switch, which is strictly in series with voltage source, down to the ground path and then adding an additional capacitor between the base of the flying capacitor and the base of the voltage source. The flying capacitor and additional capacitor are now in series and connected across the voltage source. Unfortunately, the lack of a common ground may make this solution unviable in a number of applications. Additionally, this strategy of moving the main switch to the ground side of the source only works for the one switch that is strictly in series with the source. Consequently, this strategy cannot be extended to higher level flying capacitor converters (e.g., 4L-FC buck or 3-phase series-capacitor buck).

(26) In the following subsections, start-up solutions that approach the ideal requirements and satisfy a majority of practical applications today are presented. Both of the approaches rely on the general principle of ML-FC converters, on the utilization of switching-capacitor network for obtaining voltage division.

A. Input Filter Capacitor/Commutation-Cell Based Solution

(27) This approach can be described through diagrams of FIG. 2, and FIG. 4. FIG. 2 shows the general commutation cell, where the voltage source V.sub.in is either the input voltage of the converter (for a 3-level converter, shown in FIG. 4) or the voltage between two neighboring taps of a capacitive divider for a general N-level case.

(28) For a 3 layer (3L)-FC buck, the single input capacitor of FIG. 1 is replaced with two stacked capacitors, with the center node connected to the terminals of the flying capacitor through two diodes. The cathode of the high current capacity inrush diode, D.sub.in, is connected to the top of the flying capacitor, while the anode of the small return diode, D.sub.ret, is connected to the base of the flying capacitor. FIG. 4 shows this method as implemented in the 3L-FC buck converter with the initial inrush current path at 402 and 404 and the subsequent inductor discharge path at 406 and 408. On start-up, the inrush current flows through the input filter capacitors and splits the input voltage between them setting the center node voltage to approximately V.sub.in/2. D.sub.in and D.sub.3 become forward biased and charge the flying capacitor. Once the flying capacitor voltage reaches V.sub.in/2 at its peak current, D.sub.in and D.sub.3 will become reverse biased, and D.sub.4 will begin to conduct until the inductor is fully discharged.

(29) The final estimation of the flying capacitor and output capacitor voltages is complicated by the multiple impedance paths. However, if C.sub.out>>C.sub.fly and C.sub.in1,2>>C.sub.fly the output capacitor voltage is not greatly changed by the charging of the flying capacitor, which will charge to approximately V.sub.in/2.

(30) Determining the final value of the flying capacitor and output capacitor voltages can be complicated by the multiple impedance paths and by the presence of the inductor. Due to the high initial inrush current, once the flying capacitor reaches its steady state voltage, the high instantaneous inductor current causes charge to continue to be forced to the output through the low side switch, S.sub.4. Damping along these paths is also very low as reduction in series resistance is key to reducing conduction losses. The resultant capacitor voltages depend on the values of the input, output and flying capacitors, the inductor, the characteristics of the diodes in the conducting pathway and the parasitic resistances and inductances in the paths. However, if C.sub.out>>C.sub.fly and C.sub.in1,2>>C.sub.fly, the output capacitor voltage is not greatly affected by the charging of the flying capacitor, which will charge to V.sub.in/2.

(31) With a few simplifications, one can derive expressions for the final values of the flying capacitor voltage, the output voltage, and the current through the inductor and diodes on start-up. To obtain a worst-case approximation of these values, the approach assumes ideal diodes and negligible parasitics in the conduction pathway, giving the simplified circuit model for the 3L-FC buck on start-up shown in FIG. 5. Inrush current path shown at 502, 504, 506, inductor discharge path at 508.

(32) Corresponding waveforms of the flying capacitor voltage, the output voltage and the charging currents on start-up are shown in FIG. 6.

(33) The equivalent capacitance of the flying and output capacitors is given by Eq. 1, where C.sub.eq is the equivalent capacitance, C.sub.out is the output capacitance, and C.sub.fly is the value of the flying capacitor. The resonant frequency of the output filter during portion 1 when D.sub.in and D.sub.3 conduct is given by Eq. 2, and the resonant frequency of the output filter during portion 2 when D.sub.4 conducts is given by Eq. 3, where ω.sub.o1 and ω.sub.o2 are the resonant frequencies during portions 1 and 2, respectively, and L is the value of the output inductor.

(34) $\begin{array}{cc}{C}_{\mathrm{eq}}=\frac{C_{\mathrm{fly}}{C}_{\mathrm{out}}}{C_{\mathrm{fly}}+C_{\mathrm{out}}}& \left(1\right)\\ {\omega }_{o_1}=\frac{1}{\sqrt{{\mathrm{LC}}_{\mathrm{eq}}}}& \left(2\right)\\ {\omega }_{o_2}=\frac{1}{\sqrt{{\mathrm{LC}}_{\mathrm{out}}}}& \left(3\right)\end{array}$

(35) For an input voltage step, the inductor will initially be seen as a high impedance and the centre tap voltage of the input capacitors, V.sub.tap, will initially be set by the voltage divider of C.sub.in1 and C.sub.in2. This voltage will determine the maximum inductor charging current and consequently, the maximum output voltage. The final value of V.sub.tap will be determined by a capacitive voltage divider of the input capacitors and the equivalent output capacitance, C.sub.eq, which will affect the point at which the inrush diode turns off and thus the final voltage of the flying capacitor.

(36) On start-up, the peak charging current, i.sub.peak, through the inductor, the inrush diode and the body diodes of S.sub.3 and S.sub.4 is given by Eq. 4, where V.sub.in is the input voltage, and C.sub.in1 and C.sub.in2 are the input capacitors. The maximum final output voltage, V.sub.out, f, is given by Eq. 5. The final value of the flying capacitor voltage, V.sub.Cfly, f, is given by Eq. 6.

(37) $\begin{array}{cc}{i}_{\mathrm{peak}}=V_{\mathrm{in}}\left(\frac{C_{\mathrm{in}1}}{C_{\mathrm{in}1}+C_{\mathrm{in}2}}\right)\sqrt{\frac{C_{\mathrm{eq}}}{L}}& \left(4\right)\\ v_{{\mathrm{out}}_f}=V_{\mathrm{in}}\left(\frac{C_{\mathrm{in}1}}{C_{\mathrm{in}1}+C_{\mathrm{in}2}}\right)\sqrt{\frac{C_{\mathrm{eq}}\left(C_{\mathrm{eq}}+C_{\mathrm{out}}\right)}{C_{\mathrm{out}}}}& \left(5\right)\\ v_{C_{{\mathrm{fly}}_f}}=V_{\mathrm{in}}\left(\frac{C_{\mathrm{in}1}}{C_{\mathrm{in}1}+C_{\mathrm{in}2}+C_{\mathrm{eq}}}\right)& \left(6\right)\end{array}$

(38) The flying capacitor voltage settles at t=t.sub.1. At t=t.sub.2, the inductor finishes discharging fully, with the output voltage reaching its maximum. The expressions for these times are given in Eqs. 7 and 8, where t.sub.1 and t.sub.2 are the end times of portions 1 and 2 respectively.

(39) $\begin{array}{cc}{t}_1=\frac{1}{{\omega }_{o_1}}\frac{\pi }{2}& \left(7\right)\\ t_2=\frac{1}{{\omega }_{o_2}}{\tan }^{-1}\left(\sqrt{\frac{C_{\mathrm{out}}}{C_{\mathrm{eq}}}}\right)+t_1& \left(8\right)\end{array}$

(40) During regular converter operation, the flying capacitor voltage must be actively balanced at V.sub.in/2 to limit the voltage stress across switches and maintain symmetrical current ripple, as well as overall stability of the system. Consequently, since the positive and negative terminals of the flying capacitor will range between V.sub.in/2 and V.sub.in, and 0V and V.sub.in/2 respectively, the inrush and return diodes, D.sub.in and D.sub.ret, keep V.sub.tap fixed at approximately V.sub.in/2. This allows the use of input capacitors rated for half the input voltage. Capacitor volume generally scales with the energy storage requirements of the capacitor. Though the single input capacitor is replaced by two capacitors each with double the capacitance of the original, the rated voltage is halved and thus the total stored energy is the same. As a result, theoretically, the total volume of the stacked input capacitors, C.sub.in1, and C.sub.in2 should be comparable to that of the single input capacitor.

(41) There is a potential limitation to the use of this input capacitor divider method. If the flying capacitor voltage is naturally lower than V.sub.in/2, as is the case of the series-capacitor buck operating in D.sup.2 mode for conversion ratios above 0.25, there will be current cycling through the diodes as the flying capacitor moves between the ground and input voltage rails during steady state. This cycling will reduce the efficiency of the system and disrupt its operation. In this case, the return diode can be omitted, only permitting unidirectional current flow.

(42) However, the stacked input capacitors will have to be rated for the full input voltage, increasing volume and negating some of the benefits of this solution. For converters operating with similar modulation schemes, the second start-up method may be more desirable as the start-up capacitor does not affect the steady state operation of the converter.

B. Flying Capacitor Divider Based Solution

(43) The second start-up method also features capacitive division using additional passive circuitry but utilizes the flying capacitor itself as a part of the divider. FIG. 3 shows the general commutation cell and FIG. 7 shows implementation for the 3-level buck with the initial inrush current highlighted at 702, 704, and 706 and inductor discharge paths highlighted at 708, and 710.

(44) A start-up capacitor, C.sub.div, of comparable size to the flying capacitor is connected between the input and the top of the flying capacitor forming a capacitor divider. A high current capacity inrush diode, D.sub.in, in that path charges the flying capacitor and prevents reverse current flow during steady state operation. A pull-down switch pulls the diode anode to ground sometime after start-up and keeps it reversed biased during normal operation. In this method, the start-up capacitor, flying capacitor, and output capacitor are all in series during power-up.

(45) During steady state operation, the start-up capacitor is connected in parallel with the input capacitor but contributes little to input filtering as the high R.sub.on of the small start-up switch makes the total impedance of the start-up capacitor plus switch much higher than that of the input capacitor at all frequencies.

(46) Since the start-up circuit does not interfere with steady state converter operation, this solution is better suited than the input capacitor divider solution to systems where modulation schemes may result in the flying capacitor voltage deviating from V.sub.in/2, such as the series-capacitor buck operating in D.sup.2 mode.

ILL. Implementation and Comparison of Methods

(47) These methods can be extended to other N-level flying capacitor buck converters and reduce the switch voltage stresses during start-up to (N−1) times lower value than that of a conventional buck. For both methods, extension to another 3-level topology, the 2-phase series-capacitor buck, is shown in FIG. 8A and FIG. 8B. Initial inrush current highlighted at 802, 804, 806, and inductor discharge paths highlighted at 808, and 809 for FIG. 8A. For FIG. 8B, initial inrush current highlighted at 810, 812, 818, and inductor discharge paths highlighted at 814, and 816.

(48) These methods can also be used for start-up in higher order ML-FC topologies such as the 4L-FC buck and the 3-phase series-capacitor buck. These 4-level topologies have two flying capacitors, operating with steady state voltages of 2.Math.V.sub.in/3 and V.sub.in/3. For the input capacitor divider method, adding a third stacked input capacitor provides two tap voltages, 2.Math.V.sub.in/3 and V.sub.in/3, from which two inrush diodes can be placed to charge the flying capacitors. There is some freedom in the placement of the return diodes, as long as the maximum voltage at the node connected to the return diode anode is exactly equal to the corresponding tap voltage. Implementations of this method with the 4L-FC buck and 3-phase series-capacitor buck are shown in FIG. 8C and FIG. 8E, respectively. Implementation of the flying capacitor divider method with 4-level topologies involves two additional capacitors, each one independently creating a divider with a single flying capacitor. Implementations of this method with the 4L-FC buck and 3-phase series-capacitor buck are shown in FIG. 8D and FIG. 8F, respectively.

IV. Experimental Results

(49) A discrete PCB prototype of the 3L-FC buck converter was made to test the functionality of the start-up methods. The prototype operates at 1 MHz switching frequency and is nominally rated for a conversion ratio of 24V-to-5V, 20 W output. The component values corresponding to FIGS. 4 and 7 are listed in Tables I and II. The methods were tested with fast input voltage rise times of under 1 μs. The results are detailed in FIG. 9A, FIG. 9B, FIG. 9C, and FIG. 9D.

(50) Both start-up methods guarantee that the voltage stress across each switch is limited to V.sub.in/2 during start-up, and pre-charge the flying capacitor. The peak current, final output voltage and final flying capacitor voltage differ slightly from the approximations primarily due to diode non-idealities. The small ripple in the switch voltages at approximately 8 μs following the input step for both start-up schemes indicates the point at which the body diode of S.sub.4 ceases conducting and turns off.

(51) TABLE-US-00001 TABLE I Experimental Prototype Design Specifications V.sub.in 24 V V.sub.out  5 V P.sub.out 20 W f.sub.sw   1 MHz

(52) TABLE-US-00002 TABLE II Component Parameters for FIG. 4 & FIG. 7 Input Capacitor Flying Capacitor Parameters Divider Divider L.sub.par 5 nH 5 nH R.sub.par 10 mΩ 80 mΩ C.sub.in — 5 μF C.sub.in1, C.sub.in2 10 μF — C.sub.fly 1 μF 1 μF C.sub.div — 1 μF L 1.2 μH 1.2 μH C.sub.out 50 μF 50 μF

V. Conclusions

(53) Embodiments described herein introduce two sets of methods for limiting the voltage stress across switches of multi-level flying capacitor (ML-FC) step-down dc-dc converters during start-up. These methods split the input voltage across multiple capacitors and consequently across multiple switches. For a general N-level converter, in applications where the input voltage is expected to rise in a few microseconds or longer, the presented methods ensure (in some cases, guaranteeing) the voltage stress to be (N−1) times lower value than that of a conventional buck during start-up, allowing lower voltage rating transistors with smaller on-resistances to be used. The passive nature of these methods allows their use in applications where the gate drive and logic supply voltages are sourced from the converter input or an internal node. Advantageously, the methods require a limited number of discrete components. The speeds of these methods are limited only by the quality of the matching between high-frequency impedances of the components and can theoretically be pushed to respond to input voltage ramps of fractions of a microsecond. The input capacitor divider method also reduces the stress during input voltage transients. Experimental results demonstrate the functionality of these start-up methods.

(54) The term “connected” or “coupled to” may include both direct coupling (in which two elements that are coupled to each other contact each other) and indirect coupling (in which at least one additional element is located between the two elements).

(55) Although the embodiments have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the scope. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification.

(56) As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

(57) As can be understood, the examples described above and illustrated are intended to be exemplary only.

(58) Any and all features of novelty or inventive step described, suggested, referred to, exemplified, or shown herein, including but not limited to processes, systems, devices, and computer-readable and -executable programming and/or other instruction sets suitable for use in implementing such features are claimed.