HETEROJUCTION BIPOLAR TRANSISTOR

Abstract

A heterojunction bipolar transistor, comprising: a substrate, having a first surface and an opposite second surface; a sub-emitter layer arranged on the first surface; a compound emitter layer arranged on the sub-emitter layer, making the sub-emitter layer and the compound emitter layer forms an emitter layer; a base layer arranged on the compound emitter layer; a collector ledge layer arranged on the base layer; a collector layer arranged on the collector ledge layer; a lateral oxidation region arranged on the compound emitter layer forming a current blocking region, and the outer region of the compound emitter layer surrounds inner region, so that the inner region of the compound emitter layer forms a current aperture.

Claims

1. A heterojunction bipolar transistor, comprising: a substrate having a first surface and a second surface on the opposite side; a sub-emitter layer located on the first surface of the substrate; a compound emitter layer located on the sub-emitter layer for making the sub-emitter layer and compound emitter layer form an emitter layer, the emitter layer being formed by a first emitter layer and a second emitter layer, and the second emitter layer being arranged on the first emitter layer, the first emitter layer including a first emitter transition layer, an intermediate layer, and a second emitter transition layer, and the first emitter transition layer is made of N.sup.−GaAs, the second emitter transition layer is made of N.sup.−GaAs and a material of the intermediate layer being high Aluminum content Al.sub.xGa.sub.1-xAs, and a lateral oxidation region being provided in the intermediate layer, and the lateral oxidation region is N.sup.−AlGaAs, the high Aluminum content Al.sub.xGa.sub.1-xAs has an Aluminum content x ranging from 0.80 to 0.98; a base layer located on the compound emitter layer; a collector ledge layer located on the base layer; a collector layer located on the collector ledge layer; a lateral oxidation region provided in a portion of the compound emitter layer forming a current blocking region, and the outer region of the compound emitter layer surrounds inner region of the compound emitter layer, so that the inner region of the compound emitter layer forms a current aperture.

2.-3. (canceled)

4. The heterojunction bipolar transistor as claimed in claim 1, wherein a first optional layer is provided between the first emitter transition layer and the intermediate layer, a second optional layer is provided between the second emitter transition layer and the intermediate layer, and the first optional layer and the second optional layer are made of N.sup.−AlGaAs.

5. The heterojunction bipolar transistor as claimed in claim 1, wherein the thickness of the first emitter transition layer is 20-100 nm, and the doping material is Si and the Si doping concentration is reduced from 4e18 to 3e17 cm.sup.−3; the thickness of the lateral oxidation region is 0.4-2.5 nm, and the doping material is Si and the Si doping concentration is 0-6e18 cm.sup.−3; the thickness of the second emitter transition layer is 20-100 nm, and the doping material is Si and the Si doping concentration is 5e16-5e17 cm.sup.−3.

6. The heterojunction bipolar transistor as claimed in claim 1, wherein the thickness of the first emitter transition layer is 50 nm, and the doping material is Si and the Si doping concentration is reduced from 4e18 to 3e17 cm.sup.−3; the thickness of the lateral oxidation region is him, and the doping material is Si and the Si doping concentration is 4e18 cm.sup.−3; the thickness of the second emitter transition layer is 50 nm, and the doping material is Si and the Si doping concentration is 3e17 cm.sup.−3.

7. The heterojunction bipolar transistor as claimed in claim 1, wherein the collector ledge layer is ordered N.sup.−InGaP and the energy band gap is approximately 1.85 eV.

8. The heterojunction bipolar transistor as claimed in claim 1, further include a base metal arranged on the collector ledge layer, and the base metal diffuses downward from the collector ledge layer into the base layer.

9. The heterojunction bipolar transistor as claimed in claim 1, further include a base metal arranged on the collector ledge layer, a etch through the collector ledge into the base layer is performed, and a base metal is deposited inside the etched region to connect to the base layer.

10. The heterojunction bipolar transistor as claimed in claim 1, wherein the material of the base layer is P.sup.+GaAs, P.sup.+InGaAs, or a combination thereof.

11. The heterojunction bipolar transistor as claimed in claim 1, further includes a collector cap layer arranged on the collector layer.

12. The heterojunction bipolar transistor as claimed in claim 11, wherein the material of the substrate is semi-insulating GaAs; the material of the sub-emitter layer is N.sup.+GaAs; the material of the second emitter layer is N.sup.−InGaP; the material of the base layer is of P.sup.+GaAs; the material of the collector ledge layer is N.sup.−InGaP; the material of the collector layer is N.sup.−GaAs; the material of the collector cap layer is N.sup.+GaAs or N.sup.+InGaAs.

13. The heterojunction bipolar transistor as claimed in claim 12, wherein the thickness of the sub-emitter layer is 500-1000 nm, and the doping material is Si and the Si doping concentration is 1e18-2e19 cm.sup.−3; the thickness of the second emitter layer is 30-60 nm, and the doping material is Si and the Si doping concentration is 5e16-5e17 cm.sup.−3; the thickness of the base layer is 40-120 nm, and the doping material is C and the C doping concentration is 1e19-1e20 cm.sup.−3; the thickness of the collector ledge layer is 0.4-100 nm, and the doping material is Si and the Si doping concentration is 5e16-5e17 cm.sup.−3; the collector layer is composed of a first collector layer and a second collector layer, and the thickness of the first collector layer is 300-1200 nm, and the doping material is Si and the Si doping concentration is 1e17˜2e14 cm.sup.−3, the thickness of the second collector layer is 0-800 nm, and the doping material is Si and the Si doping concentration is 1e16-1e17 cm.sup.−3; a collector transition layer, the collector transition layer extends the second collector layer, the thickness of the collector transition layer is 20-100 nm, and the doping material is Si and the Si doping concentration is larger than 1e19 cm.sup.−3, the collector cap layer further extends the collector transition layer, the thickness of the collector cap layer is 20-100 nm, and the doping material is Si and the Si doping concentration is larger than 1e19 cm.sup.−3.

14. The heterojunction bipolar transistor as claimed in claim 12, wherein the thickness of the sub-emitter layer is 800 nm, and the doping material is Si and the Si doping concentration is 4e18 cm.sup.−3; the thickness of the second emitter layer is 50 nm, and the doping material is Si and the Si doping concentration is 3e17 cm.sup.−3; the thickness of the base layer is 80 nm, and the doping material is C and the C doping concentration is 3e19 cm.sup.−3; the thickness of the collector ledge layer is 5 nm, and the doping material is Si and the Si doping concentration is 3e17 cm.sup.−3; the collector layer is composed of a first collector layer and a second collector layer, and the thickness of the first collector layer is 900 nm, and the doping material is Si and the Si doping concentration is 2e15 cm.sup.−3, the thickness of the second collector layer is 300 nm, and the doping material is Si and the Si doping concentration is 5e16 cm.sup.−3; a collector transition layer, the collector transition layer extends the second collector layer, the thickness of the collector transition layer is 50 nm, and the doping material is Si and the Si doping concentration is larger than 1e19 cm.sup.−3, the collector cap layer further extends the collector transition layer, the thickness of the collector cap layer is 50 nm, and the doping material is Si and the Si doping concentration is larger than 1e19 cm.sup.−3.

15. The heterojunction bipolar transistor as claimed in claim 12, wherein at the junction of the base layer and the second emitter layer, the N.sup.−InGaP of the second emitter layer is either ordered or disordered.

16. The heterojunction bipolar transistor as claimed in claim 1, further has an isolation implant region arranged into the sub-emitter layer and into the substrate.

17. The heterojunction bipolar transistor as claimed in claim 16, wherein the isolation implant region is composed of Boron, Argon, Hydrogen, Helium, Aluminum, or a combination thereof.

18. The heterojunction bipolar transistor as claimed in claim 11, wherein the collector layer and the collector cap layer form a first mesa; the collector ledge layer, the base layer and the compound emitter layer form a second mesa, and the first mesa is smaller than the second mesa; an emitter metal located on the sub-emitter layer; a base metal located on the collector ledge and the base metal diffuses downward from the collector ledge layer into the base layer; and a collector metal located on the collector cap layer; whereby the electron current emitted from the emitter metal to the collector metal, and the current blocking region blocks the current, which only allows the current flow through the current aperture.

19. The heterojunction bipolar transistor as claimed in claim 18, wherein further has a back-side metal arranged on the second surface of the substrate, and the substrate and the sub-emitter layer have a back-side via hole for making the back-side metal electrically connect to the emitter metal by the back-side via hole.

20. The heterojunction bipolar transistor as claimed in claim 18, wherein an under bump metal is directly connected to the collector metal whereby the heat flow emitted from the heterojunction bipolar transistor can be conducted through the under bump metal into a bump.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0031] FIG. 1 is a schematic diagram illustrating structure of the present invention with a first SiN insulation layer protecting the surface of the semiconductor;

[0032] FIG. 2 is a schematic diagram illustrating the etching of the first mesa of the present invention;

[0033] FIG. 3 is a schematic diagram illustrating the etching of the second mesa of the present invention;

[0034] FIG. 4 is a schematic diagram illustrating the forming of the lateral oxidation region of the present invention;

[0035] FIG. 5 is a schematic diagram illustrating the forming of the second SiN insulation layer and the etching of the first via hole of the present invention;

[0036] FIG. 6 is a schematic diagram illustrating the forming of the emitter metal of the present invention;

[0037] FIG. 7 is a schematic diagram illustrating the forming of the isolation implant region of the present invention;

[0038] FIG. 8 is a schematic diagram illustrating the forming of the base metal of the present invention;

[0039] FIG. 9 is a schematic diagram illustrating the forming of the collector metal of the present invention and illustrating the finished heterojunction bipolar transistor;

[0040] FIG. 10 is a schematic diagram illustrating the electron current flowing from the emitter metal to the collector metal of the present invention;

[0041] FIG. 11A is a schematic diagram illustrating the structure from the first emitter transition layer to the second emitter transition layer of the present invention;

[0042] FIG. 11B is a schematic diagram illustrating the structure from the first collector layer to the collector cap layer of the present invention;

[0043] FIG. 12 is a schematic diagram illustrating the back-side metal and the back-side via hole of the present invention;

[0044] FIG. 13 is a schematic diagram illustrating an additional dielectric passivation layer that is coated on the heterojunction bipolar transistor of the present invention;

[0045] FIG. 14 is a schematic diagram illustrating an additional under bump metal and flip-chip bump, solder bump or thermal bump wherein the heat flow emitted from the heterojunction bipolar transistor being conducted through the under bump metal into the flip-chip bump, solder bump or thermal bump.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0046] Referring to FIGS. 1-14, the present invention is a heterojunction bipolar transistor 10, comprising: a substrate 11 having a first surface 111 and a second surface 112 on the opposite side; in this embodiment, the material of the substrate 11 is semi-insulating GaAs, and the thickness of the substrate 11 is as referenced from the standard of the Semiconductor Equipment and Materials international, SEMI, and the unit is micron.

[0047] A sub-emitter layer 12 is located on the first surface 111 of the substrate 11, in this embodiment, the material of the sub-emitter layer 12 is N.sup.+GaAs, and the thickness of the sub-emitter layer 12 is 500-1000 nm, and the doping material is Si and the Si doping concentration is 1e18-2e19 cm.sup.−3; or the thickness of the sub-emitter layer is 800 nm, and the doping material is Si and the Si doping concentration is 4e18 cm.sup.−3, but the present invention is not limited to such application.

[0048] A compound emitter layer F is located on the sub-emitter layer 12.

[0049] The sub-emitter layer 12, the compound emitter layer F forms an emitter layer E; in this embodiment, the compound emitter layer F is composed of a first emitter layer 13 and a second emitter layer 14, and second emitter layer 14 is arranged on the first emitter layer 13, the material of the second emitter layer is N.sup.−InGaP and the N.sup.−InGaP is disordered with 49% Indium composition and the thickness is 30-60 nm, and the doping material is Si and the Si doping concentration is 5e16-5e17 cm.sup.−3, or the thickness of the second emitter layer 14 is 50 nm, and the doping material is Si and the Si doping concentration is 3e17 cm.sup.−3, but the present invention is not limited to such application.

[0050] A base layer 15 is located on the compound emitter layer F, in this embodiment, the material of the base layer 15 is P.sup.+GaAs, P.sup.+InGaAs, or a combination thereof, the thickness of the base layer 15 is 40-120 nm, and the doping material is C and the C doping concentration is 1e19-1e20 cm.sup.−3, or the thickness of the base layer 15 is 80 nm, and the doping material is C and the C doping concentration is 3e19 cm.sup.−3, but the present invention is not limited to such application.

[0051] A collector ledge layer 16 is located on the base layer 15, in this embodiment, the material of the collector ledge layer 16 is N.sup.−InGaP, the N.sup.−InGaP is ordered with 49% Indium composition, the thickness of the collector ledge layer 16 is 0.4-100 nm, and the doping material is Si and the Si doping concentration is 5e16-5e17 cm.sup.−3, or the thickness of the collector ledge layer 16 is 5 nm, and the doping material is Si and the Si doping concentration is 3e17 cm.sup.−3, but the present invention is not limited to such application.

[0052] A collector layer 17, is located on the collector ledge layer 16, in this embodiment, the material of the collector layer 17 is N.sup.−GaAs, and the collector layer 17 has the functions of optimizing the base-collector capacitance, the base-collector breakdown voltage, the Kirk effect, and the ruggedness of the transistor 10, but the present invention is not limited to such application.

[0053] A collector cap layer 18, is located on the collector layer 17, in this embodiment, the material of the collector cap layer 18 is N.sup.+GaAs or N.sup.+InGaAs, with the Indium composition greater than or equal to 50%, and the collector cap layer 18 has the function of forming a low-resistance contact to the collector metal, but the present invention is not limited to such application.

[0054] Referring to FIG. 1, the substrate 11, the sub-emitter layer 12, the compound emitter layer F, the base layer 15, the collector ledge layer 16, the collector layer 17, and the collector cap layer 18 form a semiconductor structure S, the surface of the semiconductor structure S is coated with a first SiN insulating layer D.sub.1.

[0055] Referring to FIG. 2, the first SiN insulating layer D.sub.1 is patterned and etched followed by an etch through the collector layer 17 and the collector cap layer 18 with the etch stopping on the collector ledge layer 16, so the collector layer 17 and the collector cap layer 18 form a first mesa M.sub.1.

[0056] Referring to FIG. 3, an etch through the collector ledge layer 16, the base layer 15 and the compound emitter layer F, to make the collector ledge layer 16, the base layer 15 and the compound emitter layer F form a second mesa M.sub.2, the first mesa M.sub.1 is smaller than the second mesa M.sub.2.

[0057] Referring to FIG. 4, a lateral oxidation region 19 is forming at the outer region R.sub.1 of the compound emitter layer F to form a current blocking region B, and the outer region R.sub.1 of the compound emitter layer F surrounds the inner region R.sub.2 of the compound emitter layer F to form a current aperture L, therefore, the present invention forms a current aperture L by the lateral oxidation of AlGaAs with high Aluminum content, the high Aluminum content Al.sub.xGa.sub.1-xAs has an Aluminum content x between 0.80 to 0.98.

[0058] Referring to FIG. 5, a second SiN insulating layer D.sub.2 is deposited to protect the semiconductor structure S and the lateral oxidation region 19, and a first via hole T.sub.1 is etched in the second SiN insulating layer D.sub.2.

[0059] Referring to FIG. 6, an emitter metal 101 is deposited inside the first via hole T.sub.1, the emitter metal 101 is formed on the sub-emitter layer 12, and the emitter metal 101 is an alloy material and the sub-emitter layer 12 is made of N.sup.+GaAs for forming a good ohmic contact.

[0060] Referring to FIG. 7, an isolation implant region 104 is formed by implanted ions going through the second SiN insulating layer D.sub.2 and into the sub-emitter layer 12. The isolation implant region 104 extends through the sub-emitter layer 12 into the substrate 11. The implant region 104 will prevent current flow between adjacent devices. In this embodiment, the isolation implant region 104 is compose of Boron, Argon, Hydrogen, Helium, Aluminum, or combination thereof, but the present invention is not limited to such application.

[0061] Referring to FIG. 8, a second via hole T.sub.2 is etched through the second SiN insulating layer D.sub.2, and deposit a base metal 102 is deposited inside the second via hole T.sub.2, the base metal 102 is formed on the collector ledge layer 16, and is diffused down to alloy the base metal 102 from the collector ledge layer 16 to the base layer 15 forming a good ohmic base contact. The lateral base metal contact to the collector ledge layer will form a Schottky contact. The material of the collector ledge layer 16 is N.sup.−InGaP and the material of the base layer 15 is P.sup.+GaAs, or the base metal 16 etch through the collector ledge 16 into the base layer 15 is performed, and a base metal 16 is deposited inside the etched region to connect to the base layer 15.

[0062] Referring to FIG. 9, a third via hole T.sub.3 is etched through the second SiN insulating layer D.sub.2, and a collector metal 103 is deposited inside the third via hole T.sub.3, the collector metal 103 is formed on the collector cap layer 18, and forms a good ohmic collector contact, the material of the collector cap layer 18 is N.sup.+InGaAs. Moreover, since the N.sup.+InGaAs is highly doped, it can be non-alloyed contact, but the present invention is not limited to such application.

[0063] Referring to FIG. 9, and by the steps disclosed in FIGS. 1-9 a heterojunction bipolar transistor 10 is completed. Also, as shown in FIG. 10, the electron current flow e from the emitter metal 101 to the base metal 102, is prevented by the current blocking region B which blocks the current and only allows the current flow through the current aperture L, but the present invention is not limited to such application.

[0064] Referring to FIG. 11A, the first emitter layer 13 includes a first emitter transition layer 131, an intermediate layer 132, and a second emitter transition layer 133, the second emitter transition layer 133 has the function of ballast resistance to improve thermal stability and RF performance of the transistor 10, and the first emitter transition layer 131 is made of N.sup.−GaAs, the second emitter transition layer 133 is made of N.sup.−GaAs and the material of the intermediate layer 132 is high Aluminum content Al.sub.xGa.sub.1-xAs, and the lateral oxidation region 19 is provided in the intermediate layer 132, and the lateral oxidation region 19 is N.sup.−AlGaAs with Aluminum content x between 0.80-0.98, in this embodiment, the thickness of the first emitter transition layer 131 is 20-100 nm, and the doping material is Si and the Si doping concentration is reduced from 4e18 to 3e17 cm.sup.−3; the thickness of the lateral oxidation region 19 is 0.4-2.5 nm, and the doping material is Si and the Si doping concentration is 0-6e18 cm.sup.−3; the thickness of the second emitter transition layer 133 is 20-100 nm, and the doping material is Si and the Si doping concentration is 5e16-5e17 cm.sup.−3; or the thickness of the first emitter transition layer 131 is 50 nm, and the doping material is Si and the Si doping concentration is reduced from 4e18 to 3e17 cm.sup.−3; the thickness of the lateral oxidation region 19 is him, and the doping material is Si and the Si doping concentration is 4e18 cm.sup.−3; the thickness of the second emitter transition layer 133 is 50 nm, and the doping material is Si and the Si doping concentration is 3e17 cm.sup.−3, but the present invention is not limited to such application.

[0065] Also, a first optional layer 134 is provided between the first emitter transition layer 131 and the intermediate layer 132, and a second optional layer 135 is provided between the intermediate layer 132 and the second emitter transition layer 133. The optional layers provide a smoother conduction band transition from the N.sup.−GaAs transition layers to the high Aluminum intermediate layers. The material of the first optional layer 134 and the second optional layer 135 are N.sup.−AlGaAs, but the present invention is not limited to such application.

[0066] Furthermore, the material of the intermediate layer 132 is high Aluminum content including AlGaAs and is highly resistive, therefore, the intermediate layer 132 needs to be thin for electron tunneling. The second emitter layer 14 is used to inject electrons into the base layer 15 and form a heterojunction between the base layer 15 and the second emitter layer 14, but the present invention is not limited to such application.

[0067] Referring to FIG. 11B, the collector layer 17 is composed of a first collector layer 171 and a second collector layer 172, and the thickness of the first collector layer 171 is 300-1200 nm, and the doping material is Si and the Si doping concentration is 1e17-2e14 cm.sup.−3, the thickness of the second collector layer 172 is 0-800 nm, and the doping material is Si and the Si doping concentration is 1e16-1e17 cm.sup.−3; the collector cap layer 18 thickness is 20-100 nm and the doping material is Si and the doping concentration is >1e19 cm.sup.−3; the collector transition layer 181 extends the second collector layer 172, the thickness of the collector transition layer 181 is 20-100 nm, and the doping material is Si and the Si doping concentration is larger than 1e19 cm.sup.−3; or the collector layer 17 is composed of a first collector layer 171 and a second collector layer 172, and the thickness of the first collector layer 171 is 900 nm, and the doping material is Si and the Si doping concentration is 2e15 cm.sup.−3, the thickness of the second collector layer 172 is 300 nm, and the doping material is Si and the Si doping concentration is 5e16 cm.sup.−3; the collector cap layer 18 further extends a collector transition layer 181, the collector transition layer 181 further extends the second collector layer 172, the thickness of the collector transition layer 181 is 50 nm, and the doping material is Si and the Si doping concentration is larger than 1e19 cm.sup.−3. The material of the collector transition layer 181 is N.sup.+InGaAs, and the Indium concentration is 0.50, but the present invention is not limited to such application. The material of the collector cap layer 18 is N.sup.+InGaAs and the Indium composition is 0.50 to 0.65. The thickness of the collector cap layer 18 is 50 nm, and the doping material is Si and the Si doping concentration is larger than 1e19 cm.sup.−3.

[0068] Referring to FIG. 12, in another embodiment, a back-side metal 20 is arranged on the second surface 112 of the substrate 11, and the substrate 11 and the sub-emitter layer 12 have a back-side via hole 21 for making the back-side metal 20 be electrically connected to the emitter metal 101 by the back-side via hole 21. Referring to FIGS. 13-14, in another embodiment, a dielectric passivation layer P is coated on the heterojunction bipolar transistor 10, the dielectric passivation layer P has a via hole T and within the via hole T, an under bump metal 30 is deposited which directly connects to the collector metal 103, whereby the heat flow emitted from the heterojunction bipolar transistor 10 can be conducted through the under bump metal 30 into a bump 40, in this embodiment, the bump 40 is deposited on the dielectric passivation layer P and the under bump metal 30, the bump 40 can be used as a thermal bump to improve the efficiency of removing heat and can be flip-chip mounted onto a circuit board, mounted to a board within a module or mounted or stacked on top of another die, but the present invention is not limited to such application.

[0069] Moreover, at the junction of the base layer 15 and the second emitter layer 14, the N.sup.−InGaP of the second emitter layer 14 is disordered or ordered, and the energy bandgap is between 1.85 to 1.90 eV; at the junction of the base layer 15 and the collector ledge layer 16, the N.sup.−InGaP of the collector ledge layer 16 is ordered, and the energy bandgap is approximately 1.85 eV, but the present invention is not limited to such application.

[0070] With the features disclosed above, the present invention having the collector arranged on the top, since the base-collector junction area is smaller, the capacitance of the base-collector junction is reduced. The lateral oxidation in the emitter reduces electrons to be injected outside of the current aperture resulting in better performance of the transistor 10 and also reduces the base-emitter junction area and the base-emitter junction capacitance, and the base in the lateral oxidation region 19 is protected. The collector ledge layer 16 covering the base layer 15 is used to prevent the base layer 15 from being exposed, and further prevents surface electron trapping and recombination improving the reliability of the transistor 10. The base metal 102 diffuses down through the collector ledge layer 16 to the base layer 15, thereby permitting the collector ledge layer 16 to protect the base layer 15. The N.sup.−InGaP material of the collector ledge layer 16 needs to be ordered, in order to achieve no conduction band discontinuity which can block and reduce electron flow from the base to the collector.

[0071] Although particular embodiments of the invention have been described in detail for purposes of illustration, various modifications and enhancements may be made without departing from the spirit and scope of the invention. Accordingly, the invention is not to be limited except as by the appended claims.